JPH02179993A - Computer system - Google Patents

Abstract

PURPOSE:To increase a processing speed by delivering the refresh operation of a memory circuit with a built-in refresh circuit to the built-in refresh circuit, and executing the refresh operation of the memory circuit having no built-in refresh circuit by means of an independent external refresh circuit regardless of the processing of a CPU. CONSTITUTION:A memory circuit 12 with the built-in refresh circuit, which executes the refresh operation in synchronization with the processing of a central processing unit 11, is adopted, and the refresh operation is delivered to the built-in refresh circuit. On the other hand, for a memory circuit 13 which has no built-in refresh circuit, an external refresh circuit 14 is provided, the external refresh circuit 14 applies a refresh command signal to the respective memory circuits 13 having no built-in refresh circuits asynchronously from the processing of the central processing unit 11, and execute refreshing. As a result, the stop of the central processing unit 11 processing in the refresh operation is suppressed. Thus the processing speed of the whole system can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a memory circuit (D
RAM; dynamic random acc
The present invention relates to a computer system in which a memory circuit that does not have a built-in refresh circuit and that requires a refresh operation coexists with a memory circuit that does not have a built-in refresh circuit and requires a refresh operation.

[Prior Art] Even for computer systems used in products that have been designed and commercialized, improvements are frequently made with the aim of increasing functionality.

Improvements aimed at increasing functionality can sometimes lead to insufficient memory capacity. In this case, new memory circuits are added to existing memory circuits, or some of the existing memory circuits are replaced. Memory circuits may be replaced with memory circuits with larger capacity.

The memory circuits that require the addition or replacement of memory circuits in this way are often those used as the main memory of the system, that is, the so-called DR.
Most common in AM. In this case, at the initial design W1 stage, DRAM without a built-in refresh circuit was the mainstay, but at the current stage when the need to add or replace memory circuits has arisen, refresh circuit Built-in types are becoming more popular.

Even if an existing design is developed, there are some computer systems in which it is difficult to replace the original memory circuit with a current memory circuit with different specifications. There are computer systems that include memory circuits from the initial design stage that do not include built-in circuits.

FIG. 2 shows a computer system in which such memory circuits are mixed. In FIG. 2, a central processing unit (CPU) 1 accesses first and second memory circuits 2 and 3 as necessary when executing various processes.

Here, the first memory circuit 2 consists of a DRAM with a built-in refresh circuit and a memory control circuit that controls the DRAM, and the second memory circuit 3 consists of a DRAM that does not have a built-in refresh circuit and a memory control circuit that controls the DRAM. It consists of a memory control circuit.

Refreshing of the first and second memory circuits 2 and 3 are both controlled by a refresh circuit 4. That is, the refresh circuit 4 outputs a bus request signal to the CPUI at the timing when refresh is required, and upon receiving the bus permission signal sent by the CPUI in response, it transmits the refresh timing and address to both memory circuits 2 and 3. Sends a refresh command signal to instruct the CPU.
Memory circuits 2 and 3 were refreshed while the process of memory circuit 1 was stopped.

Note that the first memory circuit 2 has a built-in refresh circuit, but in order to treat the refresh operation of the first and second memory circuits 2 and 3 the same as other operations, an external The refresh circuit 4 also refreshes the first memory circuit 2.

[Problem to be solved by the invention] However, in the above-mentioned conventional system, the first and second
The refresh operation of memory circuits 2 and 3 is performed by the CPU
Since it is executed while the CPU is stopped, the operating rate of the CPU is lowered and the processing speed of the entire system is slowed down.

The present invention has been made in consideration of the above points, and includes a memory circuit with a built-in refresh circuit and a refresh r:gi
To provide a computer system that is capable of improving the processing speed of the entire system compared to conventional systems by suppressing the influence of refresh operations of these memory circuits on CPU processing even when memory circuits that do not have built-in memory circuits coexist. This is what we are trying to provide.

[Means for Solving the Problems] In order to solve the problems, the present invention provides a central processing unit, at least one memory circuit that requires a refresh operation and includes a refresh circuit, and a memory circuit that requires a refresh operation. In a computer system equipped with at least one or more memory circuits that do not have a built-in refresh circuit, each memory circuit with a built-in refresh circuit is configured to refresh in synchronization with the processing of a central processing unit. For each memory circuit without a built-in refresh circuit, an external refresh circuit is provided that sends a refresh command signal asynchronously to the processing of the central processing unit.

[Operation] The present invention relates to a computer system in which at least one memory circuit with a built-in refresh circuit and at least one memory circuit without a built-in refresh circuit coexist.

For the memory circuit with a built-in refresh circuit, the built-in refresh circuit performs a refresh operation in synchronization with the processing of the central processing unit, and the refresh operation is entrusted to the built-in refresh circuit.

On the other hand, for memory circuits without a built-in refresh circuit, an external refresh circuit is provided, and this external refresh circuit gives a refresh command signal to each memory circuit without a built-in refresh circuit asynchronously with the processing of the central processing unit. I tried to refresh it.

As a result, the number of times that the processing of the central processing unit is stopped due to refresh operations can be significantly reduced compared to conventional systems, and the processing speed of the entire system can be improved.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, in this embodiment as well, first and second memory circuits 12 and 13 are provided as memory circuits accessed by a central processing unit (CPU) 11.

One of the memory circuits 12 has a built-in refresh circuit that follows the so-called hidden refresh method, which performs a refresh operation without receiving a refresh command signal by changing the logic level of a column address strobe (CAS) signal after access. It is a memory circuit. The other memory circuit 13 does not have a built-in refresh circuit, and performs a refresh operation when a refresh command signal is applied from an external refresh circuit 14.

The refresh circuit 14 outputs a refresh command signal to the second memory circuit 13 at a predetermined period, asynchronously with the processing of the CPU II. Note that by sending the refresh command signal asynchronously, the access operation command from the CPU 11 to the second memory circuit 13 and
There may also be a case where the refresh command signal from the refresh circuit 14 conflicts with the refresh command signal. So, refresh times &81
The refresh circuit 14 monitors the states of these memory address signals and memory access signals output from the CPU II, and conflicts with the sending timing of the refresh command signal. In this case, the CPU
II and sends a wait request signal to the second memory circuit 1.
3 makes the CPU II wait until the refresh process is finished.

In the above configuration, the CPU II outputs a memory address signal to the first memory circuit 12 as necessary,
It also outputs a memory access signal instructing a read or write state. Such memory address signals and memory access signals are provided to the first memory circuit 12, the second memory circuit 13, and the refresh circuit 14.

In this case, the memory address signal is transmitted to the first memory circuit 12.
Therefore, the second memory circuit 13 does not perform any operation (except for refresh operation), and
The refresh circuit 14 does not perform competition control even at the sending timing of the refresh command signal.

On the other hand, the first memory circuit 12 executes the read or write operation indicated by the memory access signal to the area of the specified address. That is, data on a data bus (not shown) is stored in an area of a designated address, or data stored in a designated address area is outputted to a data bus (not shown).

When the data exchange between the CPU 11 and the first memory circuit 12 is thus completed under the control of the CPU 11, the CPU II returns the column address strobe signal and the like to the initial state. When the first memory circuit 12 detects a change in the logic level of the column address strobe signal after access, it activates a built-in refresh circuit to perform a refresh operation.

In addition, the CPU II connects the second memory circuit 1 as necessary.
It outputs a memory address signal for No. 3, and also outputs a memory access signal instructing a read or write state. Such memory address signals and memory access signals are transmitted to the first memory circuit 12 and the second memory circuit 13.
and the refresh circuit 14.

At this time, the first memory circuit 12 does not perform any processing because the memory address signal is unrelated to the memory circuit 12 concerned.

The refresh circuit 14 performs an operation of sending a refresh command signal to the second memory circuit 13 at a predetermined period. At the sending timing of the refresh command signal, as described above, the second memory circuit 13
Upon receiving the memory address signal and memory access signal indicating the area of CP, the refresh circuit 14
A wait request signal is given to U11 to stop sending out the memory address signal and memory access signal, and a refresh command signal is sent to the second memory circuit 13.

When the second memory circuit 13 receives a memory address signal and a memory access signal indicating an area of the memory circuit 13, it waits for a period during which these signals may be stopped, and then performs the operation instructed by the memory access signal. ,
Executes for the area indicated by the address signal.

In addition, when the second memory circuit 13 receives a refresh command signal, including after the memory address signal and the memory access signal have stopped, the second memory circuit 13 executes a refresh operation for the area specified at the timing specified by the refresh command signal. do.

In addition, when the above-mentioned refresh circuit 14 stops sending the memory address signal and the memory access signal to CFULL, it stops sending the wait request signal to the CPU 11 when it finishes sending the refresh command signal. The CPU II then sends out the memory address signal and memory access signal again.

Therefore, according to the above embodiment, when the CPU II attempts to perform an access operation on the second memory circuit 2813, the refresh circuit 14 simultaneously causes the second memory circuit 13 to refresh at that timing. Only in this case, the CPU 11 is stopped for refresh operation, and in other cases, it can continue to operate, so the operating rate can be further increased compared to the past, and the overall system Processing speed can be improved.

Note that in the above embodiment, the second memory circuit 13
In the above example, when there is a conflict between a refresh operation request and an access request, the access operation is stopped to control the conflict. It may be controlled.

Furthermore, in the above embodiment, the refresh circuit 1814 also controls the contention, but the contention may be controlled by a separate independent circuit. The contents are as described above.

Furthermore, in the above-described embodiment, the application is applied to a computer system in which one memory circuit with a built-in refresh circuit and one memory circuit without a built-in refresh circuit coexist; however, a memory circuit with a built-in refresh circuit, The present invention can be applied to a device in which at least one memory circuit without a built-in refresh circuit coexists, and the total number of memory circuits is not limited to two. Furthermore, it can be applied to systems in which the methods are mixed, and the process leading to the mixing does not pose any problem.

[Effects of the Invention] As described above, according to the present invention, the refresh operation of a memory circuit with a built-in refresh circuit is entrusted to the built-in refresh circuit, and the refresh operation of a memory circuit without a built-in refresh circuit is entrusted to an independent external refresh circuit. Since the processing is performed independently of the CPU processing, it is possible to obtain a computer system in which the CPU operation rate is increased and the processing speed is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a computer system according to the present invention, and FIG. 2 is a block diagram showing a conventional system. 11...Central processing unit (CPU), 12...Memory circuit with built-in refresh circuit, 13...Memory circuit without built-in refresh circuit, 14...External refresh circuit.

Claims (1)

[Claims] Requiring a central processing unit and a refresh operation,
In a computer system comprising at least one memory circuit with a built-in refresh circuit and at least one memory circuit without a built-in refresh circuit that requires a refresh operation, each of the above memory circuits with a built-in refresh circuit In addition to applying a refresh operation in synchronization with the processing of the central processing unit, to each of the above memory circuits without a built-in refresh circuit,
A computer system comprising an external refresh circuit that sends a refresh command signal asynchronously with the processing of the central processing unit.