JPH02222052A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To attain the direct memory access(DMA) control even in a system where no memory is shared between two CPUs by switching the buffers with an FF whose output is inverted for each memory access. CONSTITUTION:When the output of an FF 10 is set at 1 by a preset signal PRST, a buffer and bidirectional buffers 3/7 and 4/8 are set in the enable and disable states respectively. Therefore the address received from a DMA controller 9 is supplied to a RAM 5 only via the buffer 3. The read data received from the RAM 5 is stored in a register of the controller 9 via the buffer 7 with no conflict produced with the data on a RAM 6 since the buffer 8 is kept disable. When a reading job is over and a memory read control signal MRC has a fall, the Q output of an FF 10 is inverted with the states of buffers 3/7 and 4/8 also inverted. Thus the data can be written into the RAM 6 with no conflict, and the DMA control is attained between two CPUs which share no memory.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides direct memory access (hereinafter referred to as
The present invention relates to a DMA control device for performing transfer (referred to as DMA), and particularly relates to a DMA control device used in a system equipped with two central processing units (hereinafter referred to as CPUs).

[Prior Art] Conventionally, DMA transfer between memories has been performed by the following procedure. That is, first, the DMA controller sends a hold request to the CPU. When the hold approval signal from the CPU that receives this is input to the DMA controller,
Since the address bus and data bus are empty, the DM
Send the address from the A controller to the address bus,
As a result, data read from a specific memory onto the data bus is written to another memory.

Furthermore, in a system where two CPUs share memory, a hold signal is sent to the two CPUs,
DMA transfer is basically performed in the same procedure as above, except that hold approval signals are input from the two CPUs.

[Problems to be Solved by the Invention] However, when the conventional DMA controller described above is used in a system in which memory is not shared between two CPUs, addresses may overlap between the memories.
There is a problem in that multiple reading from a plurality of memories and multiple writing to a plurality of memories occur, making it impossible to properly perform MA transfer.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a DMA control device that can perform DMA transfer control even in a system in which memory is not shared between two CPtJs.

[Means for Solving the Problems] A direct memory access control device according to the present invention includes a first memory accessed from a first central processing unit;
a direct memory access control unit that is provided between a second memory accessed by a second central processing unit and performs direct access control between the first and second memories; first and second buffers respectively inserted in an address bus and a data bus between the direct memory access control unit; and an address bus and a data bus between the second memory and the direct memory access control unit. 3rd and 4th respectively inserted in
a buffer, the output of which is initialized and selectively activates the first and second buffers and the third and fourth buffers prior to direct memory access; The present invention is characterized in that it includes memories for the first and second memories, and a flip-flop circuit whose output is inverted each time it is reaccessed.

[Operation] According to the present invention, a flip-flop circuit that inverts its output every time a memory is accessed selectively activates the first and second buffers and the third and fourth buffers. The first and second buffers are inserted into an address bus and data bus between the DMA control unit and the first memory, and the third and fourth buffers are inserted between the DMA control unit and the second memory. It is inserted into the address bus and data bus between the Therefore, the first memory and the second memory are accessed alternately by the DMA control unit, and data is not read from or written to both memories at the same time.

Therefore, according to the present invention, even in a system where two CPUs do not share memory, DMA transfer control is performed by repeating the operation of reading data from one memory and writing it to the other memory. be able to.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a system including a DMA control device according to an embodiment of the present invention.

The DMA control device of this embodiment includes a RAM (random access memory) 5 accessed by the CPU 1,
DMA with RAM6 accessed by CPU2
It controls transfer control and is configured as follows.

That is, a DMA controller (hereinafter referred to as DMAC) 9
is the main body of this DMA control device, and the CPU
, 2, and sends a hold request signal HLDRQ to the CPUI.
, AND of the hold acknowledge signal HLDAK1.2 from 2
When the logical product HLDAK from gate 15 is input, D
Access RAM5.6 for MA transfer. This D
The address bus 21 and data bus 22 between the MAC 9 and the RAM 5 each have a buffer 3 with an enable terminal.
and a bidirectional buffer 7 are inserted.

Also, the address bus 2 between -DMAC9 and RAM6
A buffer 4 and a bidirectional buffer 8 each having an enable terminal are inserted into the data bus 1 and the data bus 22, respectively.

The enable states of these buffers 3, 4, 7, and 8 are controlled by a flip-flop 10 with a preset input. The flip-flop 10 is reset and preset at the falling edge of the reset signal R3T and the preset signal PR3T, and outputs a hold acknowledge signal HLDAK from the AND gate 15, a memory write control signal MWC during DMA transfer, and a memory write control signal MWC during DMA transfer. The logical product result of the AND gate 11 with the read control signal MRC is input as a clock signal, and the output Q is inverted at the rising edge of the clock signal. This output Q is the OR gate 12
It is also input to one input of the OR gate 14 via the inverter 13. Further, an inverted signal of the hold acknowledge signal HLDAK by the inverter 16 is input to the other input of the OR gate 12.14. The output of the OR gate 12 is input to the enable terminals of the buffer 4 and the bidirectional buffer 8, and the output of the OR gate 14 is input to the enable terminals of the buffer 3 and the bidirectional buffer 7.

Next, the operation of the DMA control device of this embodiment configured as described above will be explained.

First, D from RAM5 of CPU1 to RAM6 of CPU2.
The case of performing MA transfer will be explained with reference to the timing diagram of FIG. 2.

In this case, the preset signal PR3T is applied to the flip-flop 10 by the I10 command, and the output Q is set to "1".

Subsequently, the DMAC9 outputs a hold request signal HLDRQ to the CPUI,2. In response to this, the CPU
1.2, a hold approval signal HLDAKI,2 is output. Then, a hold approval signal HLDAK, which is the logical product of these, is output from the AND gate 15, and the DM
When input to AC9, in response to this, DMAC9 outputs read address AD to address bus 21 and sends address strobe signal ADSTB to buffers 3 and 4.
Output. At this time, the output Q of the flip-flop 10
is "1", so buffer 3.7 is enabled and buffer 4.8 is disabled.

Therefore, no address is supplied to RAM6, and RAM5
Addresses are provided only to

Next, when the memory read control signal MRC falls, data is read from the RAM 5, and this data is transferred to the DMAC 9 via the bidirectional buffer 7 and the data bus 22.
is stored in a temporary register (not shown). In addition,
At this time, although the bidirectional buffer 8 is in a disabled state, the data read from the RAM 5 does not collide with the data read from the RAM 5.

When the reading is completed, the flip-flop 10 is inverted at the rising edge of the MRC signal, and the output Q becomes "O". This switches the enable states of the buffers, with buffers 3 and 7 being disabled and buffers 4 and 8 being enabled. From this state, the DMAC 9 starts a write operation. That is, first, the DMAC 9 outputs the write address AD to the address bus 21. This address is given only to RAM6. Then, at the fall of the memory write control signal MWC, the RA is transferred from the temporary register of the DMAC 9 via the data bus 22 and the bidirectional buffer 8.
Data is written to M6.

When the writing to the RAM 6 is completed and the memory write control signal MWC rises, the output Q of the flip-flop 10 becomes "1" again, and the buffer 3.7 is enabled.
Buffers 4 and 8 are disabled.

By repeating this operation by the number of bytes initialized in the DMAC 9, the DMA transfer of data from the RAM 5 to the RAM 6 is completed.

Also, D from RAM6 of CPU2 to RAM5 of CPUUI.
When performing MA transfer, the reset signal R3T is generated by the I10 command, the flip-flop block 10 is reset and the output Q is set to "O", and then the DMA transfer operation is started, and the procedure is exactly the same as above. DMA transfer from RAM 6 to RAM 5 can be performed with DMA transfer; when DMA transfer is not being performed, hold acknowledge signal HLDAK is "0", so buffers 3, 4, 7, .
8 are all in a disabled state, no bus contention occurs, and both the CPUI and CPtJ2 operate normally.

[Effects of the Invention] As explained above, according to the present invention, the output of the flip-flop is inverted every time a memory is accessed, and buffer switching is performed using this output to prevent data contention on the bus. , DMA transfer control can be performed even in a system in which memory is not shared between two CPUs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a DMA control device according to an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the device.

Claims (1)

[Claims] (1) Provided between a first memory accessed from a first central processing unit and a second memory accessed from a second central processing unit, and between these first and second memories. a direct memory access control unit that performs direct access control; first and second buffers respectively inserted in an address bus and a data bus between the first memory and the direct memory access control unit; a third memory inserted into the address bus and the data bus between the second memory and the direct memory access control unit, respectively;
and a fourth buffer, the output of which is initialized and selectively activates the first and second buffers and the third and fourth buffers prior to direct memory access. . A direct memory access control device further comprising a flip-flop circuit whose output is inverted each time the first and second memories are accessed.