JPH02181516A - Test circuit for counter - Google Patents

Abstract

PURPOSE:To shorten the test time of a counter circuit having the large number of bits by providing the subject circuit with a mode switching means for selecting either one of a route for successively starting counters and a route for collectively starting all the counters and a logical processing circuit for finding out the AND of carries. CONSTITUTION:The test circuit is provided with the mode switching means for selecting either one of the route for successively starting 4-bit counters 11 to 14 constituting a 16-bit counter circuit to that a carry '1' outputted simultaneously with the end of the counting of the prestage counter 11 is inputted to the succeeding counter 12 to start the succeeding counter 12 and the route simultaneously inputting signals starting the counters 11 to 14 to all the counters 11 to 14 to collectively start all the counters 11 to 14 and the logical processing means for finding out the AND of carries outputted simultaneously with the end of counting of respective counters 11 to 14. When the processed result of the logical processing means is '1', the operation of the counter circuit is decided as normal operation. Thus, the test time can be sharply shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a counter test circuit for testing the operation of a counter in a gate array.

(Prior art) Conventionally, for example, a 4-bit counter in a gate array is
When performing an operation test of a 16-bit counter circuit constructed using individual counters, it takes 2161 clocks for a carry to be output from the fourth stage counter, which is the final stage. Furthermore, it took 215 clocks to invert all the data input to the counter circuit.

Therefore, as the number of bits in the counter circuit increases, the time required to obtain a test result increases exponentially, resulting in the inconvenience that the test takes too much time.

(Problem to be Solved by the Invention) Conventionally, when performing an operation test of an n-bit counter circuit configured using a plurality of m-bit counters in a gate array, if the number of bits of the counter circuit becomes large, As you can see, the drawback was that testing took a long time. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a counter test circuit that eliminates the above-mentioned drawbacks and can reduce the test time for a counter circuit with a large number of bits.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides an n-bit counter circuit configured using a plurality of m-bit counters, in which a carry (“ 1) is input to the next stage counter and the next stage counters are activated one after another, or a signal to start the counters is input to all counters at the same time and all counters are activated at once. The present invention has a configuration comprising a mode switching means for selecting a carry, and a logic processing means for calculating a logical product of the carries outputted when each counter finishes counting.

(Function) In the counter test circuit of the present invention, the mode switching means inputs a signal (“1”) for starting the counters to all counters at the same time, selects a path for starting all the counters at once, and switches the counter circuit. Set to test mode. As a result, each counter constituting the counter circuit simultaneously counts the separately loaded initial value, and upon completion of counting, outputs a carry to the logic processing means. The logic processing means performs a logical product of the carries outputted when each counter finishes counting. If the processing result of this logic processing means is "1 pass", it is determined that the operation of the counter circuit is normal.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. The figure is a block diagram showing an embodiment of the counter test circuit of the present invention. 11 to 14 are 4-bit counters forming a 16-bit counter circuit; 21 to 23 are selectors for switching the counter circuit to either normal mode or test mode; and 3 is a carry 201 output from the counters 11 to 14. It is an AND gate that performs the logical product of ~204. Note that the test circuit for the counter is the selector 21.
.about.23 and AND gate 3 are connected to the 16-bit counter circuit.

Next, the operation of this embodiment will be explained. Counter 11~
A clock 100 is input to the 14 CK terminals, and each counter performs a counting operation based on this clock 100.

The mode switching signal 50 is connected to the SL terminal of the selectors 21 to 23.
is input and this signal 50 is a normal mode signal, the selectors 21 to 23 select the signal on the terminal X side and output it from the terminal Z to the CI terminals 12 to 14 of the counter. Data is loaded into each counter by a load signal (not shown), and when an activation signal of "1" is given to the CI terminal of the first stage counter 11, this counter 11
starts working. When this counter 11 finishes counting, it outputs a carry 201 (“1”) from the CO terminal, and this carry 20,1 is input to the CI terminal of the next stage counter 12 via the selector 21. starts its operation, and when it finishes counting, it outputs a carry 202 from the CO terminal. This carry 202
is input to the CI terminal of the counter 13 via the selector 22, and the counter 13 starts its operation.

The same goes for the rest, and finally, the operation of the counter 14 is started,
When the operation of the counter 14 is completed, a carry 204 is output from the CO terminal, and counting of all 16 bits of data is completed, and the count result is output from the flea counter. Thereafter, each counter is cleared by a clear signal (not shown) and returns to its initial state.

Next, when the mode switching signal 50 input to the terminal SL of the selectors 21 to 23 is a test mode signal, the selectors 21 to 23 select the activation signal "1" input to the terminal Y and send it to the terminal Z. Then, the output is switched to the CI terminals of the counters 12 to 14. After zero data is loaded into each counter as an initial value in this state, when "1" is applied to the CI terminal of the counter 11 and "1" is applied to the Y terminals of the selectors 21 to 23, the counter 11 ~14 CI terminals are simultaneously input with ``1'', and each counter starts counting at the same time. Each counter starts counting when 24-1 clocks are input from each GK terminal. When finished, carry “1” from each CO terminal.
201 to 204 are output to the AND circuit 3 all at once. Therefore, the AND circuit 3 receives the input carries 201 to 20.
Only when all 4 are "1", the output is set as "1",
Indicates that the counter circuit operates normally.

Note that when at least one of the carries 201 to 204 is "O", the output of the AND circuit 3 remains O", indicating that the operation of the counter circuit is abnormal. That is,
The output of the AND circuit 3 is "O" until the 15th clock, indicating that the counter circuit is normal, "1", indicating an abnormality in the counter circuit, and "Opt" from the 16th clock onwards, indicating an abnormality in the counter circuit. If it is "1", it indicates that the counter circuit is normal.

According to this embodiment, the normality/normality of the 16-bit counter circuit
The abnormality test can be performed in 24-1 clock times, and the test time can be significantly reduced compared to the conventional method. Note that when the present invention is applied to an n-bit counter circuit using one m-bit counter, 2
- The above test can be performed in one clock time, and the same effect as in the above embodiment is obtained.

[Effects of the Invention] As described above, according to the counter test circuit of the present invention, the test time for a counter circuit with a large number of bits can be reduced.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the counter test circuit of the present invention. '+1.12.13.14...Counter 21.22,
23... Selector 3... AND circuit agent Patent attorney Nori Chika Ken Yudo Sanno -

Claims (1)

[Claims] In an n-bit counter circuit composed of multiple m-bit counters, a carry (“1”) output when the previous stage counter finishes counting is input to the next stage counter, and the next stage counter is sequentially activated. mode switching means for selecting either a path for activating the counters or a path for simultaneously inputting a signal for activating the counters to all counters to activate all the counters at once; 1. A counter test circuit comprising: logical processing means for calculating the AND of carries.