JPH02185104A - Fm demodulator - Google Patents

Abstract

PURPOSE:To obtain an FM demodulator of high precision by taking the difference of phase after correcting the phase of an input FM wave at the time when the phase of the FM wave detected by a phase detector decides that the phase of the input FM wave is not correct. CONSTITUTION:The output of a phase detector 10 is delayed in a delay corrector 14 by the same delay time as a signal outputted from a control signal generator 13. An output phiK of the delay corrector 14 is inputted to a phase corrector 15, and the corrector 15 outputs phiK+pi(mod2pi) when the output signal from the control signal generator 13 is significant '1', but the corrector 15 outputs phiK when it is insignificant '0'. A subtractor 6 subtracts the output of a delay device 5 from the output of the phase corrector 15. A discontinuity corrector 7 adds 2pi to the output and outputs it only when the output of the subtractor 6 is negative. Consequently, the output of the discontinuity corrector 7 is converted to an analog signal by a D/A converter 8 to obtain the demodulation output of an FM signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM demodulator that converts an analog FM signal into a digital signal and demodulates it.

[Prior Art] When the analog FM signal for timekeeping is defined as X (tl), and the signal Y (L) is obtained by shifting the phase of this signal by 90°, the signal F (t) obtained by demodulating the signal X (L) is given by It has been known for a long time that the phase of the FM wave in this case is represented by φ(1), then the formula ■ can be expressed as follows.This can be realized by hardware using digital signal processing technology. The configuration of a conventional F'' MI adjuster is shown in FIG.

In the figure, (1) is a sampling period D/D converter that converts a human-powered analog FM signal into a digital signal, and the digitized FM signal is shifted by 90° by a 90° phase shifter (3). The phased signal Y is obtained.On the other hand,
The output of the A/D converter (1) is input to a delay compensator (2). The delay compensator (2) is for delaying the digital FM signal by the same amount as the delay time of the signal Y generated by the 90° phase shifter (3). The output Y of the phase shifter (3) can be regarded as a signal converted into M-r at the same time. (4) is t, a n −' (X
/Y) is an arithmetic unit that performs the fiif calculation, and is a delay compensator (2).
The 90° phase shifter (3) and the arithmetic unit (4) constitute a phase detector (10) that detects the phase of the FM wave.

(5) is a delay device that delays the output of the phase detector (10) by 1 sampling period, and (6) is a subtracter that subtracts the output of the delay device (5) from the output of the arithmetic unit (4). .

The arithmetic unit (4) of this embodiment uses, for example, a ROM whose input addresses are signals X and Y, and its R
As the contents of OM, the configuration is such that the value of arc tangent for X/Yl is held.In this way, for the single-powered numbers
n −' (X/Y) can be obtained.

The output of this phase detector (10) is expressed as the phase shift φ (K Tl ) of the FM wave at time t=K・1゛, as described above. if(
Hereinafter, this notation will be used for other than φ(K)), the output of the delay device (5) is φ(t1), and the output of the subtractor (6) is φ(ni)-φ(ni-1) It is. This is △φOt
).

(2) When T is sufficiently small, the formula can be approximated as follows, and since T is constant, the output △φ(ni) of the subtractor (6) will be similar to the demodulated signal F(ni),
In terms of α, the output Δφ of the subtractor (6) can be regarded as a demodulated signal.

However, the arc tangent is a periodic function, and
, Y, its period is 2π. Now, assuming that the table in the ROM has values from 0 to 2π, the original output of a n -' (X/Y) will be, for example, 1.9π at first, 2. When lπ, the output of the 1-phase detector (1G) is initially φ(K-1)
= 1, 9π, then φ(to) = 0.1π,
There is a problem in that the output of the subtracter (6) becomes negative and discontinuity occurs.

Therefore, the discontinuity corrector (7) performs correction by adding 2π to the output of the subtracter (6) only when the output becomes negative. In this way, the above-mentioned discontinuity will not occur in the output of the discontinuity corrector (7). Below,
The output of this discontinuity corrector (7) is assumed to be 5o(Kl).

Next, if the output of the discontinuity corrector (7) is converted into analog No. 4.1 by the D/A converter (8), an output obtained by demodulating the FM signal can be obtained.

[Problem to be solved by the invention] However, the A/D converter (1) is
The M wave is, for example, the F wave in the reproduction brightness signal system of a home VTR.
When an unbalanced FM wave, such as an M wave, passes through an FM transmission system with certain characteristics, including a reproducing RF equalizer, and the I2 side wave is emphasized and the upper side wave is suppressed,
It has been experimentally confirmed that in the conventional F'M demodulator shown in FIG. 15, the portion where the signal should rise from black to white may fall to black. FM like this
If the wave is directly output as an image via the D/A converter (8), it will look black and broken, resulting in an extremely difficult-to-understand image.

This phenomenon occurs in conventional analog FM demodulation.
This phenomenon is called an "inversion phenomenon," but from now on, it will also be called an "inversion phenomenon" in digital demodulation.

This "inversion phenomenon" will be explained using FIG. Assume that the modulation signal is a sine wave as shown in FIG. FM this
The FM wave after demodulation is not shown in Figure 3. F' M in Figure 3
When the upper wave of the wave is emphasized and noise is added, the waveform becomes such that the cello cross point disappears as shown in FIG. When the distorted FM waves are input manually, a phase detector (l
The output φIK) of O) may not match the phase of the FM wave. That is, originally the output φ of the 1-phase detector (10)
(ni) represents the phase of the FM wave, so sinφ(ni) and
The input FM waves should have similar shapes, but when a distorted FM wave is input manually as shown in Figure 4, sinφ(ni) becomes the 5th wave.
It has been experimentally confirmed that the situation shown in the figure can occur. In such a case, the output from the D/A converter (8) will be as shown in FIG. 6, resulting in a one-inversion phenomenon. This means that at the time when the phase φ(to) is calculated, s i rlφ(
The direct cause is that the waveform of 2) looks like one cycle of the FM wave is missing.

The present invention was made to prevent such an inversion phenomenon, and an object of the present invention is to provide an FM demodulator that can obtain an easy-to-see image without causing an inversion phenomenon.

[Means for solving the problem] The FM demodulator according to the invention of claim (1) has an input [.'M
The phase φ of the wave is determined, and from the obtained phase φ, it is detected that the increase/decrease in sinφ and the increase/decrease in the phase φ of the FM wave do not match twice in a row, and after correcting the phase φ, the difference in the phase φ is calculated. It is configured to output.

In addition, the FM demodulator according to the invention of claim (2) has a human-powered F.
Determine the phase φ of the M wave, obtain sin φ from the determined phase φ, and if the increase/decrease in this sin φ and the increase/decrease in the phase of the 2 sample points after 1) of the FM wave do not match twice in a row In this case, after correction is made by adding π to the phase φ of the central sample point of the three sample points obtained by taking the two-time difference, the difference in phase φ is output.

[Operation] The FM demodulator according to the invention of claims (1) and (2) has the following features:
In either case, the phase of the human-powered 1-'M wave is determined, and if this phase does not correctly represent the phase of the human-powered [P-M wave, then after correcting it, the difference in the phase φ of the input FM waves before and after the and output it.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to the drawings. In FIG. 1, the same components as those in FIG. 10 will be described with the same reference numerals. In the figure, (11) is the first detector that detects an increase or decrease in s i r + φ with respect to the output No. 5 φ of the 1-phase detector (10), A second detector that detects the increase or decrease of No. 3 X,
(13) means that if the output of the first detector (Ill) and the output of the second detector do not match twice in a row, then Ij, 7i, "
A control signal S-) generator that outputs a signal of ``1'' when the signal is ``1'', and otherwise outputs a signal of yl (means ``0''), (+4
) is a delay corrector that delays the output φ (to) of the phase detector (10) by 1-, and the first and second detectors f111, Tl2
1 and the control signal generator (13) constitute a reversal position detector (16) that detects the reversal position of the FM wave position. (15) is the output of the control signal generator (13) (when the Th number is significant "1", π is added to the output of the delay compensator (14), and when the signal 51 is significant "0", it is delayed. This is a phase corrector that outputs the output of the corrector (14) as it is.

Next, the operation will be explained. AID converter (1)
The FM signal digitized by the 90° phase shifter (3)
The signal Y is phase-shifted by 90'.

On the other hand, the output of the Δ/D converter (1) is transmitted through the delay compensator (
2) and is delayed by the same amount as the delay time of the signal Y caused by the 90° phase shifter (3). Therefore, if the output X of the delay compensator (2) at time t, = K・1゛ is set to is Y(Kl=A s i
nφ. (to) become. The arithmetic unit (4) includes a delay compensator (2
) and the output of the 90° phase shifter (3) and output. The arc tangent is a periodic function, X(
Considering the signs of K) and Y(ni), the period is 2π. Therefore φ (to) = φ. (K) mod 2π...
... becomes ■. That is, the phase of the FM wave is determined by the phase detector (10).

Here, if the formula ■ always holds, sinφ(K)
(hereinafter also referred to as rW (Kl)) and delay compensator (2)
The output X (in) = Δsinφ0 (in) should be similar. However, as mentioned earlier, in cases where the lower side waves are emphasized and noise is added, such as in the case of FM waves used in the reproduction brightness system of home VTRs, the formula This does not hold, and the human-powered FM wave X (as shown in Figure 4)
2), the si port φ(2) may have a waveform with one cycle missing as shown in FIG. However, for example, E
'When the M wave is 5.4MHz to 7.0M1lz and the sampling frequency is 14.3MHz, l
' The sampling points included in one cycle of the M wave are approximately 2
It has been experimentally confirmed that φ(ni), which does not satisfy the equation (2), will not be output twice in a row in the case where That is, among the three consecutive sampling points φ(1), φ(Z), and φ(3), φ
Even if (2) does not satisfy formula ■, φ(I), φ(3
) is considered to satisfy the formula ■. At this time, X (
There are two possible relationships between the waveforms of sin() and sinφ((ni)).

One is X (21
-X (1) ≦O,X (31-X (2)≧0si
nφ(2)−sinφ(1)≧Q, sinφ(31−s
In the case where inφ(2)≦0...■, the other case is as shown in Figure 8(a), (bl), Xf2)-Xm≧O1X (3) -X (2)≦ 0
sinφ(2)−sinφm≦01sinφ(3)−
This is a case where sinφ(2)≧0...■. In either case, sinφ(K) has a waveform with one period missing, so as in the equation 0.0, X (21-X (11 and sinφ(2)-s
inφ(1), X (3) −X (2) and sin
The signs of φ(3)−sinφ(2) do not match.

Therefore, first, in the first detector (11), sin
A second detector (12) detects an increase or decrease in φ.
The first detector (11
) and the output of the second detector (13) do not match twice in a row, the control signal generator (13)
φ(
Correct the value of Kl. Next, this correction method will be described.

Since φ(1) and φ(3) satisfy the formula ■, φ(1)
=φ. (I) mod 2 x , φ (3) φ
. (31 mod 2π. Therefore, now φ(1)=φ.

(1). φ(3)=φo(3) mod 2x, but between =1 and =3 as shown in FIG. 7 or 8, X(to)=Δsinφ. (ni) has one period more than sinφ (ni), so it is φ. (3): φ (3)+27C. φ(2), φ. (2) are respectively φ(1
) and φ(3) φ. (1) and φ. It is a value between (3). This is shown in FIG. Therefore, φ(2) and φ
. The difference in (2) is considered to be approximately π.

φ. (2) Cape φ(2) +π
...... ■In other words, it is considered that replacing φ(2) with φ(2)+π approaches the true phase of the FM wave.

Note that since all phases φ(ni) are determined in the range of 0 to 2π, the calculation of φ(2)+π uses 2Tt as the modulus. In other words, the correction method is to change φ(2) to (φ(2)+Tc)
Can be replaced with mod 27C.

From the above, first, the output of the phase detector (10) is delayed in the delay corrector (14) by the same amount as the delay time of the signal output from the control signal generator (13). The phase corrector (15) uses the output φ (to) of the delay compensator (14) manually, and when the output signal from the control signal generator (13) is significant "1", it outputs φ(K) + π (mod 2π). , and when the value is zero, φ(K) is output.

The output of the phase corrector (15) is input to the delay device (5) and delayed by one sampling period. A subtracter (6) subtracts the output of the delay device (5) from the output of the phase corrector (15). The discontinuity corrector (7) adds 2π to the output of the subtracter (6) and outputs the result only when the output of the subtractor (6) becomes negative. The operations of these delay device (5), subtractor (6), and discontinuity corrector (7) are the same as in the conventional example, and the operation of the continuous corrector (
The difference in the phase of the FM wave is output from the output of 7). Therefore, by converting the output of the discontinuity corrector (7) into an analog signal using the D/A converter (8), an output obtained by demodulating the FM signal can be obtained.

Next, the operation and configuration example of the first detector (11) will be explained.The first detector (11) receives the output signal φ(K) of the phase detector (10), ) is used to detect increases and decreases in

Figure 10 shows s i for the values of φ(to-1) and φ(to)
It represents the positive or negative value of nφ(Kl-sinφ(trl). According to this chart, sinφ(ni) sinφ(
If the configuration is configured to output "0" when -1) is positive and rlJ when it is negative, s
An increase or decrease in sinφ can be detected without subtracting inφ.

An example of the configuration of such a first detector +I l) is shown in the eleventh
As shown in the figure. In the figure, (20) is the phase detector (lO)
A separator that separates the output φ into the form φ=ψ+π×δ and outputs δ as the first output and ψ as the second output, (21) is the first output of the phase detector. A delay device that delays δ by one sampling period, (22) is an exclusive OR gate that manually inputs the output of the delay device (21) and the first output δ of the separator (20), and (23) is a separator ( 20) is a delay device that delays the second output ψ by one sampling period; (24) is a comparator that compares the magnitude of the second output of the separator (20) and the output of the delay device (Z3); (25) is a memory holding the value of π, (26) is a subtractor that subtracts the output of the delay device (23) from the output π of the memory (25), and (27) is the second output of the separator (20). A comparator that compares the magnitude of ψ and the output of the subtractor (26), (28) is an exclusive OR gate that receives the output of the comparator 28 (241) and the output of the comparator (27), and (29) is a separation gate. The exclusive OR gate 130) inputs the first output δ of the device (20) and the output of the exclusive OR gate +281. This is a switch that switches between the output δ of the exclusive OR gate (29) and the output of the exclusive OR gate (29).

Next, the operation will be explained. The signal φ output from the phase detector (10) is processed as φ=ψ+ in the separator (20).
It is separated into π×δ, and ψ and δ are output. this is,
For example, when the phase φ is n bits, it can be constructed by outputting the most significant bit as the first output δ and outputting the lower 1n-1) bits as the second output ψ. The first output δ of the separator (20) is delayed by one sampling period T in the delay device (21). Therefore, at time −
At T, the first output of the separator (20) is δ(K)
The output of the delay device (21) is 0, which is δ(t1).
The first output δ of the separator (20) and the delay device (21)
The output δ(ni-1) is input to the exclusive OR gate (22), and when δ(K)≠δ(ni-th), rlJ is output, and when δ(ni)δ(t1), rOJ In other words, in Fig. 10, (φ(ni-ri〈π and φ(ni)
≧π), or (φ(ni-1)≧π and φ(ni)kuπ)
At this time, rlJ is output from the exclusive OR gate (22). The output of the exclusive OR gate (22) controls the operation of the switch (30).

Also, the first output δ of the separator is connected to the switch (30
) becomes the first input value of the exclusive OR gate (22)
When the output of is rlJ, this first human power value δ(K) is selected at the switch (30).

The second output ψ of the other one separator (20) is a delay device (23)
is delayed by one sample period]. Therefore, at one time K・1゛, the second output of the 1 separator (20) is ψ・(K), and the output of the delay device (23) is ψ(t1).
It is. The second output ψ(ni) of the separator (20) and the output ψ(ni-1) of the delay device (23) are input to the comparator (24), and when ψ(ni)≧ψ(tl), “O”, ψ (ni)ku ψ
(-1), "rl" is output. In addition, a delay device (
The output ψ(-l) of 23) is input to a subtracter (26), and π-ψ(-1) is calculated. subtraction 'a (26)
The output π-ψ(ni-1) and the second output ψ(ni) of the separator (20) are input to the comparator (27), and ψ(Kl ≧π
“l” when −ψ蒐に−1), ψ(K)<π−ψ(−
1), "0" is output. Exclusive OR gate (
29) takes the exclusive OR of the output of the comparator (24) and the output of the comparator (25), and δ(ni)=δ(ni-1)=r
In the case of OJ, rOJ is output when sinφ(ni)−sinφ(ni) is positive, and “1” is output when it is negative. Also,
If δ(ni)=δ(ni-1)=rlJ, then sin
φ(K) −s i n When φ(ni-1) is positive, “
1'', rOJ is output when it is negative. The output of this exclusive OR gate (2B) and the first output δ of the separator (20)
If we input (in) into the exclusive OR gate (29), we get
Also in the case of δ(ni)=δ(ni-1)=rOJ, δ(ni)=δ
(K-1) = r I J also, sinφ(to)
"O" when sinφ (tr) is positive, rlJ when negative
is output. The output of this exclusive OR gate (29) becomes the second major chi1 of the switch (30), and when the output of the exclusive OR gate (22) is "0", the switch (
3G) selects and outputs the second input.

From the above, according to FIG. 10, sinφ(Kl−s
inφ(ni-1) "0" when positive, "cao" when negative
A first detector (11) can be constructed that outputs .

Next, an example of the configuration of the second detector (12) is shown in FIG. The output X (K) of the delay compensator (2) is
1) is delayed by one sampling T.

The output X of the delay corrector (2) and the output X of the delay device (31) are input to the comparator (32),
≧×(ni-11(7), then “0”, X(K)<X
(-1), "1" is output.

FIG. 13 shows another embodiment of the invention. Since this embodiment differs from the embodiment shown in FIG. 1 only in the configuration of the reversal position detector (16), the configuration and operation of this portion will be explained below.

In the figure, (41) is the output φ of the phase detector (10)
(42
) is a delay compensator that further delays the output X of the delay unit 1E unit (2), and (43) is a delay compensator that further delays the output This detector outputs a significant rlJ signal when they do not match, and outputs an insignificant "0" signal when they do not match. Next, the operation will be explained.

The output φ (in) of the phase detector (10) is input to the arithmetic unit (41).
is input, and W(to)=sinφ(K) is calculated.

On the other hand, the output of the delay compensator (2) is output from the delay compensator (42).
The signal Sj W (Kl) which is input manually and occurs in the arithmetic unit (4) and the arithmetic unit (41) is delayed by the same amount as the delay time of Kl.

In other words, the signal W(to)=sinφ(
) is output from the delay compensator (42), the signal X
(to)=As i n φo (K) is output.

Assuming that the human FM wave has the waveform shown in FIG. 4 explained in the embodiment of FIG. 1, the output of the delay compensator (42)
(K) and the output W (to) of the n'jfX unit (41) are:
The relationship is as shown in the 7th ward and Figure 8. Detector (43
) is the output W (to) of the arithmetic unit (11) and the delay compensator (+
2) (7) For output X (K), W (K) −W
(K-1) (7) Sign and X (K) -X (d-1
) (7) Sign, the sign of W(Ni11)-W(K) and X(
When the signs of 1)) -
Outputs the signal. The position corrector (+5) is the detector (4
When the output of 3) is significant “l”, φ(to) 1π(mo
d2π).

When the output of the detector (13) is unexpectedly "0", φ (to)
The output is similar to the embodiment shown in FIG.

In FIG. 6 showing an example of the configuration of the detector (43) in FIG. 14, (50) is the output W (Kl
A delay device, (52
) is the output W (to) of the arithmetic unit (41) and the output W (K-11) of the delay unit (50), and W (K)≧W (K-1
A comparator that outputs 1 when l<W(K-11) when +, (52) is a delay device that delays the output X (to) of the delay compensator (42) by one sampling period 1. (
53) compares the delay compensator (42) (7) output X (K) with the delay compensator (52) (7) output X (K-11,
(54) is a comparator that outputs l when K-11 (7), 0.
(Exclusive OR gate whose inputs are the output of 511 and the output of comparator (53), +551 is the exclusive OR gate (5
4) Output! The delay device (56) that delays by the sampling period T is an AND gate that receives the output of the exclusive OR gate (54) and the output of the delay device (55).

Next, the operation will be explained. The signal W(Ni) outputted from the arithmetic unit (41) becomes a signal W(Ni=1) delayed by one sampling period by the delay device (50).

W(ni) and W(nikawa) are input to the comparator (51), and W
When (to) ≧ W (to - 1), O, W (K) < W (to -
1), 1 is output. On the other hand, the delay compensator (42
) is output from j6. X (in) is a delay device (52
), the signal X(to −I
). X(ni) and X(niri) are input to the comparator (53), and when X(ni) ≥
When X(ni)kux(ni-I), 1 is output. The output of the comparator (51) and the output of the comparison Z (53) are input to the exclusive OR gate +541, and when the output of the comparator (51) and the output of the comparator (53) are equal, "0" is output. , otherwise "1" is output. That is, W(ni)≧W(ni-1) and X(ni)≧X (K-1)
or W(ni)〈W(ni-1) and X(ni)〈X(ni-
1), “0” is output, and in other cases “1”
is output. In other words, increase/decrease in W(to) and X(
When the increase/decrease in ltl matches, it outputs "0", and when it does not, it outputs rlJ. The output of this exclusive OR gate (24) is delayed by l sampling period in a delay device (55) and input to an AND gate (56). The output of the exclusive OR gate (54) is input to the other input terminal of the AND gate T561. Therefore, when the output of the exclusive OR gate (54) is "1" twice in a row, the output of the AND gate (56) is "1", and in other cases, "0" is output. That is, W (to)
If the increase/decrease in and the increase/decrease in X do not match twice in a row, "1" is output, otherwise "0" is output.

[Effects of the Invention] As described above, according to the present invention, the phase of the FM wave detected by the phase detector is different from the phase of the human-powered FM wave by iE L
Since the structure is configured such that it is determined whether or not it represents, and if it is determined that it is incorrect, it is corrected and then the phase difference is taken, a highly accurate 1-'M demodulator can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 6 are diagrams for explaining the process by which an inversion phenomenon occurs in a conventional FM demodulator, and FIGS. 7 and 8 are
A waveform diagram of the F-'M wave with phase inversion, FIG. 9 is a diagram for explaining the correction method in the phase corrector of this embodiment, and FIG. 10 is a diagram of the first detector of this embodiment. 11 is a block circuit diagram showing an example of the configuration of this first detector, and FIG. 12 is a diagram illustrating an example of the configuration of the second detector of this embodiment. 13 is a block diagram showing another embodiment of the present invention, FIG. 14 is a block circuit diagram showing one configuration example of the detector of this embodiment, and FIG. 15 is a block diagram showing a conventional 1'M detector. FIG. 2 is a block circuit diagram of a demodulator. (1)...Δ/D converter, (2)...Delay compensator, (3)...90° phase shifter, (41)...Calculator, (5)...Delay device , (6)...subtractor, (7)...
... Discontinuity corrector, (1o) ... Phase detector, (11
)...first detector, (12)...second detector,
(13)...Control signal generator, (+4), (421
...delay corrector, (15) ...phase corrector, (+6
)--Reversal position detector, (43)...Detector. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (3)

[Claims] (1) An A/D converter that converts an input analog FM signal into a digital signal, a phase detector that detects the phase of each sampling point of this digital FM signal, and a phase detector that detects the phase of each detected signal. an inverted phase detector for detecting a sampling point; a phase corrector for correcting data of the sampling point whose detected phase is inverted; a delay device for delaying the output signal of the phase corrector by one sampling period; A subtracter that subtracts the output of the delay device from the output signal of the corrector, a discontinuity corrector that corrects discontinuity points in the output signal of this subtracter, and converts the output signal of this discontinuity corrector into an analog signal. An FM demodulator equipped with a D/A converter. (2) In claim (1), when the inverting phase detector has a value of φ at each sampling point of the output of the phase detector, 1
a first detector that detects an increase or decrease in the value of sinφ with respect to the previous sampling point;
a second detector that detects an increase or decrease in the value of the digital FM signal output from the D converter at the same sampling point compared with the first detector; and the first detector and the second detector. and a control signal generator that generates a significant control signal when it detects that the output does not match twice in a row, and when the significant control signal is output, the phase is reversed in the phase corrector. F configured to add π to the value of the sampled point and correct it.
M demodulator. (3) In claim (1), when the inverting phase detector has a value of φ at each sampling point of the output of the phase detector, 1
an arithmetic unit that calculates sinφ for the previous sampling point; a delay corrector that delays the output of the A/D converter by a certain period of time so as to be synchronized with the output signal of the arithmetic unit; and an increase/decrease in the output of the arithmetic unit; and a detector that outputs a significant signal when the increase/decrease of the output of the delay compensator with respect to the previous sampling point does not match twice in a row, and when the significant signal is output, the phase compensator An FM demodulator configured to correct the value of a sampling point whose phase has been inverted by adding π.