JPH0218672A - Circuit processor - Google Patents

Circuit processor

Info

Publication number
JPH0218672A
JPH0218672A JP63169826A JP16982688A JPH0218672A JP H0218672 A JPH0218672 A JP H0218672A JP 63169826 A JP63169826 A JP 63169826A JP 16982688 A JP16982688 A JP 16982688A JP H0218672 A JPH0218672 A JP H0218672A
Authority
JP
Japan
Prior art keywords
circuit
analysis
analyzing
analysis results
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63169826A
Other languages
Japanese (ja)
Inventor
Masanori Funayama
舟山 正憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Solution Innovators Ltd
Original Assignee
NEC Solution Innovators Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Solution Innovators Ltd filed Critical NEC Solution Innovators Ltd
Priority to JP63169826A priority Critical patent/JPH0218672A/en
Publication of JPH0218672A publication Critical patent/JPH0218672A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily obtain the desired information by securing such a constitution where an analyzing result extracting means groups all analyzing results of a circuit obtained by a circuit analyzing means based on the given conditions related to the connection and read out of a control information memory means and then extracts only the most important analyzing result. CONSTITUTION:A control information memory means 3 stores the given conditions related to the connection between each terminal of a circuit and each connection line as well as the importance deciding conditions of the circuit analyzing results. Then an analyzing result extracting means 4 groups all analyzing results of the circuit obtained by a circuit analyzing means 2 based on the given conditions of the connection read out of the means 3. At the same time, only the most important analyzing result is extracted for each group of analyzing results which are grouped after the importance deciding conditions of the circuit analyzing results. An analyzing result display means 5 displays the extracted most important analyzing result. Thus the desired information is easily obtained without checking all circuit analyzing results.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は回路を解析して解析結果を表示する回路処理装
置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit processing device that analyzes a circuit and displays the analysis results.

[従来の技術] 従来、この種の回路処理装置は、回路解析手段により解
析された回路の解析結果をすへて表示していた。
[Prior Art] Conventionally, this type of circuit processing device always displays the analysis results of a circuit analyzed by a circuit analysis means.

回路処理装置の従来例としては[大規模回路向はタイミ
ング解析システムHEART]  (情報処理学会、第
35目金国大会資料、7F−6,7F7)がある。
A conventional example of a circuit processing device is [timing analysis system HEART for large-scale circuits] (Information Processing Society of Japan, 35th Gold Country Conference Materials, 7F-6, 7F7).

[発明か解決しようとする課題] 上述した従来の回路処理装置は、回路解析手段により解
析された結果をすべて表示しているのて表示された解析
結果の中から目的とする情報を見つけるのに多くの労力
を必要とするという欠点がある。
[Problem to be solved by the invention] The conventional circuit processing device described above displays all the results analyzed by the circuit analysis means, so it is difficult to find the desired information from the displayed analysis results. The disadvantage is that it requires a lot of effort.

〔課題を解決するための手段] 本発明の回路処理装置は、 回路の端子、各端子間の接続線の名称ならびに各端子と
各接続線との接続に関する情報を記憶する回路記憶手段
と、 前記回路の各端子と各接続線との接続に関する付与条件
および回路解析結果の重要度判定条件を記憶する制御情
報記憶手段と、 前記回路記憶手段から前記回路の端子、各端子間の接続
線の名称ならびに各端子と各接続線との接続に関する情
報を読出して前記回路の解析を行なう回路解析手段と、 該回路解析手段が解析した前記回路の全解析結果を前記
制御情報記憶手段から読出した前記各端子と各接続線と
の接続に関する付与条件によりグループ化し、前記制御
情報記憶手段から回路解析結果の重要度判定条件を読出
して前記グループ化された解析結果の各グループ単位ご
とに最も重要な解析結果たりを抽出する解析結果抽出手
段と、 該解析結果抽出手段により抽出された解析結果を表示す
る解析結果表示手段とを有する。
[Means for Solving the Problems] A circuit processing device of the present invention includes: circuit storage means for storing information regarding terminals of a circuit, names of connection lines between each terminal, and connections between each terminal and each connection line; control information storage means for storing conditions for connection between each terminal of the circuit and each connection line and conditions for determining the importance of circuit analysis results; and circuit analysis means for reading out information regarding connections between each terminal and each connection line to analyze the circuit, and each of the circuit analysis means for reading out all analysis results of the circuit analyzed by the circuit analysis means from the control information storage means. The grouping is performed based on conditions given regarding the connections between the terminals and each connection line, and the conditions for determining the degree of importance of the circuit analysis results are read from the control information storage means to determine the most important analysis result for each group of the grouped analysis results. and analysis result display means for displaying the analysis results extracted by the analysis result extraction means.

(作 用] 解析結果抽出手段が回路解析手段か解析した回路の全解
析結果を制御情報記憶手段から読出した接続に関する付
与条件によりグループ化し、また同しく制御情報記憶手
段から回路解析結果の重要度判定条件を読出してグルー
プ化された解析結果の各グループ単位ごとに最も重要な
解析結果だけを抽出し、その抽出された解析結果が解析
結果表示手段により表示されるので、解析された全解析
結果から目的とする情報を容易に見つけることかできる
(Function) The analysis result extraction means groups all the analysis results of the circuit analyzed by the circuit analysis means based on the given conditions regarding connections read from the control information storage means, and also extracts the importance of the circuit analysis results from the control information storage means. The judgment conditions are read out and only the most important analysis results are extracted for each group of grouped analysis results, and the extracted analysis results are displayed by the analysis result display means, so all analyzed analysis results are displayed. You can easily find the information you want.

[実施例] 次に、本発明の実施例について図面を参照して説明する
[Example] Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明の回路処理装置の一実施例のブ”  4 0ツク図、第2図は第1図の回路処理装置の回路解析の
対象となる回路の一例を示す接続状態図、第3図は第1
図の回路解析手段2が解析した第2図の回路の全解析結
果か第1図の解析結果抽出手段4によりグループ化され
た状態を示す図、第4図は第1図の解析結果抽出手段4
が抽出した解析結果を示す図である。
FIG. 1 is a block diagram of an embodiment of the circuit processing device of the present invention, and FIG. 2 is a connection state diagram showing an example of a circuit to be analyzed by the circuit processing device of FIG. 1. Figure 3 is the first
A diagram showing all analysis results of the circuit shown in FIG. 2 analyzed by the circuit analysis means 2 shown in the figure, grouped by the analysis result extraction means 4 of FIG. 1, and FIG. 4 is a diagram showing the analysis result extraction means of FIG. 1 4
It is a figure showing the analysis result extracted.

この回路処理装置は回路記憶手段1と回路解析手段2と
制御情報記憶手段3と解析結果抽出手段4と解析結果表
示手段5とからなっている。回路記憶手段1は第2図に
示された解析対象となる回路の端子6,8,10,11
,13,15゜16、]、8.20と接続線7,9.1
2,1417.19と端子6ほかの各端子と接続線7ほ
かの各接続線の接続に関する情報として遅延情報を記憶
している。回路解析手段2は、回路記憶手段1が記憶し
ている端子6ほかの各端子と接続線7ほかの各端子の名
称と遅延情報を読出して回路の遅延解析を行ない、第3
図に示す解析結果21と22と23を得る。ここて解析
結果21は第2図に示された回路のうち、端子6から接
続線7、端子8、接続線9を紅で端子10まての経路に
関する解析結果てあり、情報として端子6,10および
接続線7.9の名称と接続線7.9の遅延時間の和を含
んでいる。同様に解析結果22.23はそれぞれ端子1
1.16から接続線12、端子13、接続線]4を経て
端子15まてと、接続線17、端子18、接続線19を
経て端子20まての経路に関する解析結果で、それぞれ
両端の端子・接続線の名称と接続線の遅延時間の和を情
報に含んでいる。制御情報記憶手段3には、第2図の回
路の端子6ほかの各端子と接続線7ほかの各接続線に関
する付与条件として東線化するための各経路のグループ
形成の条件と回路解析結果2122.23の重要度判定
条件として遅延時間が最大であるとの条件が記憶されて
いる。解析結果抽出手段4は第3図の全解析結果21,
22.23を入力し、制御情報記憶手段3から先ず東線
化するための各経路のグループ形成の条件を読出して、
これに基すいて第3図に示すように全解析結果21,2
2.23を、解析結果21と22を含むグループ24と
解析結果23を含むグループ25にグループ化する。続
いて解析結果抽出手段4は、制御情報記憶手段3から重
要度判定条件としての遅延時間が最大であるとの条件を
読出して第3図のグループ24と25とよりそれぞれ遅
延時間が最大である解析結果21と23(第4図)を抽
出する。解析結果表示手段5は解析結果抽出手段4より
解析結果21と23を人力して表示する。
This circuit processing device consists of circuit storage means 1, circuit analysis means 2, control information storage means 3, analysis result extraction means 4, and analysis result display means 5. The circuit storage means 1 stores terminals 6, 8, 10, 11 of the circuit to be analyzed shown in FIG.
, 13, 15° 16, ], 8.20 and connection line 7, 9.1
2,1417.19, terminal 6 and other terminals, and connection line 7 and other connection lines, delay information is stored. The circuit analysis means 2 reads the names and delay information of each terminal other than the terminal 6 and the connection line 7 and other terminals stored in the circuit storage means 1, performs a delay analysis of the circuit, and performs a delay analysis of the circuit.
Analysis results 21, 22, and 23 shown in the figure are obtained. Here, the analysis result 21 is the analysis result regarding the path from the terminal 6 to the terminal 10 with the connecting wire 7, terminal 8, and the connecting wire 9 in red in the circuit shown in FIG. 10 and the name of the connection line 7.9 and the sum of the delay time of the connection line 7.9. Similarly, analysis results 22 and 23 are respectively terminal 1
1.16 to connection line 12, terminal 13, connection line] 4 to terminal 15, and connection line 17, terminal 18, connection line 19 to terminal 20. -The information includes the name of the connection line and the sum of the delay time of the connection line. The control information storage means 3 stores conditions for group formation of each route and circuit analysis results for forming an east line as conditions for each terminal other than terminal 6 of the circuit in FIG. 2 and each connection line other than connection line 7. The condition that the delay time is the maximum is stored as the importance determination condition for 2122.23. The analysis result extraction means 4 extracts all the analysis results 21 in FIG.
22.23 is input, and the conditions for group formation of each route to be made into an east line are first read out from the control information storage means 3.
Based on this, the total analysis results 21, 2 are shown in Figure 3.
2.23 are grouped into group 24 including analysis results 21 and 22 and group 25 including analysis result 23. Subsequently, the analysis result extracting means 4 reads the condition that the delay time is the maximum as the importance judgment condition from the control information storage means 3, and determines that the delay time is the maximum from groups 24 and 25 in FIG. Analysis results 21 and 23 (Fig. 4) are extracted. The analysis result display means 5 manually displays the analysis results 21 and 23 from the analysis result extraction means 4.

[発明の効果] 以」二説明したように本発明は、回路を解析して結果を
表示する回路処理装置に、回路の各端子と各接続線との
接続に関する付与条件および回路解析結果の重要度判定
条件を記憶する制御情報記憶手段を設け、解析結果抽出
手段が回路解析手段が解析した回路の全解析結果を、該
制御情報記憶手段から読出した接続に関する付与条件に
よりグルプ化し、また回路解析結果の重要度判定条件を
読出してグループ化された解析結果の各グループ単位ご
とに最も重要な解析結果だけを抽出して解析結果表示手
段かそれを表示することにより、回路の全解析結果を調
へることなく目的の情報が容易に得られるという効果が
ある。
[Effects of the Invention] As explained below, the present invention provides a circuit processing device that analyzes a circuit and displays the results, and provides conditions for connection between each terminal of the circuit and each connection line and the importance of the circuit analysis results. A control information storage means is provided for storing the degree determination conditions, and the analysis result extraction means groups all the analysis results of the circuit analyzed by the circuit analysis means according to the given conditions regarding the connections read from the control information storage means, and the circuit analysis All the analysis results of the circuit can be examined by reading out the importance judgment conditions of the results, extracting only the most important analysis results for each group of grouped analysis results, and displaying it on the analysis result display means. This has the effect that the desired information can be easily obtained without any trouble.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の回路処理装置の一実施例のブロック図
、第2図は第1図の回路処理装置の回路解析の対象とな
る回路の一例を示す接続状態図、第3図は第1図の回路
解析手段2か解析した第2図の回路の全解析結果か第1
図の解析結果抽出手段4によりグループ化された状態を
示す図、第4図は第1図の解析結果抽出手段4が抽出し
た解析結果を示す図である。 1・・・・・・回路記憶手段、2・・・・・・回路解析
手段、3・・・・・・制御情報記憶手段、 4・・・・・・解析結果t+II出手段、5・・・・・
・解析結果表示手段、 6、8.10.11.+3.15. +6.18.20
・・・・・・端子、7、9.12.14.17,19・
・・・・・・・・・・・・・・・・・接続線、2]、 
22.23・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・解析結果、グループ。
FIG. 1 is a block diagram of an embodiment of the circuit processing device of the present invention, FIG. 2 is a connection state diagram showing an example of a circuit targeted for circuit analysis of the circuit processing device of FIG. 1, and FIG. Circuit analysis means 2 in Figure 1 or all analysis results of the circuit in Figure 2 analyzed
FIG. 4 is a diagram showing the analysis results extracted by the analysis result extraction means 4 of FIG. 1. FIG. 1... Circuit storage means, 2... Circuit analysis means, 3... Control information storage means, 4... Analysis result t+II output means, 5... ...
-Analysis result display means, 6, 8.10.11. +3.15. +6.18.20
...Terminal, 7, 9.12.14.17, 19.
・・・・・・・・・・・・・・・Connection line, 2],
22.23・・・・・・・・・・・・・・・・・・
・・・・・・・・・Analysis results, groups.

Claims (1)

【特許請求の範囲】 1、回路の端子、各端子間の接続線の名称ならびに各端
子と各接続線との接続に関する情報を記憶する回路記憶
手段と、 前記回路の各端子と各接続線との接続に関する付与条件
および回路解析結果の重要度判定条件を記憶する制御情
報記憶手段と、 前記回路記憶手段から前記回路の端子、各端子間の接続
線の名称ならびに各端子と各接続線との接続に関する情
報を読出して前記回路の解析を行なう回路解析手段と、 該回路解析手段が解析した前記回路の全解析結果を前記
制御情報記憶手段から読出した前記各端子と各接続線と
の接続に関する付与条件によりグループ化し、前記制御
情報記憶手段から回路解析結果の重要度判定条件を読出
して前記グループ化された解析結果の各グループ単位ご
とに最も重要な解析結果だけを抽出する解析結果抽出手
段と、 該解析結果抽出手段により抽出された解析結果を表示す
る解析結果表示手段とを有する回路処理装置。
[Scope of Claims] 1. Circuit storage means for storing information regarding terminals of the circuit, names of connection lines between each terminal, and connections between each terminal and each connection line; and each terminal and each connection line of the circuit. control information storage means for storing conditions for connection of the circuit and conditions for determining the importance of the circuit analysis results; and control information storage means for storing the names of the terminals of the circuit, the connection lines between the terminals, and the names of the terminals and the connection lines from the circuit storage means. circuit analysis means for reading out information regarding connections and analyzing the circuit; and information regarding connections between each terminal and each connection line, which reads out all analysis results of the circuit analyzed by the circuit analysis means from the control information storage means. analysis result extraction means for grouping according to given conditions, reading out the importance judgment conditions of the circuit analysis results from the control information storage means, and extracting only the most important analysis results for each group of the grouped analysis results; and analysis result display means for displaying the analysis results extracted by the analysis result extraction means.
JP63169826A 1988-07-06 1988-07-06 Circuit processor Pending JPH0218672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63169826A JPH0218672A (en) 1988-07-06 1988-07-06 Circuit processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63169826A JPH0218672A (en) 1988-07-06 1988-07-06 Circuit processor

Publications (1)

Publication Number Publication Date
JPH0218672A true JPH0218672A (en) 1990-01-22

Family

ID=15893623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63169826A Pending JPH0218672A (en) 1988-07-06 1988-07-06 Circuit processor

Country Status (1)

Country Link
JP (1) JPH0218672A (en)

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