JPH0219782A - Circuit analyzing system - Google Patents
Circuit analyzing systemInfo
- Publication number
- JPH0219782A JPH0219782A JP63169835A JP16983588A JPH0219782A JP H0219782 A JPH0219782 A JP H0219782A JP 63169835 A JP63169835 A JP 63169835A JP 16983588 A JP16983588 A JP 16983588A JP H0219782 A JPH0219782 A JP H0219782A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- analysis
- invalid
- storage means
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は回路解析方式に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a circuit analysis method.
従来の回路解析方式は、例えば［遅延時間解析システム
−ＮＥＬＴＡＳ２−］ （情報処理学会、設計自動化
研究会資料、設計自動化１４−３．１９８２）に記載さ
れているように、回路の端子、端子間の接続および各接
続に関する情報により、端子間における信号の遅延時間
や波形歪み等を算出し、その結果を出力するが、そのと
き、回路上での信号の無効な伝播経路の情報は用いられ
ていない。Conventional circuit analysis methods, for example, as described in [Delay Time Analysis System - NELTAS2-] (Information Processing Society of Japan, Design Automation Study Group Materials, Design Automation 14-3.1982), The signal delay time, waveform distortion, etc. between the terminals are calculated using information about the connections and each connection, and the results are output. At this time, information about the invalid propagation path of the signal on the circuit is not used. do not have.
上述した従来の回路解析方式は、回路上での信号の無効
な伝播経路の情報を用いずに回路の解析を行なっていた
ので、実際の回路上では存在しない信号の流れをも解析
および出力の対象としてしまうという欠点がある。その
ため、出力された解析結果のうちから、無効なものは人
手により除外するような作業を必要とするという問題等
がある。The conventional circuit analysis method described above analyzes the circuit without using information about invalid propagation paths of signals on the circuit, so it is possible to analyze and output signal flows that do not exist on the actual circuit. It has the disadvantage of being targeted. Therefore, there is a problem that it is necessary to manually exclude invalid results from among the output analysis results.
本発明の回路解析方式は、回路の端子、端子間の接続お
よび各接続に関する情報を記憶する回路記憶手段（１）
と、
回路上での信号の無効な伝播経路を複数の端子の組によ
り記憶する無効点記憶手段（２）と、前期回路記憶手段
（１）が記憶する情報に基づいて回路解析を行い、該回
路解析の結果のうちから、前記無効点記憶手段が記憶す
る回路上での信号の無効な伝播経路を対象からはずして
出力する回路解析手段（３）とを含むことを特徴とする
。The circuit analysis method of the present invention includes a circuit storage means (1) that stores information regarding terminals of a circuit, connections between the terminals, and each connection.
and invalid point storage means (2) for storing invalid propagation paths of signals on the circuit using a plurality of sets of terminals, and circuit analysis based on the information stored in the circuit storage means (1). The present invention is characterized in that it includes circuit analysis means (3) for outputting, from among the results of the circuit analysis, invalid propagation paths of signals on the circuit stored by the invalid point storage means, excluded from the target.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例であり、回路記憶手段１．無
効点記憶手段２２回路解析手段３および解析結果表示手
段４から成る。FIG. 1 shows an embodiment of the present invention, in which circuit storage means 1. It consists of invalid point storage means 22, circuit analysis means 3, and analysis result display means 4.
回路記憶手段１は、回路の端子、端子間の接続および各
接続に関する情報を記憶する。無効点記憶手段２は、回
路上での信号の無効な伝播経路を複数の端子の組により
記憶する。回路解析手段３は、前記回路記憶手段１の情
報に基づき解析し、前記無効点記憶手段２の情報に基づ
き回路上での信号の無効な伝播経路を対象からはずして
解析結果を解析結果表示手段４へ出力する。解析結果表
示手段４は、該回路解析手段３により解析された結果を
表示する。The circuit storage means 1 stores information regarding terminals of the circuit, connections between the terminals, and each connection. The invalid point storage means 2 stores invalid propagation paths of signals on the circuit using sets of a plurality of terminals. The circuit analysis means 3 performs an analysis based on the information in the circuit storage means 1, excludes invalid propagation paths of signals on the circuit from the target based on the information in the invalid point storage means 2, and displays the analysis results as an analysis result display means. Output to 4. The analysis result display means 4 displays the results analyzed by the circuit analysis means 3.
第２図は、本実施例を説明するためにモデル化して示さ
れた回路パッケージ例である。FIG. 2 is an example of a circuit package modeled to explain this embodiment.
第２図において、ｌ）、（２）、（９）および（１０）
は回路パッケージの端子、（３）。In Figure 2, l), (2), (9) and (10)
is the terminal of the circuit package, (3).
（４）および（５）は回路素子１００の端子、（６）、
（７）および（９）は回路素子２００の端子を示す。(4) and (5) are terminals of the circuit element 100, (6),
(7) and (9) indicate terminals of the circuit element 200.
いま、端子（１）→（３）→（５）→（６）−→（８）
→（１０）を通る信号と、端子（２）→（４）→（５）
→（６）→（７）→（９）を通る信号が存在するものと
すると、当然にこれらの伝播経路も存在することになる
。しかし、回路動作上、端子（１）→（３）→（５）→
（６）→（７）→（９）という信号の流れは存在しない
場合には、無効点記憶手段２に端子（３）及び（７）を
記憶する。Now, terminal (1) → (3) → (5) → (6) - → (8)
→ Signal passing through (10) and terminal (2) → (4) → (5)
If it is assumed that a signal passing through →(6) →(7) →(9) exists, these propagation paths naturally also exist. However, due to circuit operation, terminals (1) → (3) → (5) →
If the signal flow from (6) to (7) to (9) does not exist, terminals (3) and (7) are stored in the invalid point storage means 2.
第３図は、第１図における回路解析手段３の処理手順例
である。FIG. 3 shows an example of the processing procedure of the circuit analysis means 3 in FIG.
開始処理Ｓ１により処理がはじまる。終了判断処理Ｓ２
では、出力すべき総ての経路が解析された時のみ終了処
理Ｓ５へ移り、それ以外の場合は解析処理Ｓ３へ移る。The process begins with start process S1. Termination judgment process S2
Then, the process moves to end processing S5 only when all routes to be output have been analyzed; otherwise, the process moves to analysis process S3.
解析処理Ｓ３では１つの経路について遅延等の回路解析
を行なう。次に、限定処理Ｓ４では、解析処理Ｓ３にお
いて解析された経路が、第１図における無効点記憶手段
２に格納された情報に該当しない場合にのみ、第１図に
おける解析結果表示手段４へ解析結果を出力して終了判
断処理Ｓ２へ移る。第１図における無効点記憶手段２に
格納された情報に該当する場合には、何も出力せずに終
了判断処理Ｓ２へ移る。終了処理Ｓ５において一連の処
理が終了する。In analysis processing S3, circuit analysis such as delay is performed for one route. Next, in the limiting process S4, only if the route analyzed in the analysis process S3 does not correspond to the information stored in the invalid point storage means 2 in FIG. The result is output and the process moves to end determination processing S2. If the information corresponds to the information stored in the invalid point storage means 2 in FIG. 1, the process moves to end determination processing S2 without outputting anything. The series of processing ends in end processing S5.
以上説明したように本発明は、回路上での信号の無効な
伝播経路の情報を用いて、回路上では存在しない信号の
、流れを解析結果出力の対象からはずす効果がある。As described above, the present invention has the effect of excluding the flow of a signal that does not exist on the circuit from the target of outputting the analysis result by using information about the invalid propagation path of the signal on the circuit.
第１図は、本発明の一実施令のブロック図、第２図は、
本実施例を説明するためにモデル化された回路パッケー
ジ図、第３図は本実施例のフローチャートである。
（１）・・・回路記憶手段、（２）・・・無効点記憶手
段、（３）・・・回路解析手段、（４）・・・解析結果
表示手段。FIG. 1 is a block diagram of one implementation order of the present invention, and FIG. 2 is a block diagram of one implementation order of the present invention.
FIG. 3, which is a circuit package diagram modeled to explain this embodiment, is a flowchart of this embodiment. (1)...Circuit storage means, (2)...Invalid point storage means, (3)...Circuit analysis means, (4)...Analysis result display means.
Claims (1)
記憶する回路記憶手段（１）と、回路上での信号の無効
な伝播経路を複数の端子の組により記憶する無効点記憶
手段（２）と、前期回路記憶手段（１）が記憶する情報
に基づいて回路解析を行い、該回路解析の結果のうちか
ら、前記無効点記憶手段が記憶する回路上での信号の無
効な伝播経路を対象からはずして出力する回路解析手段
（３）とを含むことを特徴とする回路解析方式。Circuit storage means (1) that stores information regarding circuit terminals, connections between terminals, and each connection; and invalid point storage means (2) that stores invalid propagation paths of signals on the circuit using a plurality of sets of terminals. Then, a circuit analysis is performed based on the information stored in the circuit storage means (1), and from among the results of the circuit analysis, invalid propagation paths of signals on the circuit stored in the invalid point storage means are targeted. A circuit analysis method characterized by comprising: a circuit analysis means (3) for outputting a signal separated from the circuit analysis means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169835A JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169835A JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0219782A true JPH0219782A (en) | 1990-01-23 |
| JP2613917B2 JP2613917B2 (en) | 1997-05-28 |
Family
ID=15893803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63169835A Expired - Lifetime JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2613917B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301685B1 (en) | 1997-11-19 | 2001-10-09 | Nec Corporation | Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program |
-
1988
- 1988-07-06 JP JP63169835A patent/JP2613917B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301685B1 (en) | 1997-11-19 | 2001-10-09 | Nec Corporation | Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2613917B2 (en) | 1997-05-28 |
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