JPH0218789A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent oscillation due to GND level oscillation, etc., by executing the feedback of an internal synchronizing signal, which initializes an output buffer, to an internal synchronizing signal generating circuit and preventing the internal synchronizing signal from being generated when an output is changed. CONSTITUTION:When the comparatively large transistor of an output buffer 7 is operated, a large current flows and an internal GND level is oscillated. The oscillation of such an input signal is generated simultaneously with the operation of the output buffer 7, however, the operation of the output buffer 7 is activated by the internal synchronizing signal which is inputted to the output buffer 7. The feedback of the internal synchronizing signal, which operates the output buffer 7, is executed to an internal synchronizing signal generating circuit 8 and a power source to generate the internal synchronizing signal is turned off. Accordingly, the internal synchronizing signal can be prevented from being generated when the output is changed. Thus, the oscillation due to the fluctuation of the GND level can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and particularly to an internal synchronization signal output. The present invention relates to a semiconductor memory device to be controlled.

[Prior Art] Figure 5 shows the configuration of a conventional internally synchronous semiconductor memory device. FIG. This is an internal synchronous 5TATICRA
In the example of M, the input signal (address signal given an internal address)
a decoder (2) that selects the internal address to be accessed from the input signal, a word line (3) that arranges memory cells in a lattice pattern, and is used for access.
) and bit green f51, a sense amplifier (6) that amplifies the read t signal, and an output buffer (7) that shapes it into an external signal.
7) There is! 2! , Word Edge (3), Bit Iwao [
5) An internal synchronization signal generation port K (9) that internally generates and sends a synchronization signal to the sense amplifier (6), output buffer (7), etc.

Next, the operation will be explained. In FIG. 5, the internal synchronization signal generation circuit g (9) generates a pulse (internal synchronization signal) in response to a change in the input signal.

This pulse is delayed by the input concave path (
For example, the internal synchronization signal input to the sense amplifier (6) is pin 1 (later than the internal synchronization signal input to the sense amplifier 51). Then, along the flow of signals entering from the input and exiting from the output, the timing is adjusted using an internal synchronization signal so that each circuit is initialized just before the signal arrives.

Initialization, for example, in a CMOS circuit, means setting the input of each circuit to an intermediate potential where the inverter is most sensitive and waiting for the signal from the previous stage.After this input, the signal is processed fastest. be able to.

FIG. 6 shows changes over time in the waveforms of signals processed within this internally synchronous semiconductor memory device. In Figure 2, the potential of the word line (3) shows that the friend selected in the previous cycle by the internal synchronization pulse becomes unselected.
Bit Iwao (5), sense amplifier (6), output sofa (
The potential in 7) is initialized once by the data of the previous cycle (forced to match the intermediate potential), and then the signal from the previous stage is transmitted and new data is output? It shows. Specifically, the initialized focus line (5) and cell (4) drive to transmit data, and the initialized sense amplifier (6)
The t-bit spelling (5) is driven, and the initialized n-th output buzzer +7) all sense amplifiers (6) are driven.

[Problem that the invention seeks to solve]

Conventional internally synchronous semiconductor memory devices are configured as described above, so that when a large transistor in the output circuit is operated for output, the fluctuations in the GND and V level that occur in the current are reflected in the input signal. Recognizing this as a change, the internal synchronization signal generation circuit operates, and despite initializing the output circuit, tA is applied to the transistor of the output circuit again, causing a change in the GND level.

There is a problem with falling into an oscillation state.

This invention was made in order to solve the above two problems, and is an internally synchronous semiconductor memory device that does not take in the GND level fluctuation caused by operating the output port VR as a change in the input. The whole purpose is to obtain i.

〔assignment? Means for Solving] The internally synchronous semiconductor memory device according to the present invention has an internally synchronous signal generating circuit that operates in response to changes in a human input signal that initializes each internal circuit.
(during initialization and data output) II'i has the function of not operating the internal synchronization signal generation circuit.

[Effect]

The internal synchronization signal generation circuit in this invention generates a pulse to initialize each circuit, and at the same time disables its own operation with a pulse to initialize the output buffer, thereby suppressing fluctuations in the GNOV level during data output. Make it an error that cannot be detected as an input change.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing the configuration of this embodiment. The semiconductor memory device taken as an example is a 5tatic RAM. In FIG. 2, fl) to (7) are the same as the nine shown in the conventional example of FIG. 5, so their explanation will be omitted. (8)
is an internal synchronization signal generation circuit, and unlike the conventional example, a feedback circuit A@ shown in FIG. 2 is newly added. In Fig. 2, the internal synchronization signal that initializes the output stage (7) is simultaneously fed back to the output stage (b) of the internal synchronization signal generation circuit (8), and supplies power to the output stage (b). -ah) Entering the gate of Ranjistaro.

Next, the operation will be explained. FIG. 3 shows how the waveform of a signal processed within the semiconductor memory device shown in FIG. 1 changes over time.

When the input changes, an internal synchronization signal is generated by catching it, passing through the delay circuit αat, and each time vF(word+i@
[3), Pinto @ (5>, sense amplifier (6), output bag 7a (71) Vr-manual input. Figure 3 shows the delay input to each circuit after passing through the delay circuit at) The given internal synchronization signal is shown. The function of the internal synchronization signal is the same as in the conventional example, and is initialized each time to prepare for quickly transmitting the signal from the previous stage.

Now, when the relatively large transistor of the output buffer (7) operates, a large current flows and the internal GND V level fluctuates. This fluctuation in the GND level is the same as a change in the input signal for the internal synchronization signal generation circuit (8). This fluctuation of the input signal occurs simultaneously with the operation of the output buffer (7), but the operation of the output buffer (7) is activated by an internal synchronization signal entering the output buffer (7). In this embodiment, the internal synchronization signal that causes the entire output sofa (7) to operate is fed back to the entire internal synchronization signal generation circuit (8),
What is the internal synchronization signal shown in Figure 2? By carefully shutting off the power that is generated, the internal synchronization signal is prevented from being generated when the output changes.

The input waveform portion of FIG. 3 shows the fluctuation of the input signal as the output changes. In the case of a semiconductor memory device having a conventional internal synchronization signal generation circuit (9), this fluctuation also causes the internal synchronization signal to be fully opened as an input change, so the output buffer (7)
), the output buffer (7) is initialized. In this embodiment, as shown in the internal synchronization signal l part of FIG. 4, no internal synchronization signal is generated.

2. In the above embodiment, the output buffer (7)? Internal synchronization signal to be initialized (internal synchronization signal 4 shown in Figure 3)
) is fed back and input to the output stage α■ of the internal synchronization signal generation circuit (8), but if this signal is not sufficient, the signal may be extended in time by the feedback circuit BQ3 shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the internal synchronization signal that is initially low in the output buffer is fed to the internal synchronization signal generation circuit, and the internal synchronization signal is prevented from being generated at all when the output changes. When the input level fluctuates due to GND V-bell fluctuation, etc., an internal synchronization signal is generated (7), and it does not end up in an oscillation state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an internally synchronized semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an internally synchronized signal generating circuit according to an embodiment of the present invention, and FIG. A diagram showing potential changes in the internal circuit of the circuit shown in FIG.
FIG. 5 is a block diagram showing the configuration of a conventional internally synchronous semiconductor memory device, and FIG. 6 is a conventional internally synchronous semiconductor memory device. FIG. In Figure 2, It) is an input buffer, [2] a decoder, (3) is word line 1, (4) u cell, (5) is a bit line, (6) v'i sense amplifier, (7) il Output sofa, (8) is an internal signal generating circuit, aQ1'' is a delay circuit, a is an output stage, (6) is a feedback circuit A, 0Jri feedback circuit vtB, Q41 is a p-ah) transistor. 2. In the figures, the same reference numerals indicate the same parts, and i-friends indicate corresponding parts.

Claims (1)

[Claims] A semiconductor memory device equipped with an internal synchronization signal generation circuit that is insensitive to self-generated noise.