JPH02189663A - Input/output data transfer system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an input/output data transfer system, and is mainly suitable for controlling an intelligent/OP (input/output processor) of a microcomputer.

[Conventional technology]

In conventional microcomputers, there are two methods for data transfer between the central processing unit (CPU) and the input/output interface:
There are two types of data transfer methods: one in which the input/output interface is mapped to the address space of the CPU and carried out in a program mode using general memory read/write commands, and the other in which data transfer is performed using DMA (direct memory access).

[Problem to be solved by the invention]

Conventionally, the simple input/output (hereinafter referred to as Ilo) interface directly connected to the CPU has a one-to-one correspondence with the outside, so there was no need to check input/output data.
Again, I couldn't actually do it. However, as the performance of microcomputers has improved in recent years, more functions have been added to the I
/O interface now has it. Therefore, in order to reduce the load on the CPU due to the input/output of the I/O interface, an intelligent IOP (input/output interface), which has a built-in microcomputer in the I/O interface and has functions such as data processing and buffering, is used. processors) have come into use. For this reason,
As the amount of data transferred between the CPU and IOP increases, there is a possibility that errors in the transferred data will occur. For data transfer with such intelligent IOPs, there are two methods: the traditional method of using CPU commands, and the method of using IO
There is a method in which a DMA controller is mounted on the P side and DMA transfer is performed. However, many microcomputers generally do not have a bus controller, so the DMA transfer method is not suitable. Therefore, transportation data is not currently checked during data transfer with the IOP. Also, if the IOP has a buffer memory, a large amount of address space is required, so when transferring data from the CPU to the /OP, a series of data is transferred to the buffer memory on the IOP side via the I/O control register. , are transferred sequentially. However, in the system using this buffer memory, the CPU cannot see the data on the IOP side at any time, so it is necessary to check the input/output data on the IOP side by some method. SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide an input/output data transfer method that prevents malfunctions of an input/output interface due to errors in transferred data and improves reliability.

[Means to solve the problem]

In order to achieve such an objective, the present invention provides
When transferring data to the /O interface or from the I/O interface to the CPU, the sending side adds a check SUN to the end of a series of data and sends it, and the receiving side adds the received data and check SUN. It is characterized by detecting errors in received data by comparing the received data.

[Function] The present invention can be used from a CPU to an I/O interface, or from an I/O interface.
When transferring data from the /O interface to the CPU, the sending side adds a check SUM code to the end of a series of data and sends it out, and the receiving side checks the data by comparing the transferred data with check St1M. Since errors are detected, malfunctions of the I/O interface due to data errors can be prevented, and reliability can be improved. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the structure of data in an embodiment of the present invention. Here, 21 is the data start code (STX), 22 is the inverted data of the data start code (STX), 23 is the number of data bytes, 24 is the data, and 25 is the ETX.
(End of Text Character) or ETB (End of Transmission Block Character). When data is divided into multiple blocks, this 25 becomes ETB. 2 and 6 are the BCG of the checksum (StlM) that constitutes the present invention.
(block check character) is added to the end (25) of a series of transfer data and is used for error checking on the receiving side. FIG. 2 shows an overall schematic circuit configuration of an embodiment of the present invention. Here, 1 is a CPU in charge of overall arithmetic control, 2 is a ROM (read only memory) in which control procedures related to the present invention as shown in FIG. 5 are stored in advance, and 3 is used as a work area of the CPUI, etc. RAM (Random Access Memory), and 4 an OP (input/output processor) that controls external input/output devices and processes, stores, and transfers input/output data. CPUI' and other components 2-4
are connected via the main bus 11. FIG. 3 shows the circuit configuration of l0P4 in FIG. 2. here,
5 is a control register used for data transfer control between loPds, 6 is a data transfer RAM, 7 is an MPU (microprocessor), 8 is a ROM pre-stored with the control procedure according to the present invention as shown in FIG. RAM
, and /O are I/O interfaces for transmitting and receiving data with external input devices. MPU7 is day albo-
) Main bus 11 via RAM 6 and control register 5
The main bus 11 is connected to the main bus 11 to transfer data. FIG. 4 shows the structure of the control register 5 of FIG. Here, 31 is the device status register (STR)
, 32 is a data register (DTR), 33 is an address register (ADH), and 34 is an interrupt control register (IRGX). Next, the operating procedure of the present invention will be explained with reference to the flowcharts of FIGS. 5(A) and 5(B). When transferring data from the CPU in Figure 2 to the l0P4 in Figure 3, the CPU divides the series of data into multiple blocks and checks each block for each block, as shown in Figure 5 (A). A sum (BCC) code is added and data with a checksum is transferred (steps 31 to S6). When the data transfer is completed, an interrupt is output to the l0Pd side (step S7). On the l0Pd side, in response to the above-mentioned interrupt, as shown in FIG.
ll, 512), checks the check sum of the received data (step 313), and if the check sum and the calculated value match, the data is transmitted (
Step 514), and notify the main CPUI of the device end (Step 315). In the event of a data error where the chain sum and the calculated value do not match, the main CPU is notified of the device error (step 516). When inputting data from an external input/output device, use l0P.
The data transfer request is notified from the 4 side to the CPUI and the process shown in Fig. 5 (
Executing the procedure A), CP[11 sequentially reads data from l0P4 and checks the data according to the procedure shown in FIG. 5(B).

【Effect of the invention】

As explained above, according to the present invention, a checksum is added to the end of transferred data, and data errors are detected based on the checksum on the I/O interface side. This has the effect of preventing malfunctions of the H.170 interface and improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a format diagram showing the configuration of transfer data according to an embodiment of the present invention, FIG. 2 is a block diagram showing the overall schematic circuit configuration of an embodiment of the present invention, and FIG. FIG. 4 is a block diagram showing the circuit configuration of the IOP in FIG. 4; FIG. 4 is a layout diagram showing the configuration of the control register in FIG. 3; FIG. be. 1... Main CPU. 2...ROM. 3...RAM. 4...IOP. 5...Control register, 6...Dial port RAM, 7...MPU. 8...ROM. 9...RAM, /O...IO interface, 26...
Transfer data check SUM (BCC). View/O View 2 Figure 11 Main BUS Figure 3 Light 4 Figure Ryo

Claims (1)

[Scope of Claims] When transferring data from the CPU to the I/O interface and from the I/O interface to the CPU, the sending side adds a check SUM to the end of a series of data and sends the data, On the receiving side, the received data and the check SUM
An input/output data transfer method characterized by detecting the quality of received data by comparing it with the data.