JPH0353663B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a multi-CPU that performs data transmission between a master CPU and one or more slave CPUs.
This invention relates to a transmission data check method.

[Technical background of the invention and its problems] Conventionally, a master CPU and one or more slaves
In a system that transmits data between CPUs, for example, from the master CPU to the slave CPU
There are two known methods: one in which data is transmitted unilaterally from the master CPU to the slave CPU, and another in which the slave CPU receives the transmitted data and sends only an ACK code or NACK code back to the master CPU. .

However, with the former method, if there is a failure such as a disconnection or noise in the transmission line, or if the slave
Slave due to hardware or software failure on CPU side
Master even if the CPU goes out of control.
The drawback of the CPU was that it could not be judged at all. In addition, in the latter method, only the ACK code or NCAK code is sent back, so there is a risk of misunderstanding the code due to noise. Also, if there is a failure such as a disconnection or noise in the transmission line, or if the slave CPU side If there is a hardware or software failure, the master CPU can determine the event, but it has the drawback that it cannot determine the nature of the failure.

[Object of the invention] This invention was devised to eliminate such drawbacks, and the master CPU is connected to the slave CPU.
The purpose of this invention is to provide a system for checking transmission data in a multi-CPU system that can more reliably check the transmission status of data, including its events and contents.

[Summary of the Invention] The present invention provides a method for transmitting data between a master CPU and one or more slave CPUs.
When a command is transmitted from the master CPU to the slave CPU, the slave CPU checks the status of the command, and if the command status is normal, transmits the command to the master CPU along with the ACK code as a command echo, and then checks each bit of the command. Transmits a check BCC code created by exclusive OR, and if the command status is abnormal, transmits the command along with a NACK code to the master CPU as a command echo,
Next, an error status indicating the abnormality is transmitted, and the master CPU receives the message from the slave CPU.
The purpose is to check the data transmission status from the ACK code or NACK code, command echo, and BCC code or error status.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in this example, the master CPU
The case where there is a 1:1 relationship between the CPU and the slave CPU will be described.

Figure 1 is a block diagram, 1 is the master CPU,
2 is a slave CPU. Said master CPU1
is connected to ROM (read-only memory) 4 and RAM (random access memory) via data bus 3.
A memory) 5 and various input/output devices 6 other than the mechanical section are connected. The slave CPU 2 is connected to the ROM 8, RAM 9 and I/O via the data bus 7.
Port 10 is connected. Various mechanical mechanisms are connected to the I/O port 10. The master CPU1 and slave CPU2 are port A
A control signal line 12 is connected through port B11, and a bidirectional data bus 14 is connected through port B13. The master CPU
1 and slave CPU 2 perform control operations based on program data stored in ROMs 4 and 8, respectively.

The master CPU 1 is set to perform the program processing shown in FIG. That is,
First, check whether port B13 is empty, and if it is empty, set "1" to port A11.
Set the ID data of Then port B13
Set the command to . This command is a command consisting of a single byte with ID = 1, as shown in Figure 2 a, where 1 byte consists of 8 bits, or a command consisting of ID = 1 and ID = 0, as shown in Figure 2 b. The command consists of multiple bytes.
For ID=1, the 6 bits from the 2nd bit to the 7th bit are the command storage area, the 1st bit is the execution wait bit storage area, and the 0th bit is unused. In the command section with ID=1, data representing the nature of the command group is set. If the command consists of multiple bytes, the port 1
With the command set on 3B, port B
13 commands are read into the slave CPU 2 and waits until it becomes empty. and the port B13
When the port becomes empty, the ID data of “0” is transferred to the port A.
11, and a command with ID=0 is set to the port B13. This process with ID=0
Repeat this until all commands have been set. When all the commands with ID=0 have been set, the ACK code or
It enters the state of waiting for NACK code input. Note that in this process, if the port B13 is not empty, the execution right is always transferred to the monitor.

The slave CPU 2 is set to perform the program processing shown in FIG. That is,
When data with ID=1 is set in the port A11 and a command is set in the port B13, the data of each port A and B is fetched,
Start a 20ms timer. Fetch the next command during this 20ms. If there is an instruction to cancel a command during this time, the current command will be interrupted and a new command will be accepted. When this timer times up, the table for the command with ID=1 is searched, and if that command is found in the table, the number of subsequent commands is checked. this is
This is done by checking the number of commands set in the command section with ID=1 and the number of commands actually captured. If a match is confirmed in this check of the number of commands, it is confirmed that the port B13 is empty, and then ID=1 is set in the port A11, and a 6-bit command echo and a 2-bit command echo are output as shown in a in FIG. ACK data consisting of ACK code "00" is set to port B13. This ID=1
data and ACK data are sent to the master CPU1.
When the data is read in, ID=0 is set to port A11, and the 8-bit data is read as shown in Figure 3b.
Set the BCC code to port B13. The BCC code at this time is a code created by exclusive ORing each bit of all the commands taken in from the master CPU 1. Next, the first bit of the command with ID=1 fetched from the master CPU 1 is checked to see if the wait bit is set. If the wait bit is set, the command is executed after a wait time is set; if the wait bit is not set, the command is executed immediately. After execution, return this process.

Also, in this process, if the command with ID = 1 taken in from the master CPU 1 is not in the table or the number of commands does not match, ID = 1 is set to port A11, and the 6-bit Command echo and 2-bit
NACK data consisting of NACK code is sent to port B.
Set to 13. Next, when port B13 becomes empty, ID = 0 is set to port A11, and an 8-bit error status is set to port B13 as shown in Figure 4b.Finally, the receive buffer is cleared and this process is completed. end. Note that the error status has the 0th bit as ID=1 and undefined command information, the 1st bit as an unused bit, the 2nd bit as information indicating that the number of commands is larger than the specified value, and 3 as the error status. The 1st bit is information indicating that the number of commands is less than the specified number, the 4th bit is information indicating that a new command has been received before all commands have been executed, and the 5th bit is information indicating that the command group is received by slave CPU 2. The 6th bit is information indicating that the buffer is full, and the 6th bit is information indicating that there is no command with ID=1.
The 7th bit is used as information indicating other errors.

When the master CPU 1 reads an ACK code or NACK code from the slave CPU 2, it performs the interrupt process shown in FIG. 7. That is, the transmission data from the slave CPU 2 is read through the port B13. When the BCC code or error status is read, the interrupt processing shown in FIG. 8 is performed. In other words, when it is ACK data, check the command echo match, and then
Check BCC code match. Only when everything matches does it determine that the transmission data has been transmitted normally and returns. Also,
Even if it is NACK data or ACK data, if the command echo or BCC code does not match, it is determined that there is an abnormality in data transmission, stores the error status in RAM 5, and returns.

In the device of this embodiment configured in this way, when a command is transmitted from the master CPU 1 to the slave CPU 2, the slave CPU 2 checks whether the command with ID=1 that has been taken in is present in the table, and if there is, Then check the number of commands. If the number of commands also matches, ACK data consisting of a command echo and an ACK code is transmitted to the master CPU 1. Additionally, transmit a BCC code. Also, if the command with ID=1 is not in the table or the number of commands does not match, NACK data consisting of a command echo and a NACK code is transmitted to the master CPU 1. It also transmits error status. Therefore, the master CPU 1 can determine the state of transmitted data not only by ACK and NACK but also by command echo. Therefore, it can be reliably determined that the transmission was performed normally. Further, even if the data transmission line is broken or if there is a failure due to noise, it is possible to reliably determine that an abnormality has occurred based on the state of the command echo. Furthermore, in the case of an abnormality, the detailed content can be determined based on the error status.

In this way, the transmission status can be checked more reliably, not only regarding the event, but also including the details of the abnormality, whether it is due to a disconnection or noise.

Note that the embodiment described above is based on the master CPU.
The above description applies to cases where the master CPU and slave CPU have a 1:1 relationship, but this is not necessarily the case.
It can also be applied to so-called inline systems in which there is a 1:multiple CPU relationship.

[Effects of the Invention] As detailed above, according to the present invention, the master CPU can more reliably check the status of data transmission to the slave CPU, including its events and contents. We can provide methods.

[Brief explanation of drawings]

The figures show an embodiment of the invention, with Figure 1 being a block diagram, Figure 2 being a diagram showing the configuration of commands,
Figure 3 is a diagram showing the data structure when returning an ACK, Figure 4 is a diagram showing the data structure when returning a NACK, Figure 5 is a flowchart showing the program processing of the master CPU, and Figure 6 is the program processing of the slave CPU. Flowchart showing the master CPU's ACK, Figure 7 shows
Flowchart showing interrupt processing when receiving NACK, No. 8
The figure is a flowchart showing interrupt processing when the master CPU receives a BCC code and error status. 1...Master CPU, 2...Slave CPU, 4,
8...ROM (read only memory), 11...Port A, 13...Port B, 14...Bidirectional data bus.

Claims (1)

[Claims] 1 Master CPU and one or more slave CPUs
When transmitting data between
When a command is transmitted from the CPU to the slave CPU, the slave CPU checks the status of the command, and if the status of the command is normal, transmits the command to the master CPU as a command echo along with an ACK code. A check BCC code created by exclusive OR of each bit is transmitted, and if the command status is abnormal, it is sent to the master CPU.
The command is transmitted as a command echo along with the NACK code, and then an error status indicating the abnormality is transmitted to the master CPU.
Then the ACK code from the slave CPU or
A multi-CPU characterized by checking the data transmission status from NACK code, command echo, BCC code or error status.
transmission data check method.