JPH02189794A - Memory ic - Google Patents

Abstract

PURPOSE:To constitute a system with the less number of components by providing plural memory element blocks, providing an address latch to an address given to each of the blocks and providing a terminal through which the address latch is controlled. CONSTITUTION:The system is provided with address latches 102, 106, memory element blocks 103, 107 and address latch control terminals 104, 108. An address signal inputted to an address input terminal 101 is inputted to the address latches 102, 106 and the latch control is implemented independently by the signal inputted to the address latch control terminal 104 or 108 and the latched address signal is inputted to the memory element block 103 or 107 connecting to the terminal. The write/read to the memory element block 103 or 107 is controlled to implement by the read write control terminal 105 or 109 independently. Thus, the number of components constituting the memory section is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to memory ICs.

[Conventional technology]

Figure 3 shows an internal block diagram of a conventional memory IC, and shows a general timing diagram of memory read in a function in which address output precedes data read/write (hereinafter referred to as address first-out method) in memory read/write operations by a computer. Figure 4 shows a computer system using a conventional memory IC and a first-address computer.
An example of the system configuration is shown in FIG.

In FIG. 3, 301 is a group of address input terminals of a conventional memory IC, 302 is a memory element block that stores data, 303 is a read/write control terminal that controls reading and writing to the memory element block 302, and 304 is a control terminal for inputting and outputting data. This shows the data input/output terminal group.

When writing data to the conventional memory IC shown in FIG.
4, then controls the read/write control terminal 303,
When reading data, address input terminal group 30
1 to control the read/write control terminal 303 to read data. At this time, it was necessary to keep the address signal input to the address input terminal group 301 stable until reading and writing are completed.

Next, a fourth example of the configuration of a computer system using a conventional memory IC and a computer with an address first-out system is shown.
This will be explained using the diagram and FIG.

Reference numerals 401 and 402 indicate memory read operations based on the address first-out method, 403, 404, and 405 indicate address outputs at that time, and 406 and 407 indicate data read in each read operation.

501 is a first-out address computer; 502.
504 is an address latch, 503° 505 is a conventional memory IC 1506 is an address latch control circuit, 509
, 510 is an address latch control signal, 507 is a read/write control circuit, 511.512 is a read/write control signal, 50
8 is an address bus, 513 is a data bus, and 514 is a control signal output from the computer.

Address 1 (403) output from the computer 501 using the address first-out method in the read operation of 401
is the address latch control circuit 506.
It is latched into address latch 502 by latch control signal 509 . Furthermore, the address latched in the address latch 502 is given to the conventional memory IC 503,
A read/write control signal 511 is output from the read/write control circuit 507 . As a result, the memory IC 503 outputs data 1 (406) after a certain period of time. However, the computer 501 outputs the next address 2 (404) without waiting for this data 1 (406) to be output. This address is latched into address latch 504 by address latch control signal 510, similar to the procedure described above, and provides an address signal to conventional memory IC 505. However, in this case, the read/write control signal 512 is not output yet.

After outputting address 2 (404), computer 501 reads data 1 (406) if it is ready, and then outputs the next address 405. At this time, the read/write control signal 512 is output and the memory IC 505
It becomes possible to output data 2 (407). in this case,
Since the memory IC 505 has already been given an address signal by the address latch 504, the above-mentioned data 1
Data 2 (
407) is output.

[Problem to be solved by the invention]

When configuring a computer system using a computer using the address first-out method with the conventional memory section described above, an IC for latching the address is required, and there is a problem that the number of parts increases when configuring the memory section. Ta.

[Means to solve the problem]

The memory IC of the present invention has a plurality of memory element blocks within the memory IC, has an address latch for each address given to each memory element block, and has an address latch for each address given to each memory element block. The address/
It has a terminal for controlling the latch.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an internal block diagram of an embodiment of the present invention, and FIG. 2 shows an example of a configuration of a computer system using a first-address type computer using a memory IC of the present invention.

FIG. 1 is an internal block diagram in one embodiment of the present invention, in which 101 is a group of address input terminals of a memory IC of the present invention, 102 and 106 are address latches, 103 and 107 are memory element blocks, and 104 and 108 are Address latch control terminals, 105 and 109 are access control terminals, 110 is a data input/output terminal group, and 111 is a memory IC of the present invention.

The address signal input to the address input terminal 101 is
Inputs to address latches 102 and 106. Latch control of address latches 102 and 106 is performed independently by signals input to address latch control terminals 104 or 108, respectively. address latch 102
Alternatively, the address signal latched in 106 is input to the memory element block 103 or 107 connected to each address latch. Reading and writing to the memory element block 103 or 107 can also be controlled independently using the read/write control terminals 105 or 109. Next, using FIGS. 1, 2, and 4, the address of the memory IC of the present invention will be described. An embodiment in which a computer system is configured using a first-out type computer will be described.

201 is an address first-out system computer; 202 is an address latch control circuit; 203 is an access control circuit; 204 is an address bus; 205 and 206 are address latch control signals; 207 and 208 are read/write control signals; A bus 210 represents a control signal output from a first-address computer.

In the memory read operation of 401, address 1 (40
3) is output and latched into the address latch 102 by the address latch control stop signal 205 from the address latch control circuit 202.

Further, the address latched by the address latch 102 is given to the memory element block 103, and the read/write control circuit 203 outputs a read/write control signal 207.

This allows the memory element block 103 to output data 1 (406) after a certain period of time. The computer 201 outputs the next address 2 (404) without waiting for this data 1 (406) to be output. This address is latched into the address latch 106 by the address latch control signal 206 in the same manner as in the procedure described above, and provides an address signal to the memory element block 10'7. However, in this case, the reading control signal 208 is not yet output.

After outputting address 2 (404), computer 201 reads data 1 (406) if it is ready, and then outputs the next address 405. At this time, the read/write control signal 208 is output, and the memory element block 107 is enabled to output data 2 (407). In this case, since the memory element block 107 has already been given an address signal by the address latch 106, it is possible to output data 2 (407) in a shorter time than the time required to output data 1. It is possible.

〔Effect of the invention〕

As explained above, a memory IC has a plurality of memory element blocks, has an address latch for the address given to each memory element block, and has an address latch external to the memory IC. By having terminals for control, it is possible to configure a computer system using a first address type computer with a reduced number of parts.

[Brief Description of the Drawings] Fig. 1 is an internal block diagram of the present invention, 101...Address input terminal group, 102, 10
6... Address latch, 103, 107...
...Memory element block, 104, 108...
...Address latch control terminals, 105, 109...
. . . read/write control terminal, 110 . . . data input/output terminal group, 111 . . . memory IC of the present invention. FIG. 2 is a side view of a computer system configuration using the memory IC of the present invention, 201...address first-out type computer;
202... Address latch control circuit, 203
...Read/write control circuit, 204...Address bus, 205.206...Address.
Latch control signal, 207.208... Read/write control signal, 209... Data bus, 210...
·····Control signal. FIG. 3 is an internal block diagram of a conventional memory IC, 301.
... Address input terminal group, 302 ... Memory element block, 303 ... Read/write control terminal, 304 ... Data input/output terminal group. Figure 4 is a memory read timing diagram of the address first-out method, 401.402...Memory read operation, 40
3゜404.405・・・Address output, 406
,407...data. FIG. 5 is a side view of the configuration of a computer system using a conventional memory IC. 501...address first-out system computer,
502.504 Address latch, 503
゜505... Conventional memory IC, 506...
... Address latch control circuit, 509, 510...
...Address latch signal, 507... Read/write control circuit, 511.512... Read/write control signal, 508... Address bus, 513
...Data bus, 514...Control signal. Agent Patent Attorney Uchihara Spine? Figure 3

Claims (1)

[Claims] It has a plurality of memory element blocks, and has an address latch for an address given to each of the memory element blocks,
A memory IC characterized by having an external terminal for controlling the address latch.