JPH02201515A - Initial data reset control circuit - Google Patents

Abstract

PURPOSE:To reduce the number of used ICs by writing reset data of a data receiving register in all output registers at the time of power-on to use only one register having an output control function as the output register of each line. CONSTITUTION:At the time of power-on, a reset signal 8 is validated and a select signal 11 as the output of an initial reset flip flop 10 selects and A line of a data selector 9. Consequently, the data selector 9 outputs a reference timing 7 connected to the A line to clock inputs T of output registers 12 and 13. Since a data receiving register 2 is reset at this time, reset data is written in output registers 12 and 13 and contents of output registers 12 and 13 are outputted to respective bus lines. Thus, only one register having the output control function is required for each line like output registers 12 and 13, and the number of used ICs is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an initial data reset control circuit that resets the contents of an initial data output register and controls the output in a system having various digital data registers. It is something.

[Conventional technology]

A block diagram of a conventional circuit of this type is shown in FIG. In the figure, 2 is a data reception register that accepts data from data bus 1, 4 is a data reception register write timing, 3 is a data bus that connects multiple output registers, 12 is a first output register, and 5 is a first output Register write timing, 18 is the first output register 12 and the first
A data bus connecting with the output buffer 20, 14 a first output buffer output enable signal, 22 a data bus from the second output buffer 20, 13 a second output register, 6
is the second output register write timing, 19 is the second output register write timing, and 19 is the second output register write timing.
A data bus connects the output register 13 and the second output buffer 21, 15 is a second output buffer output enable signal, 23 is a data bus from the second output buffer 21, and 8 is a reset signal.

Next, the operation will be explained. When the power is turned on, the contents of the first output register 12 are reset by the reset signal 8, and the contents of the first output register 12 are reset by the first output cover enable signal 14.
is sent to the data bus 22 by. When the data on data bus 1 is confirmed, the data is taken into data reception register 2 at data reception register write timing 4,
The data on data bus 3 is confirmed. At first output register write timing 5, the data on the data bus 3 is taken into the first output register 12, and the data on the data bus 18 is finalized. The first output buffer output enable signal 14 causes the data on the data bus 18 to be sent to the data bus 22 by the first output buffer 20. The above operation is similar in other lines of the system including the second line, which are configured with a plurality of registers.

[Problems to be Solved by the Invention] The conventional initial data reset control circuit is configured as described above, and in order to reset all the contents of each output register and perform output control when the power is turned on, a reset circuit is used. It is necessary to use an output register and an output cover sofa with an output control function, and in the case of a system that uses multiple output registers, the number of ICs used increases and the mounting area is large compared to the function. There was a problem.

This invention was made to solve the above-mentioned problems, and is an I/O system that can be implemented without impairing conventional functions.
An object of the present invention is to obtain an initial data reset control circuit that can freeze C.

[Means to solve the problem]

The initial data reset control circuit according to the present invention includes:
At power-on, the contents of the data reception register are reset, and by using the selection signal from the initial reset flip-flop to set the output of the data selector to the reference timing, reset data is written to each of the multiple output registers, and after the reset signal is released, , the contents of the data reception register are taken into each output register by setting the output of the data selector as the writing timing to each output register by the selection signal from the initial reset flip-flop.

[Effect]

In this invention, the initial reset flip-flop outputs a selection signal to the data selector so as to output the reference timing when the reset signal is valid;
By outputting a selection signal to output each register write timing when the reset signal is released, the reset data of the data reception register is written to all output registers at power-on, and the output register of each line has an output control function. Since only one register is required, the number of ICs used is reduced.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 1 is a block diagram of an initial data reset control circuit according to an embodiment of the present invention. In the figure, the same reference numerals as those in the conventional circuit indicate the same or equivalent functional parts. Further, 9 is a data selector, 10 is an initial reset flip-flop (F/F), 1) is a selection signal, 1
6 is a data bus for outputting the contents of the first output register 12, and 17 is a data bus for outputting the contents of the second output register 13.

Next, the operation of the circuit shown in FIG. 1 will be explained.

When the power is turned on, the reset signal 8 becomes valid, and the selection signal 1) output from the initial reset F/F 10 selects the A line of the data selector 9. therefore,
The data selector 9 outputs the reference timing 7 connected to the A line to the clock input T of each output register. Also, at this time, since the data reception register 2 has been reset, reset data is written to each output register. The contents of each output register are output to each pass line by each output register output enable signal.

When reset signal 8 is released, initial reset F
The selection signal 1) which is the output of /FIO is the data selector 9.
Select line B. The data reception register 2, which has taken in the data on the data bus 1 at the data reception register write timing 14, outputs the contents to the data bus 3. Due to the first output register write timing 5,
The first output register 12 takes in the data on the data bus 3. The first output register output enable signal 14 causes the contents of the first output register 12 to be transferred to the data bus 16.
is output to. Thereafter, similar operations are performed for lines including other output registers.

In such a circuit, each output register only needs one register with an output control function, and there is no need to use a conventional output buffer, so the number of ICs used is reduced, and especially when a large number of registers are When used in a system, approximately half the IC is required, reducing the mounting area.

In the above embodiment, an inverter and an R-S flip-flop were used as the initial reset flip-flop 10, but as shown in FIG. In general, fewer ICs are required and the same effects as in the above embodiments are obtained.

In addition, Figure 3 shows a circuit in which the output of the data reception register 2 is controlled by the initial reset flip-flop 10. In this case, the data bus 3 must be pulled up and each output register must have an inverting function. However, the same effect as the above embodiment is achieved.

〔Effect of the invention〕

As described above, according to the initial data reset control circuit according to the present invention, the contents of the data reception register are reset at power-on, and the reset data is referenced to the output of the data selector using the selection signal from the initial reset flip-flop. Since the configuration is configured such that all output registers are written at the timing, each output register requires only one register with an output control function, which has the effect of reducing the number of ICs used and greatly reducing the mounting area.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an initial data reset control circuit according to an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing an initial data reset control circuit according to another embodiment of the invention, and FIG. The figure is a block diagram showing a conventional initial data reset control circuit. 1 is the data bus, 2 is the data reception register, 5゜6 is the output register write timing, 7 is the reference timing, 8
9 is a reset signal, 9 is a data selector, 10 is an initial reset flip-flop, 1) is a selection signal, 12.
13 is an output register. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 2

Claims (1)

[Claims] (1) In the initial data reset control circuit, a data reception register that accepts data from the data bus and is reset based on a reset signal, a plurality of output registers that take in data from the data reception register, and each output. A data selector that selects and outputs the reference timing or write timing to a register; and a selection signal that selects the reference timing when the reset signal is valid and the write timing when the reset signal is released, to the data selector. An initial data reset control circuit comprising an initial reset flip-flop.