JPH0219026A - Serial data reproduction circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a serial data reproduction method that separates and reproduces a clock signal and a data signal from a serial composite signal in which a clock signal and a data signal are synthesized at regular intervals. Related to circuit devices.

[Prior art and its problems] Conventionally, a serial composite signal in which a clock signal and a data signal are synthesized at regular intervals has a reference clock signal outputted from an oscillator and a signal outputted from a counter, so that the serial data is The data signal is extracted from.

However, if only the demodulation section that demodulates the serial data signal is integrated into an IC, there is a problem that an oscillator that generates the reference clock signal is required, and if a counter is used, the time can be set by the input signal. There was a problem in that a circuit was required to change it.

The present invention has been made in order to solve the above-mentioned problems, and provides a serial data reproducing circuit device that does not require a reference clock oscillator or an individual circuit and can change time settings using an input signal. The purpose is to

[Means for Solving the Problems] The present invention provides one input terminal into which a serial composite signal in which a clock signal and a data signal are serially combined is inputted via one line, and a terminal in which a serial composite signal is inputted via one line. a clock terminal that outputs an output clock signal corresponding to the clock signal of the serial composite signal; an output data terminal that outputs an output data signal that corresponds to the data signal in the serial composite signal;
signal separating means for separating a serial composite signal input from two input terminals into an output clock signal and an output data signal, outputting the output clock signal to the output clock terminal, and outputting the output data signal to the output data terminal. It is characterized by:

[Operation] The signal separating means separates a serial composite signal in which a clock signal and a data signal inputted from an input terminal are serially combined, outputs an output clock signal to an output clock terminal, and outputs output data to an output data terminal. Output a signal.

[Embodiment] In FIG. 1 showing an embodiment of the present invention, a comparator 1 has a potential at a non-inverting input terminal 1-1 that is lower than an inverting input terminal 1-1.
When the voltage exceeds the reference potential set by the voltage dividing resistors 2 and 3 applied to the voltage divider 2, an H (high) level signal is output.

A non-inverting input terminal 1-1 of the comparator l is grounded via an integrating capacitor 4, and a constant current source 5 and an NP
Connected to the collector of N-type transistor 6. Further, the emitter of the transistor 6 is grounded, and the base of the transistor 6 is connected to the output side of the AND circuit 7.

comparator! The output side of is the input end of a D-type flip-flop (abbreviated as FF in the drawing) circuit 8 that latches the input signal at the rising edge of the clock signal, and the input end of the D-type flip-flop (abbreviated as FF in the drawing) circuit 8 that latches the input signal at the rising edge of the clock signal. It is connected to the clock terminal C of the flip-flop circuit 9 and also to the clock output terminal it which outputs an output clock signal via an inverter 0. The output side Q of the flip-flop circuit 8 is connected to the input side of the flip-flop circuit 9 and the input side of the AND circuit 7. The inverting output Q of the flip-flop circuit 9 is connected to a data output terminal 12 for outputting an output data signal. Further, the manual data terminal 13 to which the serial composite signal is input is connected to the input side of the AND circuit 7 and the clock terminal C of the flip-flop circuit 8.

The operation of the serial data reproducing circuit of the present invention configured as described above will be described below with reference to FIG.

The serial composite signal input to the input data terminal 13 is a serial signal in which a clock signal and a data signal are synthesized at regular intervals, as shown in FIG. 2(A).

It should be noted that the clock signal constituting the serial composite signal is referred to as a serial composite clock signal, and the data signal is referred to as a serial composite data data signal.

A time chart of the output signal of the AND circuit 7 is shown in FIG. 2 (E), and the time t81 in FIG. 2 (E) is the time t.

When the output signal of the AND circuit 7 is at H level, the transistor 6 is turned on and the integrating capacitor 4 is reset, as shown in FIG. The time chart of the output signal of comparator 1 is shown in FIG.
6, etc., the comparator 1 changes from an H level signal to a low level signal. Also, between time t and time t5 in FIG. 2(e).

As shown between time t6 and time t, when the output signal of the AND circuit 7 is at L level, the transistor 6 is off and the integrating capacitor 4 is charged by the constant current source 5. Then, as shown in FIG. 2(a), the potential A of the non-inverting input terminal 1-1 of the comparator 1 changes, for example, at time L.
a, as shown at time tl, when the potential B of the inverting input terminal 1-2 of the comparator l is exceeded, the comparator l
The output signal changes from an L level signal to a 14 level signal as shown in FIG.

In order for the output signal of the comparator l to change according to the clock signal during serial synthesis in a serial composite signal in which a clock signal and a data signal are synthesized at a regular cycle, it is necessary to ), after the integrating capacitor 4 is reset by the clock signal during serial synthesis, the non-inverting input terminals 1. -1
The data signal during serial synthesis is input before the potential A of the comparator 1 reaches the potential B of the inverting input terminal 1-2 of the comparator 1, and by the time the next clock signal during serial synthesis is input, the potential A has reached the above potential. Must exceed B.

To achieve this condition, the time required for the output signal of the comparator l to change from L level to H level as shown at time 14 from time t, for example, must be equal to the pulse of the serial composite signal shown in FIG. 2(A). It is preferable to set it to 1.2 to 1.8 times the minimum interval, for example, the time from time t1 to time t.

Then, the output signal of comparator 1 is output from inverter lO
The signal is inverted at , and becomes the output clock signal shown in FIG.

Therefore, the rise of the output clock signal appearing at the clock output terminal 11 is synchronized with the rise of the serial synthesis clock signal.

The flip-flop circuit 8 latches the input signal at the rising edge of the clock signal. For example, if we focus on time t, the flip-flop circuit 8 latches the input signal at the rising edge of the clock signal. At the rising edge of the data signal, the L level signal shown in FIG. [H that is input to the flip-flop circuit 8 at
Outputs a level signal. Flip-flop circuit 8 below
As shown in FIG. 2(1), the comparator shown in FIG. Latch and output the output signal.

Like the flip-flop circuit 8, the flip-flop circuit 9 also latches the human input signal, that is, the output signal of the flip-flop circuit 8, at the rising edge of the clock signal, that is, the output signal of the comparator 1. latches the L level signal shown in FIG. 2 (1) input to the flip-flop circuit 9 at the rising edge of the output signal of the comparator 1 shown in FIG. The signal is inverted and output from the inverting output terminal Q of the flip-flop circuit 9 as shown in FIG. 2(g). Then, at time L7 when the output signal of the comparator 1 rises, the flip-flop circuit 9 inverts the H level signal input to the flip-flop circuit 9 and outputs the inverted signal. Thereafter, as shown in FIG. 2(g), the flip-flop circuit 9 outputs the output signal of the flip-flop circuit 8 shown in FIG. 2(1) at the rising edge of the output signal of the comparator l in FIG. The signal is latched, inverted, and output to the data output terminal 12.

As described above, the serial composite signal in which the clock signal and the data signal are combined in a serial state as shown in FIG. The signal is separated into the output data signals shown in g). The output state of the output data signal shown in FIG. 2 (g) at the rise time of the output clock signal shown in FIG. 2 (g) becomes valid output data.

That is, the data signal during serial synthesis at H level at time t3 shown in FIG. 2(A) becomes an H level signal at time t shown in FIG. 2(G), and at time t shown in FIG. 2(A), The serial synthesis data signal at L level at time t becomes the L level signal at time t shown in FIG. 2 (g), and the H level signal at time j+o shown in FIG. ), and the same applies hereafter.

[Effects of the Invention] As detailed above, according to the present invention, a serial composite signal manually input from one input terminal is separated into an output clock signal and an output data signal, and the output clock signal is outputted to the output clock terminal. However, since the output data signal is equipped with a signal separation means that is output to the output data terminal, even if the demodulation section that demodulates the serial data signal does not have a reference clock signal oscillator, it can be synchronized with the clock signal in the serial composite signal. The clock signal can be obtained and the data in the serial composite signal can also be read.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a serial data reproducing circuit according to the present invention, and FIG. 2 is a time chart diagram of the circuit shown in FIG. DESCRIPTION OF SYMBOLS 1... Comparator 7... AND circuit, 8 and 9... Flip-flop circuit, 11... Clock output terminal, I2... Data output terminal, 13... Input data terminal. Patent applicant Rico Co., Ltd. - Agent Patent attorney Aoyama Hajime and 1 other person

Claims (2)

[Claims] (1) A serial composite signal in which a clock signal and a data signal are serially combined is input via one line.
a clock terminal for outputting an output clock signal corresponding to the clock signal in the serial composite signal; and an output data terminal for outputting an output data signal corresponding to the data signal in the serial composite signal; signal separating means for separating a serial composite signal input from two input terminals into an output clock signal and an output data signal, outputting the output clock signal to the output clock terminal, and outputting the output data signal to the output data terminal. A serial data reproducing circuit device characterized by: (2) The signal separating means includes an integrating circuit having a constant current source and a capacitor, a comparator that outputs a signal when the potential output from the integrating circuit exceeds a set potential, and an output signal of the comparator. a first flip-flop circuit that latches with the pulse of the serial composite signal, latches the output signal of the first flip-flop circuit with the pulse of the output signal of the comparator, and inverts the latched signal. 2. The serial data reproducing circuit device according to claim 1, further comprising a second flip-flop circuit for outputting.