JPH04200088A - Heterodyne signal automatic detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an automatic heterodyne detection device used in a frame synchronizer, time base collector, etc. that simultaneously handles a standard video signal and a hetero gain signal having time axis fluctuations.

Prior Art Conventionally, this type of heterodyne auto-detection circuit uses a burst signal of the input signal and a composite sync signal to
By extracting the difference between the SC signal and the hetero gain signal through an amplifier, converting it into a pulse through a comparator and an integrator, and shaping the waveform with a mono multivibrator,
It was creating a discrimination signal.

FIG. 4 shows the configuration of a conventional automatic heterodyne detection device. In Fig. 4, ■ is an operational amplifier (hereinafter referred to as an OP amplifier) that manually detects and outputs a burst signal from the video signal using the chroma signal and BF pulse of the video signal.
, 2 inputs an inverted signal obtained by inverting the output of this ○P amplifier 1 with an inverter 1a, a composite sync signal, and a BF pulse, and outputs a constant output when the standard NTSC signal is used, and an unsteady output when the heterodyne signal is used. This is a gate that outputs continuous pulses.

In addition, (b) directly inputs the composite sync signal to the J terminal, inputs the terminal through the inverter IC, inputs the burst pulse to the T terminal, and outputs from the Q terminal to the gate) 1d (NAN gate). A flip-flop (hereinafter referred to as J-K FF
).

A gate pulse is input to the second input terminal of the gate controller 1d through an inverter 1e.

3 is a ○P amplifier which inputs the output of gate 1d and the output of gate 2 and amplifies the level of the output of gate 2 in the case of a hetero gain signal including jitter, and 4 inputs the output of OP amplifier 3 to a predetermined reference voltage v1. This is a comparator that compares with v2 and outputs a pulse.

5 connects the output of comparator 4 to resistor R1 and capacitor C1.
6 is a mono multivibrator that inputs the output of ○P amplifier 5 and shapes the waveform.
8 is a buffer, and 8 is a gate (based on an inverter) that outputs a discrimination signal.

Next, the operation of the above conventional example will be explained with reference to the waveform diagrams of FIGS. 5(a) to 5(j). Points a to j in Figure 4
The waveforms shown in FIGS. 5(a) to 5(j) appear at the points.

When the video signal (chroma signal) and BF pulse shown in FIG. , a signal as shown in FIG. 5(b) is output.

The output of this OP amplifier 1 is applied to the gate 2 through an inverter 1a. A composite sync signal and a BF pulse are also applied to this gate 2, and by taking the logical sum of these signals, the six output points of the gate 2 are outputted as shown in the solid line pulse in Fig. 5(C). , constant output for standard NTSC signals, and Fig. 5 (c) for heterodyne signals.
) is output as a discontinuous pulse as shown by the broken line, and is further applied to the (-) input terminal of the OP amplifier 3. A predetermined reference voltage is applied to the (+) input terminal of this OP amplifier 3.

On the other hand, when the composite sync signal applied to one point of J-K FF1b is at the rHJ level, the burst pulse input to the T terminal causes the terminal Q to reach the rHJ level, and when the J terminal is at the "L" level, the terminal Q is at the rHJ level. The input burst pulse brings the terminal Q to the "L" level, and the output appearing at the terminal Q of this T-K FF1b and the burst pulse passed through the inverter 1e are ANDed at the gate 1d. The point is shown in Figure 5(d).
A signal like the one shown appears. This signal is also applied to the (-) input terminal of the oP amplifier 3.

As a result, a signal as shown in FIG. 5(e) is obtained at point e of the (-) input terminal of the OP amplifier 3.

By applying the signal shown in FIG. 5(e) to the (-) input terminal of the OP amplifier 3, the OP amplifier 3 amplifies the fluctuation of the hetero gain signal. The comparator 4 compares the signal shown in FIG. 4(f) outputted from this ○P amplifier 3 and appearing at point f at the output end at a certain voltage, and the signal shown in FIG. Output as a pulse as shown in g).

Furthermore, the output of the comparator 4 is integrated by an integrating circuit consisting of a resistor R1 and a capacitor C1, and an integrated voltage as shown in FIG. is applied.

This integrated voltage is sliced at a certain voltage by the OP amplifier 5 to create a pulse train as shown in FIG. 5 (j
) is obtained.

The output signal of this mono multivibrator 6 is sent to the buffer 7
, a discrimination signal is obtained through gate 8.

In this way, the conventional hetero gain signal automatic detection device described above can also distinguish between a standard NTSC signal and a hetero gain signal including jitter.

Problems to be Solved by the Invention However, the conventional automatic heterogain signal detection device described above requires a circuit for extracting burst pulses and a control pulse, resulting in a complicated circuit and high cost.

In addition, for signals containing noise, etc., use the OP method shown in Figure 3.
Amplifier 1. Game) 2. The circuit of the OP amplifier 3 will operate, leading to erroneous determination.

The present invention solves these conventional problems,
The circuit configuration is simple and inexpensive, and the standard NTS
It is an object of the present invention to provide an excellent heterodyne automatic detection device that can accurately detect even a C signal and a hetero gain signal containing noise, etc., without making a mistake in discrimination.

Means for Solving the Problems In order to achieve the above object, the present invention provides a counter that divides a color clock locked to a burst in a video signal and a monochrome clock locked to a horizontal synchronization signal at a predetermined frequency division ratio; A comparator is provided to compare the phase of the output of the counter, and the comparator compares the phase of the output of the counter which is obtained by dividing the color clock and monoclock by the counter. Based on whether the phases match, it is determined whether it is a standard NTSC signal or a hetero gain including jitter. It was designed to do so.

Therefore, according to the invention, by detecting the phase difference between the color clock and the monochrome clock, the standard
This has the effect of automatically detecting whether it is an SC signal or a hetero gain signal, and preventing misjudgment.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, a counter 11 inputs a color clock locked to a burst in a video signal and a monochrome clock locked to a horizontal synchronizing signal, divides the frequency by N, and outputs the result.

12 is a comparator that manually compares the phases of the two clocks output from this counter 11, that is, the N-divided color clock and the monochrome clock; 13 is a comparator that integrates the output of this comparator 12 and converts it into a DC voltage. This is an active filter circuit with resistors 133 to 13d1.
capacitors 13e, 13f,') transistors 13g, 1
It is composed of 3h.

above)・The base of transistor 13g is resistor 13a, 13
The base of the transistor 13h is connected to the output terminal of the comparator 12 via the capacitor 13f, and the base of the transistor 13h is connected to the output terminal of the comparator 12 via the capacitor 13e.
and 13b.

That is, the resistor 13 is connected to the base of the transistor 13g.
The output of the integrating circuit consisting of the resistor 13a and the capacitor 13e is inputted to the base of the transistor 13h.

The emitter of the transistor 13g is connected to - through the resistor 13c.
It is connected to the VCC power supply and to the base of the transistor 13h.

The collector of the transistor 13g is connected to the power supply +Vcc, the emitter of the transistor 13h is grounded, and the collector is connected to the +VCC power supply via the resistor 13 (l).

14 is a reference voltage v1. 15 is a FF that obtains a pulse train from the output of the comparator 14, 16 is a mono multivibrator that shapes the waveform of the output of this FF 15, and 17 is the output of this mono multivibrator 16. This is a gate that manually outputs a discrimination signal with hysteresis.

Next, the operation of the above embodiment will be explained with reference to the waveform diagrams of FIGS. 2 and 3. Figures 2(a) to 2(h)
) shows the waveforms from point a to h in Fig. 1, and Fig. 3 (a) to
The waveform in FIG. 3(d) shows the waveform at points a to d in FIG. 1 when the phases of the color clock and monochrome clock match.

The embodiment shown in FIG. 1 discriminates whether it is a standard NTSC signal or a heterodyne signal containing jitter, and a color clock locked to a burst in the video signal and a monochrome clock locked to a horizontal synchronizing signal are input to a counter 11. , 20 The frequency is divided by N by the counter 11, and a color clock as shown in Fig. 2(a) and a monochrome clock as shown in Fig. 2(b) are obtained at points a and b in Fig. 1. appear.

This polar clock and monoclock are comparator 1.
2, the phase is compared there, and the result of the comparison is outputted at the output terminal 0 point as shown in FIG. 2(c).

The output of this comparator 12 is input to an active filter circuit 13, integrated by an integrating circuit made up of a resistor 13a and a capacitor 13e, and added to the base of a transistor 13h, and then integrated by an integrating circuit made up of a resistor 13b and a capacitor 13f to a transistor 13g. By adding the output of this transistor 13[1+ to the transistor 13h, the transistor 13
At point d of the collector of h, a waveform shown in FIG. 2(d) is obtained.

In this case, when the standard signal is used, the phases of the color clock and monoclock match, so the color clock at point a at the output end of the counter 11 has the waveform shown in FIG. The monoclock signal at point b at the output end has the waveform shown in FIG. 3(b), the waveform at point 0 at the output end of the comparator 12 becomes as shown in FIG. The output appearing at point d is shown in Figure 3 (
cl), it is fixed at a certain voltage.

On the other hand, in the case of a heterodyne signal with time axis fluctuations, the phases of the color clock and monoclock do not match, so
The output of the active filter circuit 13 is already as shown in FIG.
As mentioned in 1), the output changes over time.

The output of this active filter circuit 13 is added to a comparator 14, and the voltage v1.
v2, and as set and reset pulses are applied to the 0 point and f point of the output terminal of the comparator 14, respectively (see Fig. 2).
e), a signal as shown in FIG. 2(f) is extracted.

By adding the output signal of the second comparator 14 to the FF15 as a set and reset pulse, the second FF1
An output converted into a pulse train as shown in FIG. 2(g) is obtained at 9 points at the output end of 5, but when it is a standard signal, the output is fixed at the "H" level or rLJ level.

The output signal of the FF 15 shown in FIG. 2(g) is inputted to the mono multivibrator 16, where it is shaped into a waveform, and the output signal at the output end of the mono multivibrator 16 is outputted at point h as shown in FIG. 2(h). The output of the mono multivibrator 16 is given hysteresis by the gate 17 and output as a discrimination signal.

In this case, when the time of the mono multi-vibrator 16 is increased, an output as shown by the broken line in FIG. 2(h) is outputted from the mono multi-vibrator 16.

In this way, in the above embodiment, by using the basic clock obtained by dividing the frequency of the color clock and the monoclock by N by the counter 11, and by comparing the phases with the comparator 12, it is possible to easily obtain a standard NTSC signal or a hetero gain signal including chic. Not only can the active filter circuit 13 and comparator 14 determine whether the
Stable automatic detection is possible without erroneous determination even for a C signal and a heterodyne signal that contains relatively noise.

Effects of the Invention As is clear from the above embodiment, the present invention divides the color clock locked to the burst in the video signal and the horizontal synchronization signal by dividing the monoclock frequency by N using a counter, and compares the output with a comparator. This system automatically detects whether the signal is a standard NTSC signal or a heterogain signal that includes jitter such as that of a so-called video tape recorder that has time axis fluctuations, and can reliably distinguish between a standard NTSC signal and a heterogain signal. In addition to being able to discriminate, the circuit configuration can be simplified and costs can be reduced.

Further, by using the discrimination signal between the standard NTSC signal and the hetero gain signal, it is possible to automatically operate the time base circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an automatic heterogain detection device according to an embodiment of the present invention, and FIGS. Waveform diagrams of each part, Figure 4 is a circuit diagram of a conventional hetero gain signal automatic detection device, Figures 5 (a) to 5 (j) are
FIG. 3 is a waveform diagram of each part of the automatic hetero gain signal detection device shown in the figure. 11...Counter, 12.14...Comparator,
13... Active filter circuit, 15... Flip/70 tube, 16... Mono multivibrator, 1
7...Gate. Name of agent: Patent attorney Akira Okaji Two idiots and ward 1 2 7 at ω (sha)
Niji +OCJ”Q ω
-a ward)

Claims (1)

[Claims] A counter that divides the color clock locked to the burst in the video signal and the monoclock locked to the horizontal synchronization signal by a predetermined frequency division ratio, and a first step that compares the phases of the color clock and monoclock frequency-divided by this counter. a comparator, an active filter circuit that integrates the output of this comparator and converts it into a DC voltage, a second comparator that compares the output voltage of this active filter circuit with a predetermined level, and an output of this second comparator. An automatic heterodyne signal detection device comprising means for converting into a pulse train and then shaping the waveform to generate a discrimination signal.