JPH02191027A - Plural picture elements simultaneous control system - Google Patents

Abstract

PURPOSE:To control a window in units of a single picture element, and to smoothly execute a scroll operation by individually controlling a picture element read start control signal and a display period control signal at each rising timing. CONSTITUTION:A picture display control circuit 5 issues a read address to a picture memory 1, issues a read clock control enable signal REN (REN) to a read clock generating circuit 2, and issues a display position enable signal DEN (DEN) to a parallel/serial converting circuit 3. Each rising timing of the REN and DEN is individually controlled. At the rising timing of the REN, the read of a picture memory 1 is started, and at the rising timing of the DEN, the read of the picture memory 1 is started. Although a plural picture elements simultaneous control system is adopted in this case, by shifting the instruction of the REN, the picture is displayed in units of a single picture element without using a mask memory.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an image display control method in which multiple pixels are simultaneously read out in one access and these pixels are displayed on a display. The purpose is to ensure smooth movement when performing operations, and when displaying an image on a display, multiple pixels stored in the image memory are simultaneously read out in one access. In an image display control method that displays these pixels on a display by sequentially sending multiple pixels to the display using a parallel/serial conversion circuit, the pixel readout start control signal and display period control signal The configuration is such that image display control is performed pixel by pixel by controlling the timing separately.

[Industrial Application Field] The present invention relates to an image display control method that simultaneously reads out a plurality of pixels in one access and displays these pixels on a display.

In recent years, with the development of image processing control technology, various image devices have been developed, and there is a demand for faster processing. For this reason, a control method for simultaneously displaying a plurality of pixels as described above has been proposed.

[Prior Art] FIG. 8 is a block diagram for implementing a conventional multiple pixel simultaneous display control system. In this FIG. 8, 1 is an image memory that stores image data, and 2 is a readout clock generation circuit. The read clock generation circuit 2 receives the read period information from the image display control circuit 5' and outputs the image memory 1.
and a read clock to the parallel/serial conversion circuit 3.

3 is a parallel/serial conversion circuit that converts n-pixel parallel data from image memory 1 into serial data;
is a display that receives serial data from the parallel/serial conversion circuit 3 and displays an image made up of a plurality of pixels.

5' is an image display control circuit;
receives a display start address, an image memory read start address, an image memory read end address (or a display end address), outputs a read address to the image memory 1, and outputs read period information to the read clock generation circuit 2. be.

With this configuration, when displaying the pixels in the image memory 1 on the display 4, the timing of the read clock is adjusted by giving the read period information of the image memory 1 from the image display control circuit 5' to the read clock generation circuit 2. The data is read out as parallel data for each n pixel as it is, and this parallel data is converted into serial data by the parallel/serial conversion circuit 3 and sent to the display 4, so that n pixels are simultaneously displayed on the display 4. Is displayed.

[Problems to be Solved by the Invention] However, in such a conventional multi-pixel simultaneous display control method, a boundary (boundary) of every n pixels is created in the displayed image.
This results in a window (
Furthermore, when a scroll operation is performed, the movement is not smooth.

Therefore, as shown in FIG. 9, using the mask memory 6, the AND gate 7 calculates the AND of the image data read out from the image memory 1 and the required mask data.
Although it is conceivable to control the window pixel by pixel, even if such means are used, there is still a problem in that the problem with scrolling operations cannot be solved. In FIG. 9, the same reference numerals as in FIG. 8 indicate substantially the same parts.

The present invention was created in view of these problems, and provides a multi-pixel simultaneous display control method that allows windows to be controlled on a pixel-by-pixel basis and allows for smooth movement when scrolling. is intended to provide.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In this FIG. 1, 1 is an image memory that stores image data, and 2 is a read clock generation circuit, which receives a pixel read start control signal from an image display control circuit 5 and stores it in the image memory. 1 and parallel/
It supplies a read clock to the serial conversion circuit 3.

3 is a parallel/serial conversion circuit that converts n-pixel parallel data from image memory 1 into serial data;
is a display that receives serial data from the parallel/serial conversion circuit 3 and displays an image made up of a plurality of pixels.

5 is an image display control circuit, and this image display control circuit 5 is
Upon receiving the display display start address, image memory readout start address, and display display end address, outputs a readout address to the image memory 1, outputs a pixel readout start control signal to the readout clock generation circuit 2, and further outputs a pixel readout start control signal to the parallel/serial conversion circuit. It outputs a display period control signal to 3.

Here, the rise timings of the pixel readout start control signal and the display period control signal are controlled separately, so that image display control can be performed pixel by pixel.

[Function] With this configuration, when displaying the pixels in the image memory 1 on the display 4, the image display control circuit 5 gives a read address to the image memory 1, and the pixel to the read clock generation circuit 2. giving a read start control signal;
A display period control signal is given to the parallel/serial conversion circuit 3. As a result, the serial data converted by the parallel/serial conversion circuit 3 is sent to the display 4,
displayed on this display 4. In this case, since the rise timings of the pixel readout start control signal and the display period control signal are controlled separately, image display control can be performed pixel by pixel.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, 1 is an image memory, 2 is a read clock generation circuit (read clock timing generation circuit), 3 is a parallel/serial conversion circuit, and 4 is a display, but since these are almost the same as those explained in the conventional example, detailed explanation thereof will be omitted.

By the way, 5 is an image display control circuit, and this image display control circuit 5 receives a display display start address, an image memory read start address, and a display display end address, outputs a read address to the image memory 1, and also generates a read clock. A read clock control enable signal REN as a pixel read start control signal is output to the circuit 2, and a display position control enable signal DEN as a display period control signal is output to the parallel/serial conversion circuit 3. , read clock control enable generation circuit 89 display position control enable generation circuit 9
．． It is configured with a read/display address counter 10.

Here, the read clock control enable generation circuit 8 is
It outputs a read clock control enable signal REN to the read clock generation circuit 2. Therefore, the read clock control enable generation circuit 8, as shown in FIG. Selector section 82.
It is configured with a data mask section 83.

The read start data creation section 81 receives information on the lower two bits Dst of the display display start address and the lower two bits Rst of the image memory read start address and creates data at the read start. In other words, in the case of 4-pixel time control, the readout start timing is determined by the combination of the lower 2 bits Dst of the display display start address and the lower 2 bits Rst of the image memory readout start address, as shown in FIG. However, in this case, as shown in FIGS. 5 and 6, in relation to the rise timing of the display position control enable signal DEN, the boundary including the display start position and its first
Since the timing can be expressed by the data with the previous boundary, this reading start data creation unit 81
In this case, data for two boundaries is created.

The selector unit 82 includes a first half data sector 82A that selects the first half data using the timing of the boundary before the display start reference, and a second half data sector 82A that selects the second half data using the boundary timing of the display start reference. 82B, each selector 82A, 82
B outputs the data of each created boundary at the timing of each boundary, and outputs an all H (high) read enable state signal at other times.

The data mask section 83 outputs the data from the selector section 82 during the display period of the 4-pixel boundary and the boundary immediately before that, and its output is sent to the read clock generation circuit 2 as the read clock control enable signal REN. Output.

Further, the display position control enable generation circuit 9 includes a selector section 91 and a data mask section 92, as shown in FIG.

Here, the selector section 91 includes a display start time data creation section 91A that receives the lower two bits Dst of the display display start address and creates display start data at the timing of the boundary of the display start reference; The display end data creation unit 91B receives bits D and end and creates data at the end of display at the timing of the boundary of the display end reference. At the end of the display, the data created by the display start data creation section 91A and the display end data creation section 91B are output, and at other times, an all H (high) display enable state signal is output.

The data mask section 92 outputs the data from the selector section 91 during a display period on a four-pixel boundary, and its output is output to the parallel/serial conversion circuit 3 as a display position control enable signal DEN.

Here, the rise timings of the read clock control enable signal REN and the display position control enable signal DEN are controlled separately, and these signals REN.

The relationship of DEN is shown in FIGS. 5 to 7, taking the case of simultaneous control of four pixels as an example. In these figures, reading from the image memory 1 is started at the rising edge of the read clock control enable signal REN, and displaying is started at the rising edge of the display position control enable signal DEN. Further, the end of the display is performed by similar control using the lower two bits D end of the display end address. Thereby, image display control can be performed on a pixel-by-pixel basis.

Note that the read/display address counter 10 is an address counter for the image memory 1 and the display 4.

With the above-described configuration, when displaying pixels in the image memory 1 on the display 4, the image display control circuit 5
A read address is given to the image memory 1, and a read clock control enable signal R is given to the read clock generation circuit 2.
EN and a display position control enable signal DEN to the parallel/serial conversion circuit 3. As a result, the serial data converted by the parallel/serial conversion circuit 3 is sent to the display 4 and displayed on the display 4. In this case, since the rise timings of the read clock control enable signal REN and the display position control enable signal DEN are controlled separately, the image display can be controlled pixel by pixel.

That is, as shown in FIGS. 5 and 6, reading from the image memory 1 is started at the rising edge of the read clock control enable signal REN, and displaying is started at the rising edge of the display position control enable signal DEN.

Furthermore, the display is terminated by similar control using the lower two bits Dend of the display end address, as shown in FIG.

Even with this method of controlling multiple pixels simultaneously, by shifting the readout timing of the image memory 1 for display according to the instruction of the readout clock control enable signal REN, it is possible to control each pixel in units of pixels without using a mask memory. Not only can it be displayed, but it can also be scrolled smoothly.

In addition, by making the display end dependent only on the display display end address, even when enlarging or reducing an image, the control is applied only to the specified image display range. can do.

[Effects of the Invention] As detailed above, according to the multiple pixel simultaneous display control method of the present invention, the rise timings of the pixel readout start control signal and the display period control signal are controlled separately, so that Image display control can be performed pixel by pixel, which has the advantage that the window can be controlled pixel by pixel, and the scroll operation can be performed smoothly.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a block diagram of a read clock control enable generation circuit, Fig. 4 is a block diagram of a display position control enable generation circuit, FIGS. 5 to 7 are time charts for explaining the operation of an embodiment of the present invention, FIG. 8 is a block diagram showing a conventional example, and FIG. 9 is a block diagram of another example. FIG. 2 is a block diagram showing a conventional example. In the figure, 1 is an image memory, 2 is a readout clock generation circuit, 3 is a parallel/serial conversion circuit, 4 is a display, 5 is an image display control circuit, 8 is a readout clock control enable generation circuit, and 9 is a display position control enable generation circuit. circuit. 10 is a read/display address counter, 81 is a data creation section at the start of reading, 82 is a selector section, 82A, 82B are selectors, 83 is a data mask section, 91 is a selector section, 91A is a data creation section at the start of display, 91B is a data creation section at the start of display. 92 is a data masking section.

Claims (1)

[Claims] When displaying an image on the display (4), a plurality of pixels stored in the image memory (1) are simultaneously read out in one access, and the plurality of read pixels are processed in parallel/serial mode. In an image display control method in which these pixels are displayed on the display (4) by sequentially sending them to the display (4) in the conversion circuit (3), the pixels output from the image display control circuit (5) are Image memory (
The pixel readout start control signal that controls the pixel readout start timing from 1) and the display period control signal that controls the period during which an image is displayed on the display (4) are each controlled separately in their start-up timings. , a multi-pixel simultaneous display control method characterized by performing image display control on a pixel-by-pixel basis.