JPH0219661B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding device using a voice packet decoding method. In recent years, systems have been proposed in which audio is digitized using the PCM method, etc., and further converted into packets, which are transmitted and received via a packet switching device.

When transmitting voice as packets, it is common to transmit only the voiced voice as packets in order to increase transmission efficiency or reduce the processing amount of the packet switching system. In this case, it is necessary to notify the receiving side of the presence or absence of a silent portion, its length, etc. One way to do this is on the transmitting side, when it receives audio, it converts it into an audio data block at predetermined intervals, regardless of whether it is voiced or silent. At the same time, a serial number is sequentially assigned to each audio data block. Next, it is determined whether each audio data block is active or silent, and only audio data blocks are sent out as audio packets. On the other hand, on the receiving side, there is a method of demodulating and reproducing the voice packets to which the serial numbers have been assigned in that order, and automatically generating silence for voice packets corresponding to missing numbers. 21610. Furthermore, as is well known, in a packet switching device, there is a delay before a packet sent from the transmitting side reaches the receiving side, and furthermore, this time is not constant.
However, in voice transmission, fluctuations in delay time not only cause deterioration of the voice, but also make conversation impossible in extreme cases, so it is necessary to absorb fluctuations in delay time when decoding voice packets. Needed.

Conventionally, in order to decode the voice packets described above, a voiced voice data block (hereinafter referred to as voice packet) to which a serial number has been assigned is stored in a memory provided inside the voice packet decoding device; An audio packet having a serial number that is the same as the time period at which the original audio is blocked on the audio packet transmitting side provided and a value indicated by a reading counter that increments at the same time period is searched from the memory, and the audio packet is sent to a decoder. If the audio packet is not in the memory, the audio packet is decoded by transferring silence data to a decoder. However, this method requires complicated processing to search the memory, and has the disadvantage that it is difficult to configure a decoding device with simple hardware and requires a processing device such as a microprocessor.

The purpose of the present invention is to eliminate the above-mentioned drawbacks by receiving silent section information, a write control signal, and active voice data when decoding a voice packet, updating the write address with the silent section information, and then reading the packet. To provide a high-quality and economical voice packet decoding method characterized in that addressing of an address and a write address can be configured using only an address counter, and the update of a read address is controlled by detecting a match between a read address and a write address. There is a particular thing. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a decoding apparatus according to the audio packet decoding method of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a decoding device according to the audio packet decoding method of the present invention. In the figure, VD is voice data, DIF is silent section information, WP is a write control signal, CTL is a control circuit, and M
is the memory, WG is the write gate, WAC is the write address counter, RAC is the read address counter, TIM is the timer circuit, CLK is the clock supply circuit, DET is the detection circuit, BUF is the buffer circuit,
DEC is the decoder, VF is the original audio signal, OR is the OR circuit, 24 is the AND circuit, 11 is the data line, 12 is the memory M write/read control signal, 13 is the output line, 14 is the output of the write address counter WAC 15 is the read address signal which is the output of the read address counter RAC, 16 is the memory write address counter WAC
17 is a control signal for controlling the update of the write address counter WAC based on the silent interval information DIF, 19 is an activation signal for a timer circuit TIM that measures a certain period of time, and 20 is an activation signal 19 for the timer circuit TIM. 21 is a detection circuit that outputs a read address update prohibition signal for a certain period of time after receiving
An address match signal that DET outputs when the read address signal 15 and the write address signal 14 match; 22 is a control signal that controls the write gate to write audio data corresponding to silence after reading the memory M; 23 25 is a negative output signal of the OR circuit OR, and 25 is a step clock signal.

First, in explaining the operation shown in FIG. 1, the relationship between the silent section information DIF and the write control signal WP in the audio packet received by the packet receiving device will be explained using FIG. FIG. 2a shows a pulse sequence diagram of a voice packet arriving at a packet receiving device, FIG. 2b shows silent interval information, and FIG. 2c shows a write control signal. In FIG. 1A, the shaded areas indicate voice packets, and the non-shaded areas are silent voice blocks, which are not sent from the calling side but are shown for the sake of explanation. A serial number is given to each voice packet by modulo 8, and the packets . . . arrive at the packet receiving device as voice packets.
The packet receiving device creates silent interval information DIF as shown in FIG. Audio data VD of audio packet, silent section information DIF,
The write control signal WP is sent to a decoding device based on the audio packet decoding method of the present invention.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. Voice data VD with sound from the packet receiving device
, the silent section information DIF and the write control signal WP are received. The voiced voice data VD is written to the memory via the write gate WG and the data line 11 to store the voice data. Silent section information DIF,
The write control signal WP is supplied to a control circuit CTL of a decoding device using the voice packet decoding method. When the control circuit CTL receives non-zero silent interval information DIF from the packet receiver, it updates the value of the write address counter WAC through the control signal 17 in accordance with the silent interval information DIF. After that, the control circuit
The CTL writes the audio data VD to the address designated by the write address 14 of the memory M via the write gate WG in response to the write control signal WP. When the write is completed, the write address counter WAC is incremented by 1 by the increment control signal 16.
The control circuit CTL sequentially stores the received audio data in the memory M as described above, and updates the write address counter WAC sequentially. In this case, the memory M has an area for storing a plurality of predetermined audio packets. Next, reading from memory M will be explained. The control circuit CTL receives a clock signal from the clock supply circuit CLK, and at a predetermined reading time, instructs reading by a write/read control signal 12, and the memory M outputs the audio data at the position specified by the reading address 15 to an output line. 13, the read audio data is sent to the decoder DEC via the buffer circuit BUF,
It demodulates to the original voice signal VF and sends it to a telephone (not shown). At the time when the read operation of the memory M ends, the read address counter RAC receives an increment clock signal from the clock supply circuit CLK via the AND circuit 25 and increments by one.
(When there is no output from the OR circuit OR) As described above, audio packets are sequentially written to the memory M, read out, and demodulated. However, as mentioned above, there is a delay in the packet switching network, and this delay is the allowable value. If this value is exceeded, the interaction between the interlocutors becomes unnatural. Experience has shown that the allowable delay time is several 100 ms. Furthermore, since the delay varies depending on the processing waiting time of the packet switching device, etc., if the arriving voice packet is immediately transferred to the decoder DEC, silence must be inserted when the next voice packet is delayed. To solve this problem, the received audio packets are delayed by, for example, 100 ms within the above-mentioned allowable delay time and then sent to the decoder DEC.
There is a known method of transferring the data to The timer circuit TIM is for realizing the delay,
When the control circuit CTL receives the write control signal WP, if the detection circuit DET, which is a feature of the present invention, is sending out the address match signal 21, it sends the activation signal 19 to the timer circuit TIM, and detects the corresponding signal. The timer circuit TIM transfers the read address update prohibition signal 20 for a predetermined period of time (corresponding to the delay described above) to the AND circuit 25 via the OR circuit OR, and transfers the increment clock signal 2 from the clock supply circuit CLK.
6, the update of the read address counter RAC is stopped for a certain period of time. The address match signal 21 is the read address 15 of the memory M.
This is sent when the write address 14 and the write address 14 match, but the two addresses match when the value of the read address counter RAC catches up with the value of the write address counter WAC, or vice versa. The former occurs at the start of a conversation or when a relatively long period of silence (longer than all the data in memory M is read) continues, and the received voice packet is transferred to the decoder DEC by the action of the timer circuit TIM. can be delayed for a certain period of time. The latter occurs when the number of received voice packets exceeds the storage area of the memory M, and in this case it is advantageous to discard old data in order to maintain the naturalness of the conversation. When the detection circuit DET detects an address match between the read address 15 and the write address 14, the address match signal 21 is maintained until the next active audio packet is received, and the timer circuit TIM continues to hold the read address until a certain period of time has elapsed. The counter RAC is not updated, and the audio data VD that has arrived during that time is sequentially written into the memory M, and old data is discarded. The memory M
If there is a silent section when writing to , the silent section information DIF
Accordingly, the write address counter WAC is updated, so the contents of the address part of the memory M corresponding to the silent period are not rewritten and old data remains, but such a situation is extremely rare. There is no problem in practical use. Alternatively, the address matching signal 21 may be used to rewrite the entire contents of the memory M to a silent state.

The decoder DEC plays silence while inhibiting the update of the read address counter RAC. To achieve this, the decoder DEC must have the same
It is sufficient to continuously transfer the PCM code, and in the embodiment shown in the figure, when the buffer circuit BUF is receiving the negative output signal 23 of the OR circuit OR, the output is kept at a constant value, for example, all 1, so that the decoder
Silent audio data will be transferred to DEC. Furthermore, if the memory M is configured such that one word corresponds to one audio sample (for example, one octet), silent data can be equivalently transferred to the decoder DEC simply by continuously reading the same address. . Another thing to keep in mind here is, for example, if the silent state continues for a long time and the read address 1
5 catches up with the write address 14, the voice packet that arrives again is always accompanied by a silent section. In this case, silent section information DIF
When you update the write address counter WAC with
Depending on the length of the silent section, the write address 1
4 may catch up with read address 15. To avoid this, it is preferable that the control circuit CTL does not update the write address counter WAC even if the silent section information DIF is received while the address match signal 21 is present.

In the above explanation, a case has been described in which the transmitting side assigns a serial number to the audio packet, but according to the present invention, the write address is updated using the silent interval information included between the audio packets, so the transmitting side assigns a serial number to the audio packet. Count the number of silent audio data blocks between the sent out audio data block and the currently sent out audio data block, add it to the current audio data block as silent section information, and send it out. This method can also be adopted in a packet switching device in which the order of packets sent from the same terminal is not reversed, so there is a degree of freedom in selecting the method. Further, as described in detail in the explanation of the operation of the embodiment, read and write addressing can be configured using only an address counter, and furthermore, a detection circuit detects coincidence between a read address and a write address and controls updating of the read address counter. Since the required slip phenomenon can be generated by using this method, it is possible to provide a high-quality, economical voice packet decoding method with an extremely simple configuration, and it can be used in complex communication systems that process both voice communication and data communication. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an explanatory diagram showing the relationship between silent interval information of a voice packet and a write control signal, in which figure a is a pulse sequence diagram of a voice packet, figure b is silent interval information, and figure c is a write control signal. WG...Write gate, CTL...Control circuit, TIM
…Timer circuit, M…Memory, WAC…Write address counter, RAC…Read address counter,
DET...detection circuit, OR...OR circuit, CLK...clock supply circuit, BUF...buffer circuit, DEC...decoder, VD...audio data, DIF...silent section information,
WP...Write control signal, 25...AND circuit.

Claims (1)

[Claims] 1. When decoding an audio packet, receiving silent interval information, a write control signal, and audio data, and specifying a write address to storage means for the audio data and storage means for the audio data. write address designation means for specifying a read address; and detection means for designating writing and reading by the read address designation means for designating a read address, and detecting that the write address designation means and the read address designation means designate the same address; clocking means for measuring a predetermined time from the time when the write control signal is received when there is an output signal of the detection means; write address updating means for updating a write address based on the silent interval information; and within the predetermined time. stops the address update by the read address update prohibiting means for prohibiting the update of the read address, reads the audio data in the storage means according to the address specified by the read address designation means, and then writes silent data to the address. 1. An audio packet decoding method comprising: a silent data writing means for detecting a same address; and a means for generating silence when there is an output from a same address detecting means or a clocking means for counting a certain period of time. 2. The audio packet decoding method according to claim 1, wherein the write address is not updated even if silent section information is received while a certain period of time is being counted.