JPS6253092B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an audio packet decoding method that can easily reproduce high-quality audio.

In recent years, systems have been proposed in which audio is digitized using the PCM method, etc., and further converted into packets, which are transmitted and received via a packet switching device. When audio is transmitted in the form of packets, it is common to use a method in which only voiced sounds are transmitted as packets in order to increase transmission efficiency or reduce the amount of processing required by the packet switching system. In this case, it is necessary for the sending side to notify the receiving side of the presence or absence of a silent section, its length, etc., but in the conventional method, the sending side first forms the audio into audio blocks at predetermined intervals, regardless of whether or not there is sound. At the same time, a serial number is sequentially assigned to each audio block, and then it is determined whether each audio data block has sound or no sound, and only those with sound are sent out as audio packets.On the other hand, on the receiving side, the serial numbers assigned with the serial numbers are A method was used in which audio packets were demodulated and reproduced in that order, and silence was generated for packets corresponding to missing numbers. In this method, a buffer memory is provided on the receiving side, and means is provided to search for a packet with a specific serial number among the packets stored in the buffer memory.
This requires a control device with sophisticated logical judgment functions, such as means for searching for packets corresponding to missing numbers among the serial numbers, and this type of function usually cannot be realized with simple hardware alone.

The present invention has been made in view of the above-mentioned drawbacks, and includes means for receiving silent interval information, active voice data, and a write control signal from a packet receiving device, and storing the silent interval information and voice data. means for specifying a write address to the storage means, means for specifying a read address from the storage means, means for generating silence according to silence interval information from the storage means, and the write address designation means. means for detecting that the reading address specifying means specifies the same address; means for controlling such that silence is generated when there is an output from the detecting means; and silent interval information received when there is an output from the detecting means. By converting to a constant value and creating new silent interval information, the above-mentioned drawbacks are eliminated, and economical audio is easy to design and adjust without requiring software to realize advanced logical judgment functions. It provides a packet decoding method. The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a decoding device according to the audio packet decoding method of the present invention. In the figure, VD is active audio data, DIF is silent interval information, WP is a write control signal, CTL is a control circuit, M is a memory, WG is a write gate, WAC is a write address counter, RAC is a read address counter, D is the identification circuit, CLK is the clock circuit, DET is the detection circuit, BUF is the buffer circuit,
DEC is the decoder, VF is the original audio signal, OR is the OR circuit, 10 is the AND circuit, 11 is the data line, 12 is the data line, 13 is the write address counter WAC
14 is the read address signal that is the output of the read address counter RAC, 15 is the output line, 16 is the output line, 17 is the control line, 18 is the increment clock signal, 19 is the OR circuit OR 20 is a write/read control signal for audio data in the memory M, 21 is a write/read control signal for silent section information in the memory M, and 22 is a control signal for the write gate WG to convert the silent section information into a constant value. 23 is a step control signal for the write address counter WAC of memory M, 2
4 is a read address update prohibition signal based on the silent interval information output from the identification circuit D, and 25 is an address match signal output by the detection circuit DET when the write address signal 13 and the read address signal 14 match.

In explaining the operation of FIG. 1, the relationship between the silent interval information DIF and the write control signal WP in the audio packet received by the packet receiving device will be explained using FIG. FIG. 2a shows a pulse sequence diagram of a voice packet arriving at a packet receiving device, FIG. 2b shows silent interval information, and FIG. 2c shows a write control signal. In FIG. 2a, the hatched area indicates a voice data packet with sound, and the unshaded area is a silent voice data block which is not sent from the calling side, but is shown for the sake of explanation. Each packet is assigned a serial number using modulo 8, and the packet a in FIG. 2 arrives at the packet receiving device as a voice packet. The packet receiving device creates silent interval information DIF as shown in FIG. 2b based on the serial number of the audio packet, and also generates a write control signal as shown in FIG. 2c in response to the audio packet.
Create a WP and create the audio data VD of the audio packet,
The silent section information DIF and the write control signal WP are sent to the audio packet decoding device according to the method of the present invention. The example in Figure 2 shows a case where the calling side assigns a serial number to the audio data block and only the voice blocks with sound are sent out as audio packets, but in the case of a method in which the calling side adds silent interval information DIF to the audio packet. In this case, the packet receiving device receives the silent period information.
DIF can be used as is.

Next, the operation of the embodiment shown in FIG. 1 will be described. This audio packet decoding device receives silent section information DIF, audio data VD, and write control signal WP sent from the packet receiving device. The silent section information DIF is written into the memory M using the address counter.
The silent section information is written to the address specified by WAC using the write/read control signal 21, and the audio data VD is written to the address of the memory M using the audio data write/read control signal 20. After the writing of the audio data VD is completed, the address counter WAC is incremented by +1 using the increment control signal 23. The above operation is started when the write control signal WP is supplied to the control circuit CTL, and each time the write control signal WP arrives, the silent section information is
DIF and audio data VD are sequentially stored in memory M, and write address counter WAC is sequentially updated. The memory M has an area for storing a plurality of predetermined pieces of silent section information and an area for storing audio data of a plurality of predetermined audio packets. Therefore, there are two types of information in memory M, one type is silent section information.
DIF, and the other type is audio data VD.
Both the address where the silent interval information DIF is stored and the address where the audio data VD is stored are specified by the write address counter WAC. The silent interval information DIF and the audio data VD may be stored in the memory M by any memory addressing, but as an example, the following is the method. It is assumed that there are eight areas each for storing blocks of silent interval information DIF and audio data VD, and one audio block occupies 64 addresses. In the above case, the total number of counter addresses is 64×8= ²⁹ , and if it is configured with a binary counter, it becomes a 9-bit counter. The entire output of the binary counter is audio data VD.
The upper 3 bits of the binary counter specify the memory address for silent interval information DIF. In the memory M, the areas for storing the silent section information DIF and the audio data VD are independent from each other.

Next, reading the audio data VD from the memory M will be explained. Control circuit CTL is a clock circuit
When the clock signal CLK is received and a predetermined reading time comes, the audio data write/read control signal 20 instructs reading, and the memory M outputs the audio data at the address specified by the read address signal 14 to the output line 16. The output audio data is sent to the decoder DEC via the buffer circuit BUF, where it is demodulated into the original audio signal VF and sent to a telephone (not shown). At the time when the audio data read operation from memory M ends, the read address counter RAC is input from clock circuit CLK to AND circuit 1.
Clock signal 1 for increment sent via 0
Receive 8 and advance by +1. When there is no output from the silent section identification circuit D or detection circuit DET, the audio data written in the memory M as described above is
Sequentially reads the VD and demodulates the voice data with sound.

Next, reading the silent interval information DIF from the memory M will be explained. The silent interval information DIF is read before the audio block is read, thereby generating silence. This is because generation of silence is essential for demodulating the original audio signal VF.
The control circuit CTL is supplied with the clock signal of the clock circuit CLK and the signal of the control line 17, and when a predetermined reading time of the silent section information comes, it instructs the reading of the silent section information by the writing/reading control signal 21.
The silent interval information DIF of the address designated by the read address signal 14 in the memory M is outputted to the output line 15, and the silent interval information DIF is sent to the identification circuit D. In response to this, the discrimination circuit D outputs silent section information.
A read address update prohibition signal 24 is output for a time corresponding to the value of DIF. That is, the output time is set as follows: [Output of the silent section identification circuit]=T×DIF. T is a silent interval time corresponding to a unit block of audio. Output 2 of identification circuit D
4 is supplied to the negative input of the AND circuit 10 and the buffer circuit BUF via the OR circuit OR, and prohibits the incrementing clock signal 18 of the read address counter RAC from being supplied to the counter RAC, and also to the buffer circuit BUF. Since it instructs to generate silence, the read silence interval information DIF
In response, silence is generated and sent to a telephone (not shown). As explained above, the silent interval information DIF and the audio data VD are sequentially written into the memory M, and the silent interval information DIF and the audio data VD are sequentially read from the memory M, and silence is generated based on the silent interval information DIF. The original voice signal VF is decoded by demodulating the voiced signal using VD.

Next, the time interval of the packets arriving at the packet receiving device changes, so the silent period information DIF and audio data supplied to the audio packet decoding device vary.
A case where the time intervals of VD and write control signal WP are not constant will be explained. Generally, in a packet switching device, there is a delay before a packet sent from a sender reaches a receiver, and the delay is not constant depending on the packet. However, in the transmission of voice packets, variations in delay not only cause deterioration of voice, but also may make communication impossible in extreme cases. For example, if you immediately transfer the audio data VD written to the memory M to the decoder DEC, if the next audio data VD arrives later, the audio will not be able to be decoded (no silence will be inserted). It is also clear that it causes inconvenience (unavoidable). Therefore, when decoding to the original audio, it is essential to absorb the variation in delay time on the decoding side. Fluctuations in packet delay are generally absorbed as follows. That is, a method may be adopted in which the voice data is deliberately delayed by remaining in the memory M for a permissible time such as 100 msec so that the conversation between the parties does not become unnatural, and then transferred to the decoder DEC. In order to realize the delay, a detection circuit DET and a write gate WG are provided and function as follows. The detection circuit DET detects whether the write address counter WAC and the read address counter RAC match, and when they match, an address match signal 25 is obtained. Address match signal 2
5 is supplied to the OR circuit OR and is also a control circuit.
Also supplied to CTL. Now, if silence continues for a relatively long time (more than the extent to which all the audio data in memory M is read out), initially the silence section information DIF
is read to generate silence as described above, and then the audio data VD is read to decode the active audio, but after that, no signal is sent from the packet receiver to the audio packet decoder, and the write address counter is
Since WAC remains stopped, read address counter RAC catches up with write address counter WAC and becomes the same address. Here the detection circuit
DET detects the match between both counters and outputs an OR circuit.
Therefore, the gate of the AND circuit 10 is closed, the read address counter RAC is prohibited from incrementing, and the buffer circuit BUF is instructed to generate silence. In the above state, a new audio packet is received by the packet receiving device, and the audio packet decoding device receives the silent interval information DIF, audio data VD, and write control signal.
When the WP is sent, the silent section information DIF at this time has already generated silence on the decoding device side, so there is no need to use the silent section information DIF as is to generate silence. In this case, by supplying the address match signal 25 of the detection circuit DET to the control circuit CTL, the control circuit CTL outputs the control signal 22 and the write gate WG blocks the silent interval information DIF. Therefore, the silent section information DIF is converted into a constant value and written into the memory M. Here, the constant value means that the silent interval information DIF is
This value is such that the read address update prohibition signal 24 is output for about 100 msec when the read address update prohibition signal 24 is supplied to the read address update inhibit signal 24. The silent interval information DIF written in the memory M is immediately sent to the identification circuit D (since the memory M is empty), which prohibits the read address counter RAC from incrementing for a certain period of time and generates silence in the buffer circuit BUF. Instruct the audio data VD to the decoder DEC
Transfer can be delayed for a certain period of time.
Therefore, even if the arrival of a packet is delayed, there is no need to insert silence, and fluctuations in packet delay can be absorbed.

In addition to the above-mentioned conditions, the write address counter WAC and the read address counter RAC match when the write address counter WAC catches up with the read address counter RAC. This occurs when the number of received voice packets exceeds the storage area of the memory M, and in this case it is advantageous to discard old data in order to maintain the naturalness of the conversation. When the detection circuit DET detects an address match, the address match signal 25 is held until the next active packet is received, and the read address counter RAC
is not updated and the buffer circuit BUT produces silence. At this time, when a voice packet arrives, the silent section information DIF is converted to a constant value as described above and written to the memory M, and the voice data VD
is successively written to memory M, old audio data VD
has been discarded in memory M.

Therefore, according to the embodiment, the original audio signal can be decoded by generating silence using the silence interval information included between audio packets, and the audio packets can be decoded with sufficient absorption capacity even when the delay of audio packets varies. A decoding device is obtained.

Also, while updating of the read address counter RAC is prohibited, it is necessary to instruct the buffer circuit BUF to send silent data to the decoder DEC. If configured so that it is compatible with can be simplified.

As explained above, according to the system of the present invention, silence can be generated on the decoding device side using the silence section information included between audio packets. Therefore, the originating side does not need to assign serial numbers to audio packets, but instead it is sufficient to provide silent section information. It is adaptable and provides flexibility in selecting the method for the entire packet switching system. To implement the method of the present invention, an extremely simple hardware configuration is required in which the addressing mechanism consists of only a counter, and a detection circuit matches the write address and read address, and generates silence according to the value of the silence interval information. An economical voice packet decoding device with excellent quality can be obtained, and can be applied to complex communication systems that process voice communication and data communication together.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an explanatory diagram showing the relationship between the silent section information of the audio packet and the write control signal, where a is a pulse sequence diagram of the audio packet, b is the silent section information, and c is the write control signal. WG...Write gate, CTL...Control circuit, M
...Memory, WAC...Write address counter, RAC...Read address counter, DET...
...Detection circuit, 10...AND circuit, OR...OR circuit, CLK...clock circuit, D...discrimination circuit, BUF...buffer circuit, DEC...decoder,
VD...Sound data, DIF...Silent section information, WP...Write control signal, VF...Original audio signal.

Claims (1)

[Claims] 1. In an audio packet decoding method that receives silent interval information, audio data, and a write control signal when decoding an audio packet, and decodes the original audio signal, the silent interval information and audio data are stored. means for specifying a write address to the storage means, means for specifying a read address from the storage means, means for generating silence in accordance with silence interval information from the storage means, and means for detecting that the addressing means and the read addressing means designate the same address; means for controlling to generate silence when there is an output from the detecting means; and silence to receive when there is an output from the detecting means. An audio packet decoding method characterized by having means for converting section information into a constant value to obtain new silent section information. 2. The audio packet decoding system according to claim 1, wherein one audio sample is stored at one address of the storage means designated by the write address designation means.