JPH02197162A - Resistor - Google Patents
ResistorInfo
- Publication number
- JPH02197162A JPH02197162A JP1895889A JP1895889A JPH02197162A JP H02197162 A JPH02197162 A JP H02197162A JP 1895889 A JP1895889 A JP 1895889A JP 1895889 A JP1895889 A JP 1895889A JP H02197162 A JPH02197162 A JP H02197162A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion region
- semiconductor substrate
- resistor
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000003287 optical effect Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体基板上に形成される抵抗器に関するも
のであり、例えばモノリシックIC上に形成される抵抗
器として適するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a resistor formed on a semiconductor substrate, and is suitable as a resistor formed on a monolithic IC, for example.
[従来の技術]
従来、抵抗器の抵抗値は、固定式、半固定式、及び印加
電圧により連続的に変化するものがあった。固定式の抵
抗器としてはソリッド抵抗や、半導体集積回路中の拡散
抵抗などがあり、また、半固定式の抵抗器としては、機
械的なスライダーを有する可変抵抗器があり、印加電圧
により連続的に変化するものとしては、バリスタがある
。[Prior Art] Conventionally, the resistance value of a resistor has been of a fixed type, a semi-fixed type, and one that changes continuously depending on an applied voltage. Fixed resistors include solid resistors and diffused resistors in semiconductor integrated circuits, while semi-fixed resistors include variable resistors with a mechanical slider that can be adjusted continuously depending on the applied voltage. An example of something that changes is the barista.
[発明が解決しようとする課題]
ところで、印加電圧により抵抗値が段階的に変化するよ
うな抵抗器があれば、簡単な構成で入力信号のレベルを
弁別することが可能となり、好都合であると考えられる
。[Problems to be Solved by the Invention] By the way, if there were a resistor whose resistance value changed stepwise depending on the applied voltage, it would be possible to discriminate the level of an input signal with a simple configuration, which would be advantageous. Conceivable.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、印加電圧により抵抗値が段階的
に変化するような抵抗器を提供することにある。The present invention has been made in view of these points, and an object of the present invention is to provide a resistor whose resistance value changes stepwise depending on the applied voltage.
〔課題を解決するための手段]
本発明にあっては、上記の課題を解決するために、第2
図及び第3図に示すように、低不純物濃度の半導体基板
44に導電型の異なる不純物を拡散させた拡散領域40
を形成し、半導体基板44と拡散領域40の間に生じる
PN接合が逆バイアスされるように半導体基板44の電
位を設定し、拡散領域40と半導体基板44の間に生じ
る空乏層を拡げるような電位を印加されたアルミニウム
膜4つを拡散領域40を覆うように配して成る抵抗器に
おいて、第1図に示すように、拡散領域40は少なくと
も2種類の間隔で蛇行するように形成され、前記2種類
の間隔は、拡散領域40と半導体基板44の間に生じる
空乏層が印加電圧の増加につれて段階的につながるよう
な間隔に設定されていることを特徴とするものである。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a second method for solving the problems.
As shown in the figure and FIG. 3, a diffusion region 40 in which impurities of different conductivity types are diffused into a semiconductor substrate 44 with a low impurity concentration.
The potential of the semiconductor substrate 44 is set so that the PN junction formed between the semiconductor substrate 44 and the diffusion region 40 is reverse biased, and the depletion layer formed between the diffusion region 40 and the semiconductor substrate 44 is expanded. In a resistor in which four aluminum films to which a potential is applied are arranged to cover a diffusion region 40, the diffusion region 40 is formed in a meandering manner at at least two different intervals, as shown in FIG. The two types of intervals are characterized in that they are set at such intervals that the depletion layer formed between the diffusion region 40 and the semiconductor substrate 44 gradually connects as the applied voltage increases.
なお、アルミニウム膜49は他の金属膜であっても良い
ことは言うまでもない。Note that it goes without saying that the aluminum film 49 may be another metal film.
[作用]
本発明にあっては、このように、半導体基板44上に形
成される拡散抵抗において、拡散領域40の間隔を2種
類組み合わせたので、後述するような原理により、拡散
領域40よりなる拡散抵抗の抵抗値を印加電圧の増加に
つれて段階的に変化させることができるものである。[Function] In the present invention, in the diffused resistor formed on the semiconductor substrate 44, two types of spacing between the diffused regions 40 are combined, so that the distance between the diffused regions 40 is The resistance value of the diffused resistor can be changed stepwise as the applied voltage increases.
[実施例]
第1図は本発明の一実施例に係る抵抗器の拡散パターン
を示す平面図である。まず、第1図の破線Cで囲まれた
部分に形成される抵抗器の動作について、第2図乃至第
5図を用いて説明する。[Example] FIG. 1 is a plan view showing a diffusion pattern of a resistor according to an example of the present invention. First, the operation of the resistor formed in the portion surrounded by the broken line C in FIG. 1 will be explained using FIGS. 2 to 5.
第2図及び第3図に示す抵抗器(特願昭63−3248
6号参照)は、低不純物濃度の半導体基板44に導電型
の異なる不純物を拡散させた拡散領域40よりなる。こ
こでは、抵抗器が形成される単結晶シリコン基板にN型
の不純物を低濃度にドープして半導体基板44としてい
る。また、表面には、P型の不純物を高濃度に拡散され
た拡散領域40が形成されている。この拡散領域40は
、第2図に示すように、蛇行して形成されている。The resistors shown in Figures 2 and 3 (Patent Application No. 63-3248
(see No. 6) consists of a diffusion region 40 in which impurities of different conductivity types are diffused into a semiconductor substrate 44 with a low impurity concentration. Here, a semiconductor substrate 44 is formed by doping a single crystal silicon substrate on which a resistor is formed with N-type impurities at a low concentration. Furthermore, a diffusion region 40 in which P-type impurities are diffused at a high concentration is formed on the surface. As shown in FIG. 2, this diffusion region 40 is formed in a meandering manner.
拡散領域40は不純物濃度が高いので、低抵抗層となっ
ており、その不純!t#1度に応じた抵抗率を有する。Since the diffusion region 40 has a high impurity concentration, it is a low resistance layer, and the impurity! It has a resistivity corresponding to t#1 degree.
拡散領域40及び不純物半導体基板44の表面は、Si
O2よりなる絶縁147で覆われている。拡散領域40
の両端にはオーミック接触でアルミニウム電極41.4
2が接続されている。The surfaces of the diffusion region 40 and the impurity semiconductor substrate 44 are made of Si.
It is covered with an insulation 147 made of O2. Diffusion area 40
There are aluminum electrodes 41.4 in ohmic contact at both ends of the
2 are connected.
アルミニウム電極41.42間の抵抗値は、拡散領域4
0の抵抗率と、拡散領域40の幅と長さでほぼ決まる。The resistance value between the aluminum electrodes 41 and 42 is the same as that of the diffusion region 4.
It is approximately determined by the resistivity of 0 and the width and length of the diffusion region 40.
拡散領域40の不純物濃度は表面はど高く、電流密度は
表面近くほど高い、したがって、拡散領域40の深さは
抵抗値には余り関係しない、実施例では、N型の不純物
半導体基板44の比抵抗は60Ωcab、 P型の不純
物拡散領域40の幅は3μ転間隔は4μm、不純物とし
てはB(ボロン)を用い、濃度は2.5 X 10 ”
doseとした。The impurity concentration of the diffusion region 40 is highest at the surface, and the current density is higher near the surface.Therefore, the depth of the diffusion region 40 has little relation to the resistance value.In the embodiment, the ratio of the N-type impurity semiconductor substrate 44 The resistance is 60 Ωcab, the width of the P-type impurity diffusion region 40 is 3 μm, the pitch is 4 μm, B (boron) is used as the impurity, and the concentration is 2.5 × 10 ”
I set it to a dose.
一方のアルミニウム電極42は、N型の不純物を低濃度
に拡散された不純物半導体基板44にもオーミック接触
している。したがって、N型の不純物半導体基板44は
、安定な電位に保持される。One aluminum electrode 42 is also in ohmic contact with an impurity semiconductor substrate 44 in which N-type impurities are diffused at a low concentration. Therefore, the N-type impurity semiconductor substrate 44 is maintained at a stable potential.
なお、アルミニウムを極42と不純物半導体基板44が
オーミック接触する部分には、N型の不純物を高濃度に
拡散した電極領域43が形成されている。基板の上には
、アルミニウム電極41.42の形成後に、CVD法を
用いてSiO2よりなる5000人程度0バッシベーシ
ョンIll!48が被着されている。Note that an electrode region 43 in which an N-type impurity is diffused at a high concentration is formed in a portion where the aluminum pole 42 and the impurity semiconductor substrate 44 make ohmic contact. After forming aluminum electrodes 41, 42 on the substrate, about 5,000 bassivations made of SiO2 are applied using the CVD method. 48 is attached.
この抵抗器に電圧を印加すると、拡散領域40と不純物
半導体基板44の間のPN接合は、逆バイアス状態とな
る。不純物半導体基板44の不純物濃度が低いので、印
加電圧が低くても、空乏層は第4図(a)の破線で示す
ように不純物半導体基板44の側に大きく拡がる。さら
に、拡散領域40の上に存在する遮光を目的としたアル
ミニウム膜49を低電圧側の電[41と接続させること
により、フィールドプレート作用が強められ、印加電圧
の低い状態で空乏層を拡げることが可能となる。そして
、前記逆バイアス電圧が所定値を越えると、第4図(b
)の破線で示すように、不純物半導体基板44の中で空
乏層がつながってしまい、同図の矢印で示すように、電
子が流れ得る状態となる。したがって、蛇行する拡散領
域40を蛇行せずに電流が流れるようになり、抵抗器の
抵抗値が下がる。また、入力電圧が低いときには、第4
図(、)に示すように、空乏層がつながる状態には至ら
ないので、蛇行する拡散領域40により高抵抗が得られ
る。When a voltage is applied to this resistor, the PN junction between the diffusion region 40 and the impurity semiconductor substrate 44 becomes reverse biased. Since the impurity concentration of the impurity semiconductor substrate 44 is low, even if the applied voltage is low, the depletion layer greatly expands toward the impurity semiconductor substrate 44 as shown by the broken line in FIG. 4(a). Furthermore, by connecting the light-shielding aluminum film 49 that exists on the diffusion region 40 to the low voltage side electrode [41], the field plate effect is strengthened and the depletion layer is expanded in a state where the applied voltage is low. becomes possible. Then, when the reverse bias voltage exceeds a predetermined value, FIG.
), the depletion layers in the impurity semiconductor substrate 44 are connected, and electrons can flow as shown by the arrows in the figure. Therefore, current flows through the meandering diffusion region 40 without meandering, and the resistance value of the resistor decreases. Also, when the input voltage is low, the fourth
As shown in the figure (,), since the depletion layers do not reach a connected state, a high resistance can be obtained by the meandering diffusion region 40.
第5図は、この抵抗器の印加電圧と通電電流との関係を
示す。図中、光起電力の発生時における印加電圧と通電
電流の関係は、第1象限に示された特性のようになり、
所定値くここでは約3V)以上の印加電圧が加わると、
通電電流が急速に増加する。FIG. 5 shows the relationship between the applied voltage and the current flowing through this resistor. In the figure, the relationship between the applied voltage and the conducting current when photovoltaic force is generated is as shown in the first quadrant,
When an applied voltage of more than a predetermined value (approximately 3V here) is applied,
The carrying current increases rapidly.
第1図に示す抵抗器において、端子A、B間の抵抗値は
、印加電圧が低いときには約4.9MΩとなっているが
、印加電圧の増加により、破線Cで囲まれた部分でバン
チスルーが発生したときには、端子A、B間の抵抗値は
約0,4MΩとなり、さらに印加電圧を上げると、破&
lDで囲まれた部分でもバンチスルーが発生し、端子A
、B間の抵抗値は約0.1MΩとなる。破線Cで囲丈れ
た部分のバンチスルーは約3■で、また、破線りで囲ま
れた部分のバンチスルーは約6■で発生するように、拡
散パターンの間隔や、不純物濃度を設定している。In the resistor shown in Figure 1, the resistance value between terminals A and B is approximately 4.9 MΩ when the applied voltage is low, but as the applied voltage increases, bunch through occurs in the area surrounded by broken line C. When this occurs, the resistance value between terminals A and B will be approximately 0.4MΩ, and if the applied voltage is further increased, damage will occur.
Bunch-through also occurs in the area surrounded by LD, and terminal A
, B is approximately 0.1 MΩ. The spacing of the diffusion patterns and the impurity concentration are set so that the bunch through in the area surrounded by the broken line C occurs at approximately 3 cm, and the bunch through in the area surrounded by the broken line C occurs at approximately 6 cm. ing.
第1図に示す抵抗器RABを用いた簡単な電圧弁別回路
を第6図に示す。この回路は、入力電圧Vinを前記抵
抗器RABと固定抵抗器Roとで分圧して、出力電圧V
outを得るものである。固定抵抗器R。A simple voltage discrimination circuit using the resistor RAB shown in FIG. 1 is shown in FIG. This circuit divides the input voltage Vin by the resistor RAB and the fixed resistor Ro, and outputs the voltage V.
This is to obtain out. Fixed resistor R.
の抵抗値は100 KΩとした。同回路において、入力
電圧Vinを1〜IOVの範囲で変化させたときの出力
電圧Voutの変化と、抵抗器RA日の抵抗値の変化を
第7図に示す0図中、実線は出力電圧VouLを示して
おり、破線は抵抗器RAsの抵抗値を示している。The resistance value was 100 KΩ. In the same circuit, the change in the output voltage Vout when the input voltage Vin is changed in the range of 1 to IOV and the change in the resistance value of the resistor RA are shown in Figure 7. In Figure 7, the solid line indicates the output voltage VouL. , and the broken line indicates the resistance value of the resistor RAs.
なお、本発明の抵抗器はモノリシックIC上に形成する
用途に特に適するものであるが、単体の抵抗器としても
使用できることは言うまでもない。Note that although the resistor of the present invention is particularly suitable for use in forming on a monolithic IC, it goes without saying that it can also be used as a single resistor.
[発明の効果〕
本発明の抵抗器にあっては、低不純物濃度の半導体基板
に導電型の異なる拡散領域を少なくとも2種類の間隔で
形成し、半導体基板と拡散領域の間に形成されるPN接
合が逆バイアスされるように半導体基板の電位を設定し
、空乏層を拡げるような電位に設定された金属膜を拡散
領域を覆うように配するという、通常の半導体製造プロ
セスで簡単に製造できる構造でありながら、印加電圧の
増加につれて抵抗値が段階的に変化する拡散抵抗を得る
ことができるという効果がある。また、拡散領域におけ
る2種類の間隔の組み合わせを変えることにより、任意
の抵抗変化特性を実現できるという利点がある。[Effects of the Invention] In the resistor of the present invention, diffusion regions of different conductivity types are formed at least two types of intervals in a semiconductor substrate with a low impurity concentration, and the PN formed between the semiconductor substrate and the diffusion region is It can be easily manufactured using normal semiconductor manufacturing processes, which involves setting the potential of the semiconductor substrate so that the junction is reverse biased, and placing a metal film set at a potential that expands the depletion layer to cover the diffusion region. Despite the structure, it is possible to obtain a diffused resistance whose resistance value changes stepwise as the applied voltage increases. Furthermore, there is an advantage that an arbitrary resistance change characteristic can be realized by changing the combination of two types of intervals in the diffusion region.
第1図は本発明の一実施例に係る抵抗器の拡散パターン
を示す平面図、第2図及び第3図はそれぞれ同上の要部
構成を説明するための斜視図及び断面図、第4図は同上
の動作説明図、第5図は同上の電圧−電流特性を示す図
、第6図は同上の実施例の一応用例を示す回路図、第7
図は同上の動作説明図である。
40は拡散領域、44は不純物半導体基板、49はアル
ミニウム膜である。
第1図
40・・・拡散領域
44−・−不純物半導体基板FIG. 1 is a plan view showing a diffusion pattern of a resistor according to an embodiment of the present invention, FIGS. 2 and 3 are a perspective view and a sectional view respectively illustrating the configuration of the main parts of the same, and FIG. 4 is an explanatory diagram of the same operation as above, FIG. 5 is a diagram showing the voltage-current characteristics of the same as above, FIG. 6 is a circuit diagram showing an example of application of the above embodiment, and
The figure is an explanatory diagram of the same operation as above. 40 is a diffusion region, 44 is an impurity semiconductor substrate, and 49 is an aluminum film. FIG. 1 40...Diffusion region 44--Impurity semiconductor substrate
Claims (1)
物を拡散させた拡散領域を形成し、半導体基板と拡散領
域の間に生じるPN接合が逆バイアスされるように半導
体基板の電位を設定し、拡散領域と半導体基板の間に生
じる空乏層を拡げるような電位を印加された金属薄膜を
拡散領域を覆うように配して成る抵抗器において、拡散
領域は少なくとも2種類の間隔で蛇行するように形成さ
れ、前記2種類の間隔は、拡散領域と半導体基板の間に
生じる空乏層が印加電圧の増加につれて段階的につなが
るような間隔に設定されていることを特徴とする抵抗器
。(1) A diffusion region in which impurities of different conductivity types are diffused is formed in a semiconductor substrate with a low impurity concentration, and the potential of the semiconductor substrate is set so that the PN junction generated between the semiconductor substrate and the diffusion region is reverse biased. , in a resistor in which a metal thin film to which a potential is applied to expand a depletion layer generated between the diffusion region and the semiconductor substrate is arranged so as to cover the diffusion region, the diffusion region is meandered at at least two different intervals. 2. A resistor, characterized in that the two types of intervals are set at intervals such that a depletion layer generated between the diffusion region and the semiconductor substrate gradually connects as the applied voltage increases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1895889A JPH02197162A (en) | 1989-01-26 | 1989-01-26 | Resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1895889A JPH02197162A (en) | 1989-01-26 | 1989-01-26 | Resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02197162A true JPH02197162A (en) | 1990-08-03 |
Family
ID=11986155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1895889A Pending JPH02197162A (en) | 1989-01-26 | 1989-01-26 | Resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02197162A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258916B2 (en) | 2008-07-02 | 2012-09-04 | Nxp B.V. | Meander resistor |
-
1989
- 1989-01-26 JP JP1895889A patent/JPH02197162A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258916B2 (en) | 2008-07-02 | 2012-09-04 | Nxp B.V. | Meander resistor |
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