JPH02199854A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02199854A JPH02199854A JP1911189A JP1911189A JPH02199854A JP H02199854 A JPH02199854 A JP H02199854A JP 1911189 A JP1911189 A JP 1911189A JP 1911189 A JP1911189 A JP 1911189A JP H02199854 A JPH02199854 A JP H02199854A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- excluding
- semiconductor device
- polyimide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000011347 resin Substances 0.000 abstract description 22
- 229920005989 resin Polymers 0.000 abstract description 22
- 238000007789 sealing Methods 0.000 abstract description 21
- 229920001721 polyimide Polymers 0.000 abstract description 19
- 239000009719 polyimide resin Substances 0.000 abstract description 15
- 239000010408 film Substances 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 6
- 239000004642 Polyimide Substances 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 229910000831 Steel Inorganic materials 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910000851 Alloy steel Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特に半導体装置
のリードフレームに関スる。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a lead frame of a semiconductor device.
従来、この種の半導体装置は、ニッケルと鉄の合金や鋼
材等の薄板をプレスによる打ち抜き又はエツチングによ
り所定の形状のリードフレームを得、アイランドに所定
の集積回路（以下ＩＣと略記する）チップを搭載し、ポ
ンディングワイヤで、リードフレームのステッチ部とＩ
Ｃチップとを接続した後、樹脂封止を行なっていた。Conventionally, this type of semiconductor device has been produced by punching or etching a thin plate of nickel-iron alloy or steel to obtain a lead frame in a predetermined shape, and then mounting a predetermined integrated circuit (hereinafter abbreviated as IC) chip on an island. The stitched part of the lead frame and I are connected with the bonding wire.
After connecting with the C chip, resin sealing was performed.
上述した半導体装置は、リードフレームの表面にＩＣチ
ップを搭載し、リードフレームとＩＣチップをポンディ
ングワイヤで接続した後、４００℃程度の溶融した樹脂
で封止する。この場合、リードフレームと封止樹脂の熱
膨張率の違いにより封止樹脂に応力がかかり、封止樹脂
にクラックが入るという欠点がある。そのため、クラッ
ク発生による回路素子の損傷、および半導体装置内部へ
水分が浸入することによる金属部材の腐食、短絡等の問
題が発生していた。In the semiconductor device described above, an IC chip is mounted on the surface of a lead frame, the lead frame and the IC chip are connected with a bonding wire, and then sealed with molten resin at about 400°C. In this case, there is a drawback that stress is applied to the sealing resin due to the difference in thermal expansion coefficient between the lead frame and the sealing resin, causing cracks in the sealing resin. This has caused problems such as damage to circuit elements due to cracks, corrosion of metal members due to moisture infiltration into the semiconductor device, and short circuits.
本発明の目的は、上記問題を解決し、樹脂封止時に封止
樹脂に加わるストレスの発生を緩和できる半導体装置を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can solve the above problems and alleviate the stress that is applied to the sealing resin during resin sealing.
本発明の半導体装置のリードフレームは、少なくとも集
積回路チップ搭載面およびポンディングの施されるステ
ッチ部を除く、樹脂封止領域内の少なくともリードフレ
ームの表面にポリイミド樹脂膜等の応力緩衝膜を有して
いる。そのため、樹脂封止時にリードフレームと封止樹
脂間の熱膨張率の違いにより生じる応力を緩和すること
ができるものである。The lead frame of the semiconductor device of the present invention has a stress buffering film such as a polyimide resin film on at least the surface of the lead frame within the resin sealing area, excluding at least the integrated circuit chip mounting surface and the stitched portion where bonding is performed. are doing. Therefore, it is possible to alleviate stress caused by a difference in coefficient of thermal expansion between the lead frame and the sealing resin during resin sealing.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）は本発明の第１の実施例の平面図であり、
第１図（ｂ）はＡ−Ａ’線における断面図である。二、
ケルと鉄の合金又は鋼材等の薄板をプレスによる打ち抜
き又はエツチングにより所定の形状にバターニングした
リードフレーム１において、ＩＣチップの搭載されるア
イランド２のチップ搭載面およびＩＣチップとボンディ
ングされるステッチ３を除く樹脂封止領域４内の少なく
ともリードフレーム１０表面にポリイミド樹脂膜５が設
けられている。このような構成により樹脂封止時にリー
ドフレームと封止樹脂間の熱膨張率の違いにより生じる
応力がポリイミド樹脂膜により緩和され、直接封止樹脂
に応力が加わることはない。FIG. 1(a) is a plan view of the first embodiment of the present invention,
FIG. 1(b) is a sectional view taken along line AA'. two,
In the lead frame 1, which is formed by patterning a thin plate of steel and iron alloy or steel into a predetermined shape by punching or etching with a press, the chip mounting surface of the island 2 on which an IC chip is mounted and the stitch 3 that is bonded to the IC chip. A polyimide resin film 5 is provided on at least the surface of the lead frame 10 within the resin-sealed region 4 except for the lead frame 10 . With this configuration, stress caused by a difference in coefficient of thermal expansion between the lead frame and the sealing resin during resin sealing is alleviated by the polyimide resin film, and no stress is directly applied to the sealing resin.
本実施例に示した半導体装置は、例えばリードフレーム
用薄板を所定の形状にバターニングした後、溶融したポ
リイミド樹脂を滴下し、ポリイミドの薄膜を形成し、そ
の後、公知のエツチング技術を用いて、アイランド部２
とステッチ部３を除くリードフレーム形状にバターニン
グすることにより形成される。In the semiconductor device shown in this embodiment, for example, a thin plate for a lead frame is patterned into a predetermined shape, and then molten polyimide resin is dropped to form a polyimide thin film, and then, using a known etching technique, Island part 2
It is formed by patterning the lead frame shape excluding the stitched portion 3.
また、バターニングされていないリードフレーム用薄板
にポリイミド薄膜を形成した後、エツチングによりポリ
イミド薄膜とリードフレーム用薄板を所定の形状にバタ
ーニングしても良い。Alternatively, after a polyimide thin film is formed on an unpatterned lead frame thin plate, the polyimide thin film and the lead frame thin plate may be patterned into a predetermined shape by etching.
次に第２図に本発明の第２の実施例を示す。第１の実施
例ではリードフレームの上下面のみ、あるいは上下およ
び側面がポリイミド樹脂膜により被覆されているだけで
あったが本実施例では、アイランド部２およびステッチ
部３を除く樹脂封止領域内全域にポリイミド樹脂膜５′
が形成されている。そのためＩＣチップとのワイヤ接続
のためにリードフレーム１から突出して設けられている
内部リード１′間の応力が緩和され封止樹脂のクラック
発生の危険性を抑えることができる。Next, FIG. 2 shows a second embodiment of the present invention. In the first embodiment, only the top and bottom surfaces of the lead frame, or the top and bottom and side surfaces were covered with the polyimide resin film, but in this embodiment, the resin sealing area excluding the island portion 2 and the stitch portion 3 is covered with a polyimide resin film. Polyimide resin film 5' over the entire area
is formed. Therefore, the stress between the internal leads 1', which are provided protruding from the lead frame 1 for wire connection with the IC chip, is relaxed, and the risk of cracks in the sealing resin can be suppressed.
本実施例の製造方法は、リードフレーム用薄板をバター
ニングした後、溶融したポリイミド樹脂を滴下し、エツ
チングによりアイランド部２．ステッチ部３．および樹
脂封止領域外のポリイミド樹脂膜を除去すれば良い。In the manufacturing method of this embodiment, after patterning a thin plate for a lead frame, molten polyimide resin is dropped and etching is performed to form the island portion 2. Stitch part 3. Then, the polyimide resin film outside the resin-sealed area may be removed.
以上説明したように本発明は、アイランドおよびステッ
チを除く、少なくとも樹脂封止領域内のリードフレーム
表面にポリイミド樹脂膜を形成することによりリードフ
レームと封止樹脂の熱膨張率の違いによる封止樹脂のス
トレスがポリイミド樹脂膜により緩和されクラックの発
生を防止でき、信頼性の高い半導体装置を提供できる。As explained above, the present invention has the advantage of forming a polyimide resin film on the surface of the lead frame at least in the resin sealing area, excluding the islands and stitches, to prevent the sealing resin from forming the sealing resin due to the difference in thermal expansion coefficient between the lead frame and the sealing resin. This stress is alleviated by the polyimide resin film, preventing the occurrence of cracks, and providing a highly reliable semiconductor device.
第１図（ａ）のＡ−Ａ’の断面図、第２図は本発明の第
２の実施例を示す平面図である。FIG. 1(a) is a sectional view taken along line AA', and FIG. 2 is a plan view showing a second embodiment of the present invention.
１・・・・・・リードフレーム、１′・・・・・・内部
リード、２・・・・・・アイランド、３・・・・・・ス
テッチ、４・・印・樹脂封止領域、５，５′・・・・・
・ポリイミド樹脂膜。1... Lead frame, 1'... Internal lead, 2... Island, 3... Stitch, 4... Mark/resin sealing area, 5 ,5'...
・Polyimide resin film.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第１図（ａ）は本発明の第１の実施例を示す半導体装置
のリードフレームの平面図、第１図（ｂ）は（１）ノ
茅
凹
茅
閏FIG. 1(a) is a plan view of a lead frame of a semiconductor device showing a first embodiment of the present invention, and FIG. 1(b) is a plan view of a lead frame of a semiconductor device according to a first embodiment of the present invention.
Claims (1)
およびステッチ部を除く樹脂封止領域内の少なくともリ
ードフレームの表面に応力緩衝膜を設けたことを特徴と
する樹脂封止型半導体装置。1. A resin-sealed semiconductor device, characterized in that a stress buffer film is provided on at least a surface of a lead frame within a resin-sealed region excluding an integrated circuit chip mounting surface and a stitched portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1911189A JPH02199854A (en) | 1989-01-27 | 1989-01-27 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1911189A JPH02199854A (en) | 1989-01-27 | 1989-01-27 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02199854A true JPH02199854A (en) | 1990-08-08 |
Family
ID=11990370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1911189A Pending JPH02199854A (en) | 1989-01-27 | 1989-01-27 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02199854A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04106964A (en) * | 1990-08-27 | 1992-04-08 | Nec Corp | Semiconductor device |
| WO2025084109A1 (en) * | 2023-10-18 | 2025-04-24 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
-
1989
- 1989-01-27 JP JP1911189A patent/JPH02199854A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04106964A (en) * | 1990-08-27 | 1992-04-08 | Nec Corp | Semiconductor device |
| WO2025084109A1 (en) * | 2023-10-18 | 2025-04-24 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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