JPH0220166B2 - - Google Patents
Info
- Publication number
- JPH0220166B2 JPH0220166B2 JP59051448A JP5144884A JPH0220166B2 JP H0220166 B2 JPH0220166 B2 JP H0220166B2 JP 59051448 A JP59051448 A JP 59051448A JP 5144884 A JP5144884 A JP 5144884A JP H0220166 B2 JPH0220166 B2 JP H0220166B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- emitter
- capacitor
- emitter follower
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 230000010355 oscillation Effects 0.000 claims description 4
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1433—Balanced arrangements with transistors using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
- H03D7/1425—Balanced arrangements with transistors
- H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Superheterodyne Receivers (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、主としてテレビジヨンチユーナー回
路、CATVコンバーター回路等に用いることの
できる高周波領域における集積回路を用いた高周
波信号処理装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a high frequency signal processing device using an integrated circuit in a high frequency region, which can be used mainly for television tuner circuits, CATV converter circuits, and the like.
従来例の構成とその問題点
従来の高周波信号処理装置の一例を第１図に示
す。Configuration of Conventional Example and Its Problems An example of a conventional high frequency signal processing device is shown in FIG.
図示する高周波信号処理装置は周波数混合回路
１、エミツタホロア回路２、中間周波数増幅回路
３によつて構成されている。周波数混合回路１
は、ダブルバランス型回路により構成され、端子
Ａより局部発振信号が供給され、端子Ｂより高周
波信号が供給される。周波数混合回路１の出力信
号はシングルバランスでとり出され、高周波成分
と直流成分の両方をエミツタホロア回路２に供給
する。エミツタホロア回路２にて、インピーダン
ス変換を行つたのち、その出力は中間周波数増幅
回路３に供給され、ここで帯域同調がなされて端
子Ｇより所望の周波数帯域を示す中間周波信号を
得ることができる。各段の回路は、集積回路４の
内部にて構成されている。 The illustrated high-frequency signal processing device includes a frequency mixing circuit 1, an emitter follower circuit 2, and an intermediate frequency amplification circuit 3. Frequency mixing circuit 1
is constituted by a double-balanced circuit, a local oscillation signal is supplied from terminal A, and a high frequency signal is supplied from terminal B. The output signal of the frequency mixing circuit 1 is taken out in a single balanced manner, and both the high frequency component and the DC component are supplied to the emitter follower circuit 2. After impedance conversion is performed in the emitter follower circuit 2, its output is supplied to an intermediate frequency amplifier circuit 3, where band tuning is performed and an intermediate frequency signal indicating a desired frequency band can be obtained from a terminal G. The circuits at each stage are configured inside the integrated circuit 4.
中間周波数増幅回路３の内部構成は、エミツタ
ホロワ回路２の出力をトランジスタ３１のベース
に供給し、そのエミツタに抵抗３２，３３とバイ
パス容量３４による帰還をかけ利得調整をなし、
かつトランジスタ３１のコレクタに接続される容
量３５とコイル３６，３７にて帯域同調負荷を構
成し、コイル３６，３７の分割点よりインピーダ
ンス変換された所望の周波数帯域の出力信号を結
合容量８を介して出力端子に供給している。 The internal configuration of the intermediate frequency amplifier circuit 3 is such that the output of the emitter follower circuit 2 is supplied to the base of the transistor 31, and the emitter is fed back by resistors 32, 33 and a bypass capacitor 34 to adjust the gain.
A capacitor 35 connected to the collector of the transistor 31 and coils 36 and 37 constitute a band-tuned load, and an output signal of a desired frequency band whose impedance has been converted from the dividing point of the coils 36 and 37 is passed through a coupling capacitor 8. is supplied to the output terminal.
ところが、トランジスタ３１のベース側から見
た入力インピーダンスは負性インピーダンスとな
り第１図のエミツタホロア回路２の入力側や、周
波数混合回路１の入力端子への正帰還ループを構
成し、発振状態等の不安定動作に陥いつてしまう
という欠点があつた。 However, the input impedance seen from the base side of the transistor 31 becomes a negative impedance, forming a positive feedback loop to the input side of the emitter follower circuit 2 in FIG. The drawback was that the operation became unstable.
発明の目的
本発明は、かかる動作の不安定状態を改善する
ものであり、安定動作を確保するための手段を集
積回路内で構成することを目的とするものであ
る。OBJECTS OF THE INVENTION The present invention aims to improve such unstable state of operation, and it is an object of the present invention to configure means for ensuring stable operation within an integrated circuit.
発明の構成
本発明による高周波信号処理装置は、高周波信
号と、局部発振信号とをダブルバランス型周波数
混合回路に加え、その出力をダブルバランス回路
の第１〜４のスイツチングトランジスタの一方の
共通コレクタに接続された負荷回路と該共通コレ
クタの交点からとり、これをエミツタホロア回路
を通した後に、トランジスタのベースに加え、上
記トランジスタはそのエミツタとアース間に抵抗
を挿入し、この抵抗の中間からアース間に容量を
挿入し、かつ上記トランジスタのコレクタに帯域
同調負荷回路を構成するとともに、上記トランジ
スタのベースとエミツタ間に容量を接続し、この
容量を集積回路内で構成することを特徴とするも
のであり、上記容量にて正帰還ループを遮断する
ことができ、回路動作の不安定状態を除去するこ
とができるものである。Structure of the Invention The high frequency signal processing device according to the present invention adds a high frequency signal and a local oscillation signal to a double-balanced frequency mixing circuit, and outputs the output from the common collector of one of the first to fourth switching transistors of the double-balanced circuit. The intersection of the common collector and the load circuit connected to A capacitor is inserted between the transistors, a band-tuned load circuit is configured on the collector of the transistor, a capacitor is connected between the base and the emitter of the transistor, and this capacitor is configured within an integrated circuit. The positive feedback loop can be interrupted by the capacitance described above, and unstable conditions in the circuit operation can be eliminated.
実施例の説明 本発明の一実施例の構成を第２図に示す。Description of examples FIG. 2 shows the configuration of an embodiment of the present invention.
図示する高周波信号処理装置はダブルバランス
型周波数混合回路１とエミツタホロア回路２と中
間周波数増幅回路３により構成され、図の４で示
す範囲が集積回路で構成されている部分である。
なお、ここで第１図と同一回路、同一素子には同
一番号を付している。局部発振信号を端子Ａから
供給し、端子Ｂより高周波信号を供給するとダブ
ルバランス型周波数混合回路１のシングル出力に
は、前述と同様に高周波成分と直流成分とを含ん
だ信号が出力されエミツタホロア回路２に供給さ
れる。エミツタホロア回路２はインピーダンス変
換した信号を中間周波増幅回路３に供給する。 The illustrated high-frequency signal processing device is composed of a double-balanced frequency mixing circuit 1, an emitter follower circuit 2, and an intermediate frequency amplification circuit 3, and the area indicated by 4 in the figure is the part composed of integrated circuits.
Note that the same circuits and elements as in FIG. 1 are given the same numbers. When a local oscillation signal is supplied from terminal A and a high frequency signal is supplied from terminal B, a signal containing a high frequency component and a DC component is outputted to the single output of the double-balanced frequency mixing circuit 1 as described above, and the emitter follower circuit 2. The emitter follower circuit 2 supplies the impedance-converted signal to the intermediate frequency amplification circuit 3.
中間周波増幅回路３の動作は第１図と同様であ
り、構成要素１〜８は同じ物で同じ番号を付して
いるのでその説明は省略する。 The operation of the intermediate frequency amplification circuit 3 is the same as that shown in FIG. 1, and since the components 1 to 8 are the same and are given the same numbers, their explanation will be omitted.
この回路では、第１図の場合に問題となつたト
ランジスタ１のベース側から見た負性インピーダ
ンスを改善するために、トランジスタ１のベース
とエミツタ間に容量３９を接続することによりこ
れを改善し、周波数混合回路１の入力端子Ｂ及び
エミツタホロア回路２の入力端子への正帰還ルー
プをしや断している。上記容量３９は0.5pF〜
1pFの値で十分であり、集積回路４内で構成して
もチツプ面積の著しい増加にはならない。 In this circuit, in order to improve the negative impedance seen from the base side of transistor 1, which was a problem in the case of Figure 1, this was improved by connecting a capacitor 39 between the base and emitter of transistor 1. , the positive feedback loop to the input terminal B of the frequency mixing circuit 1 and the input terminal of the emitter follower circuit 2 is interrupted. The capacitance 39 above is 0.5pF ~
A value of 1 pF is sufficient, and configuring it within the integrated circuit 4 does not significantly increase the chip area.
また集積回路の外部ピン数をも増加させないと
いう点で実用上有効な手段であるといえる。 It can also be said that this is a practically effective means in that it does not increase the number of external pins of the integrated circuit.
発明の効果
このように、本発明によれば、集積回路のピン
数を増やすことなく簡単な構成によつて動作の安
定した高周波信号処理装置を得ることができる。Effects of the Invention As described above, according to the present invention, a high frequency signal processing device with stable operation can be obtained with a simple configuration without increasing the number of pins of an integrated circuit.
第１図は従来の高周波信号処理装置の構成を示
す回路図、第２図は本発明による高周波信号処理
装置の実施例を示す回路図である。
１……ダブルバランス型周波数混合回路、２…
…エミツタホロア回路、３……中間周波増幅回
路、３１……トランジスタ、３４，３５，３８，
３９……容量、３２，３３……抵抗、３６，３７
……コイル。
FIG. 1 is a circuit diagram showing the configuration of a conventional high frequency signal processing device, and FIG. 2 is a circuit diagram showing an embodiment of the high frequency signal processing device according to the present invention. 1...Double balanced frequency mixing circuit, 2...
... emitter follower circuit, 3 ... intermediate frequency amplification circuit, 31 ... transistor, 34, 35, 38,
39... Capacity, 32, 33... Resistance, 36, 37
……coil.
Claims (1)
ス型周波数混合回路に加え、この周波数混合回路
の出力信号を同回路を構成する第１〜第４のスイ
ツチングトランジスタの一方の共通コレクタに設
定された負荷回路と上記共通コレクタの交点から
取り出し、この出力信号をエミツタフオロア回路
を通した後にエミツタ接地型トランジスタのベー
スに加えるようにするとともに、上記周波数混合
回路、エミツタフオロア回路並びにトランジスタ
は集積回路化し、上記トランジスタのエミツタと
アース間に抵抗を挿入し、この抵抗の中間からア
ース間に容量を挿入し、かつ上記トランジスタの
コレクタに帯域同調負荷回路を構成するととも
に、上記トランジスタのベースとエミツタ間に容
量を接続し、かつこの容量は上記集積回路内で構
成することを特徴とする高周波信号処理装置。1. A high frequency signal and a local oscillation signal are added to a double-balanced frequency mixing circuit, and the output signal of this frequency mixing circuit is applied to a load set to the common collector of one of the first to fourth switching transistors that make up the circuit. The output signal is taken out from the intersection of the circuit and the common collector, and after passing through the emitter follower circuit, is applied to the base of the emitter grounded transistor.The frequency mixing circuit, the emitter follower circuit, and the transistor are integrated into an integrated circuit. Insert a resistor between the emitter and ground, insert a capacitor between the resistor and the ground, configure a band-tuned load circuit on the collector of the transistor, and connect a capacitor between the base and emitter of the transistor. , and the capacitor is configured within the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59051448A JPS60194811A (en) | 1984-03-16 | 1984-03-16 | High frequency signal processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59051448A JPS60194811A (en) | 1984-03-16 | 1984-03-16 | High frequency signal processing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60194811A JPS60194811A (en) | 1985-10-03 |
| JPH0220166B2 true JPH0220166B2 (en) | 1990-05-08 |
Family
ID=12887211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59051448A Granted JPS60194811A (en) | 1984-03-16 | 1984-03-16 | High frequency signal processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60194811A (en) |
-
1984
- 1984-03-16 JP JP59051448A patent/JPS60194811A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60194811A (en) | 1985-10-03 |
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