JPH02201794A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the configuration of its output buffer 7 circuit portion.

[Conventional technology]

FIG. 3 is a circuit diagram of one channel (hereinafter referred to as N-ch) and a transistor in the final stage of the output buffer circuit of a conventional semiconductor memory device, and FIG. 4 is a circuit diagram of the N-ch transistor in the circuit of FIG. 3. FIG. 3 is a waveform diagram showing input signals and output waveforms of the /data output transistor. In this case, (1) is an "H" data output transistor, and (2) is an "L" data output transistor.

Next, the operation will be explained. When the input signal B1 of the N-ch 'L' data output transistor (2) in the final stage of the output buffer 7 circuit goes from 'L' to <'H' and outputs 'L' data, the output waveform Dout is , it is pulled from the high impedance state to O(V) and tries to become 0(■), but as shown in FIG. 4, undershoot occurs and ringing occurs.

[Problem to be solved by the invention]

Since the final stage N-ch transistor circuit of a conventional output buffer circuit is configured as described above, ringing occurs due to undershoot when data is output.
Therefore, access time is delayed.

The present invention was made to solve the above-mentioned problems, and aims to speed up access time by suppressing ringing due to undershoot of the output waveform.

[Means to solve the problem]

Is this invention an output buffer circuit? An output buffer circuit is provided which momentarily turns on the <''H' data output transistor of the output buffer 7 circuit after turning on the L'/data output transistor and opening it with a slight delay.

[Effect]

The output buffer circuit according to the present invention suppresses ringing due to undershoot of the 'hL/1 data output signal, making it possible to speed up access time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the final stage N-c of the output buffer circuit of a semiconductor memory device.
h) Circuit diagram of a transistor. In the figure, the source is connected to the power supply voltage and the drain is connected to the output pin.
〃Data output transistor.

(2) is a data output transistor with the source connected to the ground and the drain connected to the output pin, (3)
is a one-shot pulse generating circuit that generates a one-shot pulse in the input signal AI when the input signal B2 changes from L' to "H".

FIG. 2 shows the input signal B2. Bl, AI and output waveform Do
FIG. 2 is a waveform diagram showing ut.

Next, the operation will be explained. Before data output, input signal A2. Both B2 are ゞL〃, and when outputting <''L// data, the input signal B2 changes from ``L'' to ゞH〃, so the input signal B1 also changes from ゞL' to <H, like input signal B2. 〃, <'L〃Data output transistor (2)
is ON L, and the output waveform Dout attempts to go from a high impedance state to 0 (V). However, input signal B
2 changes from ゞL〃 to ``H'', the input signal A1 also momentarily changes from ゞL〃 to "H" by the one-shot pulse generation circuit (3), so that the ``H'' data output transistor (1) - Since it is turned on momentarily, the through current is prevented from flowing and the output waveform Dout becomes O(V). Therefore, the amount of undershoot of the output waveform Dout becomes smaller,
Ringing is also reduced.

〔Effect of the invention〕

As described above, according to the present invention, when data is output, <y L //After the data output transistor is turned on, <
By turning on the "H" data output transistor momentarily, the output waveform is momentarily blunted, the amount of undershoot is reduced, and ringing is less likely to occur, making it possible to speed up the access time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a final stage N-ch transistor of an output buffer 1 circuit of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a waveform diagram showing input signals and output waveforms in the circuit of FIG. , FIG. 3 is a circuit diagram of a final N-ch transistor of an output buffer circuit in a conventional semiconductor memory device, and FIG. 4 is a waveform diagram showing input signal and output waveforms in the circuit of FIG. 3. In the figure, (1) is a <'H' data output transistor, (2) is a 'L' data output transistor, and (3) is a one-shot pulse generation circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] After turning on the "Low" (hereinafter referred to as "L") data output transistor of the output buffer circuit, after a short period of time, the "High" (hereinafter referred to as "H") data output transistor of the output buffer circuit is turned ON. A semiconductor memory device comprising an output buffer circuit that is turned on.