JPH0487419A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, particularly to the structure of its output buffer circuit portion.

[Conventional technology]

Fig. 4 is a circuit diagram of a conventional output buffer 1 circuit, and Fig. 5 is a circuit diagram of one conventional output buffer circuit.
4 is a timing chart showing each signal and output waveform at the time of data output.
(hereinafter referred to as "L") In Figure 0, which is a timing chart showing each signal and output waveform at the time of data output, (1
) is an N-channel (hereinafter referred to as N-ch) "H" data output transistor (hereinafter referred to as Tr), (2] is an N-c
h"L" data output Tr.

f6) is an output terminal.

Next, the operation will be explained. First, when outputting "H" data, when the main amplifier output data B2 is "H" and the main amplifier output data c2 is "L", the output control signal A
When I changes from "L" to "H", the control signal CI of the N-ch "L" data output Tr (2) remains "Lo" and N
-Ch"H" data output T r (11 control signal B1
is from “L” to “H”.

The output is high impedance (hereinafter referred to as “Hi-2”).
When outputting "L" data, main amplifier output data B2 is "L" and main amplifier output data C2 is "♂". When the wI control signal 1 changes from 'L' to 'H', the control signal B1 of N-ch 'H1 data output Tr!I) remains 'L' and the N-ch 'L' data output Tr
The control signal C1 in (2) changes from °L° to "H", the output changes from the Hi-z state to "L", and outputs °L data.

At this time, when trying to speed up the access time, N-ah
``L'' When the size of data output Tr (2) is increased,
Output ringing occurs.

Problem to be solved by the invention C] Since the conventional output buffer circuit is configured as described above, in order to speed up the access time, the N-ch “L”
``Increasing the size of the data output Tr causes problems such as output ringing and, conversely, a delay in access time.

This invention was made to solve the above problems, and suppresses ringing due to undershoot.
The object of the present invention is to obtain a semiconductor memory device with faster processing times.

[Means to solve the problem]

The semiconductor memory device according to the present invention is provided with a second N-ch "L" data output Tr between the output terminal and the ground, and the input signal of the "L" data output Tr is generated by an output control signal. This is a one-shot pulse signal.

[Effect]

By using the output buffer circuit as described above in the semiconductor memory device of the present invention, ringing due to undershoot of the "L" data output signal can be suppressed and access time can be increased.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of the output buffer circuit. In figure 0, the drain is the power supply voltage, and the source is the output terminal (6
) respectively connected to N-c h″H” data output T
r, +21 is the first N-ch "L" data output T r, (31 is the source connected to the ground and the drain connected to the output terminal (6)), whose source is connected to the output terminal (6). , the second ON-ch whose gate is connected to the signal from the one-shot pulse generation circuit, respectively.
"L" data output cuff r +41 is a delay circuit, (5
) is a one-shot pulse generation circuit.

FIG. 2 shows the signal A3. when "H" data is output in the circuit of FIG. A2. A1. B2. It is a timing chart showing Bl, C2, C1, and output waveforms.

Figure 3 shows the signal A3.A2゜Am when outputting °L” data.
B2. 2 is a timing chart showing Bl, C2, CI, and output waveforms.

Next, the operation will be explained. First, when outputting "H" data, when the main amplifier output data B2 is H' and the main amplifier output data C2 is "L", the output wi damage signal 3 changes from "L" to °H'. The shot pulse generation circuit (5) generates one shot pulse A2 of 1L"
to @H”, and the second N-ch “L” data output T
r131 turns "ON" and the output changes from the "Hi-z" state to the "L level".After that, when the delay signal A1 of the output side IIM No. A3 changes from °L2 to °H, the H-ch "H" data output T r ill control signal B1 changes from "L" to "H", H-ch "H" data output T r (L) turns "ON", and at the same time one-shot pulse A2 changes to 1H" In order to return to “L” from
H-ch “L” data output T r f3) is “OFF”
'L' The output was about to go to 'L', but soon went to 'H'.

Next, when outputting “L” data, main amplifier output data B2 is “L” and main amplifier output data C2 is “H”.
”, when the output control signal A3 changes from “L” to H, the one-shot pulse generation circuit (5) changes the one-shot pulse A2 from “L” to @H, and the second N-c
h'L" data output T r (31 is "ON',
The output changes from "B5-z"teM to "L" level, and then when the delay signal A1 of the output control signal A3 changes from "S" to "1H", the N-ch'1." data output T r ( The wi control signal C1 of 21 goes from "L" to "H", and the first N-ch'L" data output T r (21 turns 'ON').

At the same time, since the one-shot pulse A2 returns from "Hl" to "L#," the second N-ch'L" data output T"(3) turns off, but the first N-ch'L2 data output T Since r f21 is “ON”, the output data is “
Becomes L#.

At this time, the second N-ch'L' data output Tr (3) turns "ON" and the output level tries to become "Hi-z" color "L", but the output level becomes VOL level (output N− before the data reaches a level that is recognized as “L’”
ch"H" data output Tr (1) or first N-c
h'L" data output Tr (2) turns "ON", and the second N-ch "L" data output Tr (31 turns "OFF").
``Certify to do so.

As mentioned above, once the output is changed from the “Hi-z” state to °)(
By turning on the output Tr and outputting the output after setting it to a level lower than "i-z" and higher than the VOL level, the amount of undershoot becomes small or does not occur when "L" data is output, and ringing can be suppressed. Also, when outputting "H data, N~ch"H' data output T r fi
The driving force of N-ch “L” data output T r (21
By making the driving force larger than that of the VOH level (the level at which the output data is recognized as "H") and "H" Since the potential difference between this level and the level at which the data settles is large, access is not affected.

〔Effect of the invention〕

As described above, according to the present invention, the output level is
By changing the level from the Hi-z state to below the Hi-z level and above the VOL level, and then turning the output Tr "ON" and outputting the output, the amount of undershoot will be small or will not occur when the "L" data is output. Since ringing can be suppressed, access time can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an output buffer circuit according to an embodiment of the semiconductor memory device according to the present invention, and FIG. 2 shows each signal and output waveform when "H" data is output in the circuit of FIG. 3 is a timing chart diagram showing each signal and output waveform when "L" data is output in the circuit of FIG. 1; FIG. 4 is a circuit diagram of a conventional output buffer circuit; The figure is a timing chart showing each signal and output waveform when 'H' data is output in the circuit of Figure 4. Figure 6 is a timing chart showing each signal and output waveform when 'H' data is output in the circuit of Figure 4. FIG. 3 is a timing chart diagram showing waveforms. In the figure, (1) is the N-ch “H” data output Tr
, (21, (31 is N-ch'L" data output T r
, (41 is a delay circuit, (5) is a one-shit pulse generation circuit, and (6) is an output terminal. In the figures, the same reference numerals indicate the same or equivalent parts. Agent: Masuo Oiwa Figure 1

Claims (1)

[Claims] In the output buffer circuit, a "high" data output transistor has its drain connected to the power supply voltage and its source to the output terminal, a first "low" data output transistor has its drain connected to the output terminal and its source to ground, and the drain is connected to the output terminal. In addition, an output buffer circuit is provided which has a second "Low" data output transistor whose source is connected to ground, and which momentarily turns "ON" the second "Low" data output transistor immediately before data is output. A semiconductor memory device characterized by: