JPH02201947A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02201947A
JPH02201947A JP1020042A JP2004289A JPH02201947A JP H02201947 A JPH02201947 A JP H02201947A JP 1020042 A JP1020042 A JP 1020042A JP 2004289 A JP2004289 A JP 2004289A JP H02201947 A JPH02201947 A JP H02201947A
Authority
JP
Japan
Prior art keywords
lead
semiconductor element
electrode
electrodes
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1020042A
Other languages
Japanese (ja)
Inventor
Kenji Ooyachi
賢治 大谷内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1020042A priority Critical patent/JPH02201947A/en
Publication of JPH02201947A publication Critical patent/JPH02201947A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To double electrode placement space and realize high-density mounting by disposing electrodes on two oppositely facing sides and connecting a first and a second lead which are insulated and the electrode on each side. CONSTITUTION:In a semiconductor element 1, a circuit is formed on two oppositely facing sides, a plurality of electrodes 2 are disposed on the edge of each side, and an internal lead 3 is placed near each electrode 2. The internal lead 3 is formed in such a manner that a first lead 3a and a second lead 3b are stacked via an insulator 3c. The electrode 2 disposed on the top surface of the semiconductor element 1 and the first lead 3a are connected by a metal fine wire 4. The electrode 2 disposed on the bottom surface of the semiconductor element 1 and the second lead 3b are connected by a metal fine wire 4. Thus, wire connection can be made from both sides of the semiconductor element 1. As a result, electrodes of a two-fold number can be mounted at the same electrode wiring density. Thus, a yield at manufacturing time can be enhanced and a high integration is possible.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体素子上の電極とリードフレームとを金属
細線で結線してなる半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which an electrode on a semiconductor element and a lead frame are connected with a thin metal wire.

[従来の技術] 従来、この種の半導体装置は、リードフレームの素子搭
載部に半導体素子を固着し、半導体素子上に設けられた
電極と、リードフレームの内部リードとを回路形成面側
から金属細線にて結線し、この結線部を例えば樹脂で封
止することによって構成されていた。
[Prior Art] Conventionally, in this type of semiconductor device, a semiconductor element is fixed to the element mounting part of a lead frame, and the electrodes provided on the semiconductor element and the internal leads of the lead frame are connected with metal from the circuit forming surface side. It was constructed by connecting with a thin wire and sealing the connected portion with, for example, resin.

[発明が解決しようとする課題] しかしながら、上述した従来の半導体装置では半導体素
子の集積度の向上に伴って入出力ビン数が増加すると、
半導体素子上の電極数も増加し、半導体素子が大型化す
るという問題点があった。
[Problems to be Solved by the Invention] However, in the conventional semiconductor device described above, when the number of input/output bins increases as the degree of integration of semiconductor elements increases,
There was a problem that the number of electrodes on the semiconductor element also increased, making the semiconductor element larger.

また、半導体素子を小型化しようとすると、実装密度が
増加し、電極間隔が狭くなるため、電極とリードフレー
ムの内部リードとを金属細線で結線する場合に結線済み
の隣接する金属細線に結線治工具が接触し、隣接する金
属細線を変形させ、極端な場合には切断してしまい、半
導体素子の歩留りを低下させるという問題点があった。
In addition, when trying to miniaturize semiconductor devices, the packaging density increases and the spacing between electrodes becomes narrower. There is a problem in that the tool comes into contact with the metal wire, deforming the adjacent metal wire, and in extreme cases cutting it, reducing the yield of semiconductor devices.

本発明はかかる問題点に鑑みてなされたものであって、
製造時の歩留りが高いと共に、高集積化が可能の半導体
装置を提供することを目的とする。
The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a semiconductor device that has a high manufacturing yield and can be highly integrated.

[課題を解決するための手段] 本発明に係る半導体装置は、複数の電極が形成された半
導体素子と、この半導体素子の各電極の近傍に一端が配
置された複数のリードと、これらリードの一端と前記半
導体素子の各電極とを夫々接続する金属細線とを備えた
半導体装置において、前記半導体素子は、相対する両面
に夫々複数の電極が形成され、前記複数のリードは少な
くともその一部が絶縁体を介して重合された第1のリー
ド及び第2のリードからなり、前記金属細線は前記半導
体素子の一方の面に形成された電極と前記第1のリード
とを接続すると共に、前記半導体素子の他方の面に形成
された電極と前記第2のリードとを接続するものである
ことを特徴とする。
[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor element in which a plurality of electrodes are formed, a plurality of leads having one end disposed near each electrode of the semiconductor element, and a plurality of leads of these leads. In a semiconductor device comprising thin metal wires connecting one end and each electrode of the semiconductor element, the semiconductor element has a plurality of electrodes formed on opposing surfaces, and at least a part of the plurality of leads is It consists of a first lead and a second lead that are polymerized through an insulator, and the thin metal wire connects the electrode formed on one surface of the semiconductor element and the first lead, and also connects the first lead to the electrode formed on one surface of the semiconductor element. It is characterized in that the electrode formed on the other surface of the element is connected to the second lead.

[作用] 本発明においては、複数のリードの少なくとも一部が、
絶縁体を介して第1及び第2のリードを重合させた三重
構造となっている。そして、半導体装置には、その両面
に電極が形成され、一方の面の電極が第1のリードと、
また、他方の面の電極が第2のリードと結線される。従
って、本発明によれば、電極の配置スペースを従来の2
倍にすることができ、その分だけ電極の配置密度を低下
させることができるので、高集積度の半導体装置につい
ても製造時の歩留りの低下を抑制することができる。
[Function] In the present invention, at least some of the plurality of leads are
It has a triple structure in which the first and second leads are polymerized via an insulator. Electrodes are formed on both sides of the semiconductor device, and the electrode on one side is connected to a first lead,
Further, the electrode on the other side is connected to the second lead. Therefore, according to the present invention, the space for arranging the electrodes can be reduced compared to the conventional one.
Since the number of electrodes can be doubled and the arrangement density of electrodes can be reduced by that amount, it is possible to suppress a decrease in yield during manufacturing even for highly integrated semiconductor devices.

[実施例] 次に、本発明の実施例について添付の図面を参照して説
明する。
[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

第1図は本発明の第1の実施例に係る樹脂封止型半導体
装置を示す図で、(a)はその一部を示す平面図、(b
)は立面図、(c)は側面図である。
FIG. 1 is a diagram showing a resin-sealed semiconductor device according to a first embodiment of the present invention, in which (a) is a plan view showing a part of the device, and (b)
) is an elevational view, and (c) is a side view.

半導体素子1は相対する2つの面に回路が形成されてお
り、各面の周縁部に複数の電極2を配設したものとなっ
ている。リードフレームは素子搭載部を持たず、その内
部リード3が前記各電極2の近傍に配置されたものとな
っている。内部り−ド3は、第1のリード3aと第2の
リード3bとを絶縁体3cを介して重ね合わせた構造と
なっている。第1のリード3aは、半導体素子1の図中
上面側に配置され、第2のリード3bは、半導体素子1
の図中下面側に配置されている。そして、半導体素子1
の上面に設けられた電極2と第1のり−ド3aとが、ま
た、半導体素子1の下面に設けられた電極2と第2のリ
ード3bとが夫々金属細線4によって接続されている。
The semiconductor element 1 has circuits formed on two opposing surfaces, and a plurality of electrodes 2 arranged at the periphery of each surface. The lead frame does not have an element mounting portion, and its internal leads 3 are arranged near each of the electrodes 2. The internal lead 3 has a structure in which a first lead 3a and a second lead 3b are overlapped with an insulator 3c interposed therebetween. The first lead 3a is arranged on the upper surface side of the semiconductor element 1 in the figure, and the second lead 3b is arranged on the upper surface side of the semiconductor element 1.
It is located on the bottom side in the figure. And semiconductor element 1
The electrode 2 provided on the upper surface and the first lead 3a are connected by the thin metal wire 4, and the electrode 2 provided on the lower surface of the semiconductor element 1 and the second lead 3b are connected, respectively.

更に、この結線部分を含めて半導体素子1は封止樹脂5
により封止されている。
Furthermore, the semiconductor element 1 including this connection portion is covered with a sealing resin 5.
It is sealed by.

このように構成された樹脂封止型半導体装置によれば、
半導体素子1の両面から結線を行うことができるので、
従来と同一の電極配線密度で従来の2倍の数の電極を配
置することできる。このため、現在のリードフレームの
作成技術及びワイヤボンディング技術を考慮した場合で
も、外部へ引き出し可能な外部電極数を400本以上に
することが可能である。
According to the resin-sealed semiconductor device configured in this way,
Since connections can be made from both sides of the semiconductor element 1,
Twice the number of electrodes can be arranged with the same electrode wiring density as in the past. Therefore, even when current lead frame production technology and wire bonding technology are considered, it is possible to increase the number of external electrodes that can be drawn out to the outside to 400 or more.

第2図は、本発明の第2の実施例に係る樹脂封止型半導
体装置を示す図で、(a)はその一部を示す平面図、(
b)は立面図、(c)は側面図である。なお、この第2
図において第1図と同一物には同一符号を付しその部分
の説明は省略する。
FIG. 2 is a diagram showing a resin-sealed semiconductor device according to a second embodiment of the present invention, in which (a) is a plan view showing a part of the device;
b) is an elevational view, and (c) is a side view. Note that this second
In the figure, the same parts as in FIG. 1 are given the same reference numerals, and the explanation of those parts will be omitted.

この実施例では、リードフレームの一部の内部リード3
′が、第1のり一部3aと第2のリード3bとを金属3
dを介して重ね合わせた構造となっている。
In this embodiment, some internal leads 3 of the lead frame are
′ connects the first glue portion 3a and the second lead 3b to the metal 3
It has a structure in which they are overlapped via d.

この実施例によれば、半導体素子1の相対する2つの面
に形成された回路相互間で内部リード3′を介して電気
信号の授受を行うことができるので、外部にてこれら回
路を結線するための作業を省略することが可能であると
いう利点がある。
According to this embodiment, since electrical signals can be exchanged between the circuits formed on two opposing surfaces of the semiconductor element 1 via the internal leads 3', these circuits can be connected externally. This has the advantage that it is possible to omit the necessary work.

[発明の効果コ 以上説明したように、本発明は半導体素子の相対する2
つの面に電極を設け、絶縁体によって絶縁された第1の
リード及び第2のリードと、各面の電極とを結線してい
るので、1つの面からしが結線を行わなかった従来の半
導体装置に比して、電極の配置スペースを2倍にするこ
とでき、高密度実装が可能になる。また、1枚の半導体
ウェハから生産される半導体素子数を約2倍とすること
でき、製品コストの低減を図ることが可能である。
[Effects of the Invention] As explained above, the present invention provides
Since electrodes are provided on two surfaces and the first and second leads insulated by an insulator are connected to the electrodes on each surface, conventional semiconductors with one surface do not have wiring connections. Compared to other devices, the electrode arrangement space can be doubled, allowing high-density packaging. Further, the number of semiconductor elements produced from one semiconductor wafer can be approximately doubled, and product costs can be reduced.

更に、本発明によれば電極間隔を従来の2倍にすること
が可能となることから、金属細線で結線する場合に、治
工具が金属細線を変形させたり、切断することがない。
Furthermore, according to the present invention, it is possible to double the electrode spacing compared to the conventional one, so when connecting thin metal wires, the jigs and tools do not deform or cut the thin metal wires.

このため、半導体装置の製造歩留りが向上すると共に、
信頼性を著しく向上させることができる。
Therefore, the manufacturing yield of semiconductor devices is improved, and
Reliability can be significantly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の第1の実施例に係る樹脂封止型
半導体装置の一部を示す平面図、第1図(b)は同装置
の立面図、第1図(c)は同装置の側面図、第2図(a
)は本発明の第2の実施例に係る樹脂封止型半導体装置
の一部を示す平面図、第2図(b)は同装置の立面図、
第2図(C)は同装置の側面図である。 1;半導体素子、2;電極、3.3’  、内部リード
、3a;第1のリード、3b;第2のリード、3c;絶
縁体、3d;金属、4;金属mt!、5;封止樹脂
FIG. 1(a) is a plan view showing a part of a resin-sealed semiconductor device according to the first embodiment of the present invention, FIG. 1(b) is an elevational view of the device, and FIG. ) is a side view of the device, and Figure 2 (a) is a side view of the same device.
) is a plan view showing a part of a resin-sealed semiconductor device according to a second embodiment of the present invention, FIG. 2(b) is an elevational view of the device,
FIG. 2(C) is a side view of the device. 1; Semiconductor element, 2; Electrode, 3.3', Internal lead, 3a; First lead, 3b; Second lead, 3c; Insulator, 3d; Metal, 4; Metal mt! , 5; Sealing resin

Claims (1)

【特許請求の範囲】[Claims] (1)複数の電極が形成された半導体素子と、この半導
体素子の各電極の近傍に一端が配置された複数のリード
と、これらリードの一端と前記半導体素子の各電極とを
夫々接続する金属細線とを備えた半導体装置において、
前記半導体素子は、相対する両面に夫々複数の電極が形
成され、前記複数のリードは少なくともその一部が絶縁
体を介して重合された第1のリード及び第2のリードか
らなり、前記金属細線は前記半導体素子の一方の面に形
成された電極と前記第1のリードとを接続すると共に、
前記半導体素子の他方の面に形成された電極と前記第2
のリードとを接続するものであることを特徴とする半導
体装置。
(1) A semiconductor element having a plurality of electrodes formed thereon, a plurality of leads having one end disposed near each electrode of the semiconductor element, and a metal connecting one end of these leads to each electrode of the semiconductor element, respectively. In a semiconductor device equipped with a thin wire,
In the semiconductor element, a plurality of electrodes are formed on each of opposing surfaces, the plurality of leads are composed of a first lead and a second lead, at least a part of which are polymerized through an insulator, and the thin metal wire connects an electrode formed on one surface of the semiconductor element and the first lead, and
an electrode formed on the other surface of the semiconductor element and the second
A semiconductor device, characterized in that the semiconductor device is connected to a lead.
JP1020042A 1989-01-30 1989-01-30 Semiconductor device Pending JPH02201947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1020042A JPH02201947A (en) 1989-01-30 1989-01-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1020042A JPH02201947A (en) 1989-01-30 1989-01-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02201947A true JPH02201947A (en) 1990-08-10

Family

ID=12016004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1020042A Pending JPH02201947A (en) 1989-01-30 1989-01-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02201947A (en)

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