JPH02202065A - Manufacturing method of static induction transistor - Google Patents

Manufacturing method of static induction transistor

Info

Publication number
JPH02202065A
JPH02202065A JP2279889A JP2279889A JPH02202065A JP H02202065 A JPH02202065 A JP H02202065A JP 2279889 A JP2279889 A JP 2279889A JP 2279889 A JP2279889 A JP 2279889A JP H02202065 A JPH02202065 A JP H02202065A
Authority
JP
Japan
Prior art keywords
gate
source
shape
formation
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2279889A
Other languages
Japanese (ja)
Inventor
Hiroyuki Mizukami
裕之 水上
Shuji Masumura
増村 修司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Komatsu Ltd
Original Assignee
Komatsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Ltd filed Critical Komatsu Ltd
Priority to JP2279889A priority Critical patent/JPH02202065A/en
Publication of JPH02202065A publication Critical patent/JPH02202065A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the dispersion of a transistor characteristics and to improve it in switching speed by a method wherein the doping required for the formation of a gate and a source electrode section is executed through a laser doping method, and the epitaxial growth made for the formation of a source is performed in an environment of low temperature. CONSTITUTION:The doping required for the formation of a gate 204 and a source electrode section 205 is executed through a laser doping method, and the epitaxial growth made for the formation of a source 205 is performed in an environment of low temperature. Therefore, a reaction is prevented from taking place outside a required range, and the shape of impurity of a channel section which forms a gate can be uniformly formed just conforming to the shape of a mask 203, and the channel section can be made short, so that the channel section can be stably made small in resistance as in the same as designed. The impurity is formed very sharp in form, so that a depletion layer can be reduced in capacity. By this setup, a transistor of this design can be protected against dispersion in characteristics and improved in switching speed.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は静電誘導型トランジスタの製造方法に係わり、
特にゲートチャネルの抵抗値が低く特性のばらつきの少
ない安定な静電誘導型トランジスタの製造方法に関する
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a static induction transistor,
In particular, the present invention relates to a method for manufacturing a stable static induction transistor with a low gate channel resistance value and little variation in characteristics.

[従来の技術] 従来、静電誘導型トランジスタの製造は第3図に示すよ
うな過程で行われている。
[Prior Art] Conventionally, static induction transistors have been manufactured through a process as shown in FIG.

例えばN型の静電誘導型トランジスタを製造するにはま
ず第3図(a>に示すようなドレイン電極を形成するた
めの不純物濃度の高いN型半導体層302と層をなしエ
ピタキシャル成長等で形成した低不純物濃度のN型半導
体301の上に(b)に示すように形成すべきゲート形
状に合わせてたパタン形状にホトリソグラフィ技術等に
よって空隙を設けたマスキングを行い(303)、その
空隙からゲートを形成させるように3族元素例えばボロ
ンを熱拡散またはイオン注入によってドーピングさせ(
304)、マスキングの材料を除去しな後(c)に示す
ように5iC1ガス中、約1100°Cの雰囲気中でN
型の低不純物濃度層をエピタキシャル成長させ(305
)、その上に5族の元素例えば燐を拡散させて高不純物
層のソースを形成させ(306)、最後に(e)に示す
ようにゲート部をエツチングした後純粋なアルミニュー
ム等をメタライズして各電極を形成させている。
For example, to manufacture an N-type static induction transistor, first a layer is formed by epitaxial growth or the like with an N-type semiconductor layer 302 having a high impurity concentration for forming a drain electrode as shown in FIG. 3 (a). As shown in (b), on the N-type semiconductor 301 with a low impurity concentration, masking is performed by creating a void using photolithography technology in a pattern shape that matches the shape of the gate to be formed (303), and the gate is formed from the void. A group 3 element such as boron is doped by thermal diffusion or ion implantation to form (
304), after removing the masking material, N was removed in 5iC1 gas at about 1100°C as shown in (c).
A low impurity concentration layer of the mold is epitaxially grown (305
), a group 5 element such as phosphorus is diffused thereon to form a highly impurity layer source (306), and finally, as shown in (e), after etching the gate part, pure aluminum or the like is metallized. Each electrode is formed using the same method.

第3図(e)において307がソース、308がゲート
、309がトレインの各電極である。
In FIG. 3(e), 307 is a source electrode, 308 is a gate electrode, and 309 is a train electrode.

[発明が解決しようとする課題] ところが上記従来の製造方法では、不純物のドーピング
において約1100°Cという高温による熱処理を行う
なめに、ゲートを構成するチャネル部分の不純物の形状
がマスク形状の通りにならないで第3図(b)の304
及び第4図の曲線300に示すようにように必要とする
形状に仕上がらないでキャリアの通路であるN型の低不
純物層との境目が崩れて拡がるため、チャネル抵抗が増
大するとか特性がばらつくという問題があった。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional manufacturing method, the shape of the impurity in the channel portion constituting the gate follows the shape of the mask because heat treatment at a high temperature of approximately 1100°C is not required for doping the impurity. 304 in Figure 3(b)
As shown by the curve 300 in FIG. 4, the required shape is not completed and the boundary with the N-type low impurity layer, which is a carrier path, collapses and widens, resulting in an increase in channel resistance and variations in characteristics. There was a problem.

本発明は上記従来の問題点に着目し、ゲートを構成する
チャネル部分の不純物の形状がマスク形状の通りに−様
に形成することの出来る静電誘導型トランジスタの製造
方法を提供することを目的としている。
The present invention has focused on the above-mentioned conventional problems, and an object of the present invention is to provide a method for manufacturing a static induction transistor in which the shape of the impurity in the channel portion constituting the gate can be formed in accordance with the shape of a mask. It is said that

[課題を解決するための手段] 上記目的を達成するために、本発明による静電誘導型ト
ランジスタの製造方法では、半導体によって製作された
ドレインとなるべき基盤上に基盤の材質に対して不活性
な材質によって製作され目的とするパタン状の空隙を持
つマスクを設け、該マスクの空隙から不純物を注入して
ゲートを構成させ、マスクを除いた後にエピタキシャル
成長によってソースを形成させるようにした静電型トラ
ンジスタの製法において、ゲート作成のためのドーピン
グを室温においてレーザドーピングによって行い、ソー
ス形成のためのエピタキシャル成長を低温環境において
なすようにして静電誘導型トランジスタを製造するよう
にした。
[Means for Solving the Problems] In order to achieve the above object, in the method for manufacturing a static induction transistor according to the present invention, a material that is inert to the material of the substrate is formed on a substrate that is to be a drain made of a semiconductor. An electrostatic type method in which a mask is made of a suitable material and has voids in the desired pattern, and impurities are injected into the voids of the mask to form a gate, and after the mask is removed, a source is formed by epitaxial growth. In a method for manufacturing a transistor, doping for forming a gate is performed by laser doping at room temperature, and epitaxial growth for forming a source is performed in a low-temperature environment to manufacture a static induction transistor.

[作用] 上記製造方法によれば、ゲート及びソース電極部形成の
ためのドーピングをレーザドーピングによって行い、ソ
ース形成のためのエピタキシャル成長を低温環境におい
てなすようにしたので必要とする範囲以外まで反応が進
むことが無くなり、ゲートを構成するチャネル部分の不
純物の形状がマスク形状の通りに−様に形成することが
出来、従ってチャネルを短く出来るので抵抗値を設計通
り小さく安定に形成することが出来るので特性がばらつ
くことがなく−様な特性の静電誘導型トランジスタを製
作することができる。また不純物の形状が急峻に仕上が
るので空乏層容量が減りスイッチング速度を向上するこ
とが出来な。
[Function] According to the above manufacturing method, the doping for forming the gate and source electrode portions is performed by laser doping, and the epitaxial growth for forming the source is performed in a low temperature environment, so that the reaction progresses beyond the required range. The shape of the impurity in the channel part constituting the gate can be formed in the same way as the mask shape, and the channel can therefore be shortened, making it possible to stably form the resistance value as small as the design. It is possible to manufacture static induction type transistors with various characteristics without any variation in the characteristics. Furthermore, since the shape of the impurity is finished steeply, the depletion layer capacitance decreases, making it impossible to improve the switching speed.

[実施例コ 以下本発明に係わる静電誘導型トランジスタの実施例を
図面を参照して詳細に説明する。第1図によって本発明
に基づく静電誘導型トランジスタの製造過程の一実施例
を説明する。
[Embodiment 2] Hereinafter, embodiments of the static induction transistor according to the present invention will be described in detail with reference to the drawings. An embodiment of the manufacturing process of a static induction transistor according to the present invention will be explained with reference to FIG.

例えばN型静電誘導型トランジスタを製造するには、ま
ず第1図(a>に示すようなドレイン電極を形成するた
めの不純物濃度の高いN型半導体層202と層をなしエ
ピタキシャル成長等で形成した低不純物濃度のN型半導
体201の上に(b)に示すように形成すべきゲート形
状に合わせてたパタン形状にホトリソグラフィ技術等に
よって空隙を設けてアルミニューム又は多結晶のシリコ
ンによってマスキングを行い(203)、その空隙にし
たがってゲートを形成させるように3族元素例えばボロ
ンを含むドーパントガスの雰囲気の中でレーザ光を照射
してレーザによる局部的な熱によってドーピングさせ(
204)、マスキングの材料をエツチング剤によって溶
解除去した後、モノシランガスの約600乃至700°
Cの雰囲気中でN型の低不純物濃度層をエピタキシャル
成長させ(205)、その上に5族の元素例えば燐を含
むオスフィンガスの雰囲気の中で再びレーザドーピング
させて高不純物層のソースを形成させる(206)、最
後に(e)に示すようにゲート部をエツチングした後純
粋なアルミニューム等をメタライズして各゛電極を形成
させている。
For example, in order to manufacture an N-type static induction transistor, first, a layer is formed with an N-type semiconductor layer 202 having a high impurity concentration for forming a drain electrode as shown in FIG. As shown in (b) on the N-type semiconductor 201 with a low impurity concentration, voids are created using photolithography technology in a pattern shape that matches the shape of the gate to be formed, and masking is performed with aluminum or polycrystalline silicon. (203), by irradiating a laser beam in an atmosphere of a dopant gas containing a group 3 element such as boron so as to form a gate according to the gap, and doping by localized heat from the laser (
204), after dissolving and removing the masking material with an etching agent, monosilane gas is heated at about 600 to 700°
An N-type low impurity concentration layer is epitaxially grown in a C atmosphere (205), and then laser doping is performed again in an osphine gas atmosphere containing a group 5 element such as phosphorus to form a source of a high impurity layer. Finally, as shown in (e), after etching the gate portion, pure aluminum or the like is metallized to form each electrode.

第3図(e)において207がソース、208がゲート
209がドレインの各電極である。
In FIG. 3(e), 207 is a source electrode, and 208 is a gate 209, which is a drain electrode.

本発明に基づくゲート電極部のP型層の形状は第4図の
曲線200に示されるように、従来の製造方法によって
製作された300の曲線にしめされた電極部のようにN
型層との境界が不明確になること無く明確に形成される
The shape of the P-type layer of the gate electrode part according to the present invention is as shown by curve 200 in FIG.
The boundary with the mold layer is clearly formed without becoming unclear.

次にレーザドーピングの方法について第2図によって説
明する。
Next, the method of laser doping will be explained with reference to FIG.

第2図は本発明に基づく静電誘導型トランジスタのレー
ザドーピング装置の概要図であって、ゲートを形成させ
るためのマスキングを施した基盤らを排気装置7によっ
て内部の気体が#を出されている真空槽4の中に固定し
ている。真空槽4の中に固定された基盤5のマスキング
を施した前面には石英で作られた窓6があってレーザ装
置1からのレーザ光8が誠意を通して基盤5に当たるよ
うになっている。真空槽4には二つの口があって一方か
らは排気装置7によって排気ガス9を排出させ、もう一
方の口からは低圧の反応ガスを注入させている。また、
真空槽4は加熱されず常温のまま維持されている。
FIG. 2 is a schematic diagram of a laser doping apparatus for an electrostatic induction transistor according to the present invention, in which internal gas is exhausted by an exhaust device 7 from a masked substrate for forming a gate. It is fixed in a vacuum chamber 4. A window 6 made of quartz is provided on the masked front side of a substrate 5 fixed in a vacuum chamber 4, so that a laser beam 8 from a laser device 1 can be directed to the substrate 5 through the laser beam. The vacuum chamber 4 has two ports, and exhaust gas 9 is discharged from one port by an exhaust device 7, and low-pressure reaction gas is injected from the other port. Also,
The vacuum chamber 4 is not heated and is maintained at room temperature.

次に真空槽4の内部の働きについて説明する。Next, the internal workings of the vacuum chamber 4 will be explained.

真空槽4は排気装置7によって排気した状態で3族元素
を含む例えばボロンを含むドーパントガスを水素ガスで
希釈して低圧で注入し、真空槽4の中に固定された基盤
5は稀薄なドーパントガスが表面に接触している状態に
なっている。
The vacuum chamber 4 is evacuated by an exhaust device 7, and a dopant gas containing group 3 elements, for example boron, is diluted with hydrogen gas and injected at low pressure. The gas is in contact with the surface.

ドーパントガスが表面に接触し、空隙を設けたマスキン
グを成されている基盤5の表面にレーザ装置1によって
垂直にレーザ光8を照射すると、該基盤5の表面におけ
るマスキングの空隙は瞬間的にレーザのエネルギによっ
て局部的に溶融し、溶融した基盤のシリコンの結晶構造
の中にボロンが溶は込んで横方向には拡散しないために
設計の侭の形状にP型結晶が構成される。
When the laser device 1 irradiates the laser beam 8 perpendicularly to the surface of the substrate 5, which is masked with voids in contact with the surface of the dopant gas, the voids in the masking on the surface of the substrate 5 are instantaneously exposed to the laser beam. The P-type crystal is formed in the designed shape because the boron is melted locally by the energy of , and the boron melts into the crystal structure of the molten base silicon and does not diffuse laterally.

例えばガス圧50 torrの雰囲気中でエキシマレー
ザによって1,6J/cm’ショットのニオ・ルギーを
照射すると濃度3X10”/cm’深さ0.4μのゲー
ト部が形成される。
For example, by irradiating 1.6 J/cm' shots of Nitrogen with an excimer laser in an atmosphere with a gas pressure of 50 torr, a gate portion with a concentration of 3 x 10''/cm' and a depth of 0.4 μm is formed.

ソースの為の高不純物濃度の結晶を形成させるには上述
しな3族元素を含むガスのかわりに5族の元素を含むガ
ス例えば燐を含んだオスフィンガスを注入した中でレー
ザをスキャニングすることによって同一の真空槽4を用
いて加工することが出来る。
To form a crystal with a high impurity concentration for the source, scan a laser in a gas containing a group 5 element, such as osphine gas containing phosphorus, instead of a gas containing a group 3 element as described above. This allows processing to be performed using the same vacuum chamber 4.

またガス圧およびレーザ装置は拡散したい深さや濃度に
従って適当な圧力および発光方式の装置を選べば良い [発明の効果] 以上説明したように本発明に基づく静電誘導型トランジ
スタの製造方法によれば、ゲート及びソース電極部形成
のためのドーピングをレーザドーピングによって行い、
ソース形成のためのエピタキシャル成長を低温環境にお
いてなすようにしたので必要とする範囲以外まで反応が
進むことが無くなり、ゲートを構成するチャネル部分の
不純物の形状がマスキング形状の通りに、また、深さも
浅く−様に形成することが出来、従ってチャネル距離を
短く出来るので抵抗値を設計通り小さく安定に形成する
ことが出来るので特性がばらつくことがなく−様な特性
の静電誘導型トランジスタを製作することができる。ま
た不純物の形状が急峻に仕上がるので空乏層容量が減り
スイッチング速度を向上することが出来た。
In addition, the gas pressure and laser device may be selected according to the desired diffusion depth and concentration. [Effects of the Invention] As explained above, according to the method of manufacturing a static induction transistor based on the present invention, , doping for forming the gate and source electrode portions is performed by laser doping,
Since the epitaxial growth for forming the source is performed in a low-temperature environment, the reaction does not proceed beyond the required range, and the shape of the impurity in the channel part that makes up the gate follows the masking shape, and the depth is also shallow. -The channel distance can be shortened, so the resistance value can be formed stably to a small value as designed, and the characteristics will not vary. Can be done. Furthermore, since the shape of the impurity is finished steeply, the depletion layer capacitance is reduced and the switching speed can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に基づく静電誘導型トランジスタ製造過
程の説明図。 第2図は本発明に基づくレーザドーピング装置の概要図
。 第3図は従来の静電誘導型トランジスタ製造過程の説明
図。 第4図は本発明による製造方法と従来の製造方法による
ゲート周辺の不純物濃度と浸透深さの違いの説明用曲線
図。 1・・・・・・レーザ装置 2・・・・・・反応ガス 4・・・・・・真空槽 5・・・・・・基盤 6・・・・・・石英窓 7・・・・・・排気装置 8・・・−・・レーザ 9・・・・・・排気ガス 200.300・・・不純物濃度/浸透深さ特性曲線 201.301・・・ドレイン側を形成する基盤202
.302・・・ドレイン電極部 203.303・・・マスキング 204.304・・・ゲート 205.305・・・ソース 206.306・・・ソース電極部 207.307・・・電1iiii(ソース)208.
308・・・電極(ゲート) 209.309・・・電極(ドレイン)出願人   株
式会社小松製作所 第2図 (b) (C) 第1図 第3図
FIG. 1 is an explanatory diagram of the manufacturing process of a static induction type transistor based on the present invention. FIG. 2 is a schematic diagram of a laser doping apparatus based on the present invention. FIG. 3 is an explanatory diagram of a conventional static induction transistor manufacturing process. FIG. 4 is a curve diagram for explaining the difference in impurity concentration and penetration depth around the gate between the manufacturing method according to the present invention and the conventional manufacturing method. 1...Laser device 2...Reactive gas 4...Vacuum chamber 5...Base 6...Quartz window 7...・Exhaust device 8...Laser 9...Exhaust gas 200.300...Impurity concentration/penetration depth characteristic curve 201.301...Base 202 forming the drain side
.. 302...Drain electrode part 203.303...Masking 204.304...Gate 205.305...Source 206.306...Source electrode part 207.307...Electricity 1iii (source) 208.
308...Electrode (gate) 209.309...Electrode (drain) Applicant: Komatsu Ltd. Figure 2 (b) (C) Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体によって製作されたドレインとなるべき基盤上に
基盤の材質に対して不活性な材質によつて製作され目的
とするパタン状の空隙を持つマスクを設け、該マスクの
空隙から不純物をドーピングしてゲートを構成させ、マ
スクを除いた後にエピタキシャル成長によってソースを
形成させるようにした静電誘導型トランジスタの製造方
法において、ゲート作成のためのドーピングをレーザド
ーピングによって行い、ソース形成のためのエピタキシ
ャル成長を低温環境においてなすようにしたことを特徴
とする静電誘導型トランジスタの製造方法。
A mask made of a material inert to the material of the substrate and having voids in the desired pattern is provided on a substrate which is to be a drain made of a semiconductor, and impurities are doped through the voids of the mask. In a method for manufacturing a static induction transistor in which a gate is formed and a source is formed by epitaxial growth after removing a mask, doping for forming the gate is performed by laser doping, and epitaxial growth for forming the source is performed in a low temperature environment. 1. A method of manufacturing a static induction transistor, characterized by comprising:
JP2279889A 1989-01-31 1989-01-31 Manufacturing method of static induction transistor Pending JPH02202065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2279889A JPH02202065A (en) 1989-01-31 1989-01-31 Manufacturing method of static induction transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2279889A JPH02202065A (en) 1989-01-31 1989-01-31 Manufacturing method of static induction transistor

Publications (1)

Publication Number Publication Date
JPH02202065A true JPH02202065A (en) 1990-08-10

Family

ID=12092705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2279889A Pending JPH02202065A (en) 1989-01-31 1989-01-31 Manufacturing method of static induction transistor

Country Status (1)

Country Link
JP (1) JPH02202065A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226775A (en) * 1989-02-28 1990-09-10 Komatsu Ltd Semiconductor manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226775A (en) * 1989-02-28 1990-09-10 Komatsu Ltd Semiconductor manufacturing method

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