JPH02205111A - Waveform formatter circuit - Google Patents

Abstract

PURPOSE:To obtain a signal with short pulse width without being affected by the operating minimum pulse width of an RS flip-flop by directly generating the rise of a pulse with a first clock edge signal and the fall of the pulse with a second clock edge signal. CONSTITUTION:A gate 24 is closed by setting an NRZ signal to be added on the gate 24 at,'LOW', and a clock edge signal 2 whose timing is adjusted inputted from a delay element 22 is prevented from passing. Therefore, no D-FF 25 is operated, and only a D-FF 23 is operated by pattern data added from a memory 3 and a clock edge signal 1 added via a delay element 21. Since the D-FF 23 outputs the pattern data added on a terminal D at the leading edge of the clock edge signal 1, the NRZ signal can be obtained from the terminal Q of the D-FF 23. Thereby, it is possible to secure the pulse width of an output signal as a preset value as designed, and to obtain the signal with pulse width narrower than conventional one.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a waveform formatter circuit that outputs a pulse train signal and is capable of setting the pulse generation period and pulse width.

<Prior Art> For example, in the field of LSI testers and the like, pulse train signals with different pulse generation periods and pulse widths are required to test LSIs.

FIG. 4 is a diagram showing the configuration of a conventional waveform formatter circuit.
FIG. 3 is a time chart of this circuit.

In FIG. 4, 1 is a reference clock generator that generates a reference clock, 2 is a program counter (hereinafter simply referred to as PC2) that counts this reference clock, and 3 is a P
This is a memory into which the count value of C2 is introduced as an address signal, and pattern data described later is written6.
For example, memory 3 address ^01:1, ^D2:0,
When AD3: 1, A[14:0 is written, reference clocks CI, C2, C3°C41, . . . are generated, and the output of PC2 becomes 401. ＾02. At)3.・・・
. . , the pattern data shown in FIG. 3 (1) is output from the memory 3. Here 1 is “HIGH”, 0
means "tow".

4 is a programmable edge generator (hereinafter simply P
EG4) and outputs two clock edge signals 1.2 shown in FIG. 3 (3) and (4). To explain further, PEG 4 introduces a reference clock, and uses, for example, the rising edge of this reference clock as a reference time, and sets a preprogrammed delay time TI,
After T2 (see Figure 3), two clock edge signals 1
．． 2.

Reference numeral 6 denotes an RS flip-flop (hereinafter simply referred to as R8FF 6), into which clock edge signal 1 is introduced into a set terminal and clock edge signal 2 is introduced into a reset terminal. Therefore, when clock edge signal 1 becomes "old G)l", its output Q becomes "HIGH", and clock edge signal 2
When becomes "HIGH", its output becomes "10-".

That is, the generation time difference between the two clock edge signals 1.2 (
'T2-TI) (see Figure 3 ■). Note that the pulse width of the operation clock signal in Figure 3 (■) output from R3FF 6 and the reference time ( The delay time from C1, C2, . . . ) in FIG. 3 can be controlled by PEG 4.

Gate 7 is based on the pattern data in Figure 3 (1) and Figure 3 ■
Since the logical product with the operation clock is calculated, the waveform shown in FIG. 3 (9) is output.Such a signal is generally called the RZ scratch signal Return Zero.
This RZ flaw signal pattern data is "old GH" and is a signal that goes to the "HIGH" level only during the edge period of clock edge signals 1 and 2 (that is, the pulse width of the operating clock). The RZ flaw signal can be made into various formats by changing the pattern data and operation clock of FIG. 3(1).

8 is a D-type flip-flop (hereinafter simply referred to as DFF 8), which operates on the edge (rising edge in the case of Figure 4) of the operating clock output from the Q terminal of R5FF 6, and when this edge occurs, The state of the D terminal (pattern data in FIG. 3) is output to the Q terminal. Therefore DFF
A waveform shown in FIG. 3 (6) is obtained from the Q terminal of 8. Such a signal is generally referred to as an NRZ signal (Won
NR21 (Return 2ero) is a signal that changes to "HIGH" or "tot+" of pattern data at the rising edge of the operation clock. Similarly to the RZ flaw signal, the NRZ signal can be made into various formats by changing the format of the pattern data and operation clock shown in FIG. 3(1).

As described above, the circuit of FIG.
), and the NRZ signal shown in FIG. 3 (6) can be output from the mouth FF 8. This R7 signal and NR? The format of both signals can be set □ by the pattern data □ written in the memory 3 and the clock edge signal 1.2 from PEG J.

Since the circuit forming the RZ flaw signal HRZ signal is affected, the delay time of the RZ flaw signal NRZ signal also differs from the reference time. The seven RZ signals to be explained are obtained via the gate 7 into which pattern data and operation clocks are introduced, while the NRZ signal is obtained via the DFF 8. OfB is composed of a plurality of gate elements, so the NR signal passing through [1, FF 8] is connected to gate 7.
The delay is larger than that of the R2 signal that passes through one DFF, so in order to absorb this delay time difference, delay elements 9 and 10 are provided at the output ends of the gate 7 and the DFF 8 to adjust the timing.

Then, the RZ flaw signal and NRZ signal whose timing has been adjusted to be outputted from the delay elements 9 and 10 are selected by the selector 11 and taken out as output. A control signal RZ/NRZ for determining which signal is selected by the selector 11 is selected from a controller (not shown).

<Problem that the invention seeks to solve> Conventional circuits like the one above have two problems.

■ The pulse waveform of the RZ flaw signal NR2 signal passing through the delay element 7.10 causes waveform distortion, and the rise time and fall time are not the same, resulting in a change in pulse width. There is a problem that the pulse width cannot be obtained.

Add explanation. The output stage of gate 7 and DFF g is the sixth
As shown in the figure, it has two transistors. One transistor is for supplying current 11, and the other is for drawing t-current 12.6 Normally, this current 11.12 has different values, so a pulse signal as shown in Fig. 7 (1) is connected to the coil and capacitor. When added to the delay element 9.10 composed of
The signal passing through this delay element 9゜10 is shown in Fig. 7 (2).
Since the rising slope a and the falling slope are different, the pulse width changes.

■ The circuit in Figure 4 is an RZ signal with a narrow pulse width, NRZ
In producing the signal, there are limitations as explained in FIG. The minimum pulse width of the RZ signal and NRZ signal is determined by the minimum pulse width of the operating clock (as is clear from C and (5) in Fig. 3). Fig. 5 shows the operation in which the operating clock is generated by R8FF6. FIG.

R3FF 6 (The RSS pre-lag flop operates on the level of the signal applied to the set terminal and the reset terminal. That is, the RS flip-flop operates at the set terminal.

If the signal applied to the reset terminal is an extremely narrow pulse width signal, it cannot operate. Therefore, commercially available RS flip-flops have a standardized minimum input pulse width that can be operated. There is.

In addition, in order to switch an RS flip-flop from set operation to reset operation or vice versa, the signal applied to the set terminal and reset terminal must have a certain time interval. It is clearly stated.

α shown in FIG. 5 is this minimum time interval.

As is clear from FIG. 5, the minimum pulse width of the operating clock obtained by R5FF6 is Waiu=E+α, and R
Limited by the performance of the S flip 70g.

An object of the present invention is to provide a waveform formatter circuit that can prevent pulse width fluctuations and narrow the minimum output pulse width.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides means (3
), and means (4) for outputting first and second clock edge signals generated at an arbitrary delay time from the edge of the reference clock.
), and a first D-type flip-flop (hereinafter simply referred to as DFF) that inputs the pattern data to the D terminal and introduces the first clock edge signal to the clock terminal via the first delay element (21). A second clock edge signal is introduced into one terminal via the second delay element (22), and a control signal (R,?/NRZ) for controlling the opening/closing of this gate is introduced into the other terminal. The gate and the D terminal are connected to "HIGH", the output of the gate is introduced to the clock terminal, the Q terminal is connected to the reset terminal of the first DFF, and the own reset terminal is connected to the Q terminal of the first DFF. The second DFF is connected to the second DFF.

Effect> In the present invention, the operation clock explained in FIG. 4 is not created,
The clock edge signal of the direct cylinder 1 generates a rising pulse, and the second clock edge signal generates a falling pulse. Therefore, since it is not affected by the minimum operating pulse width of the RS flip-flop (E+α in FIG. 5), a signal with a shorter pulse width than the conventional one can be obtained.

In addition, the clock edge signal is adjusted by a delay element, and this timing-adjusted clock edge signal (the pulse width may vary) is applied to the clock terminal of the D-type flip-flop that operates as an edge. The pulse width does not fluctuate; in other words, the pulse width does not fluctuate because it operates in synchronization with only one edge (for example, the rising edge) of the clock edge signal whose timing has been adjusted. The present invention will be described in detail.

FIG. 1 is a diagram showing an embodiment of the waveform formatter circuit according to the present invention, and FIG. 2 is a time chart of the circuit shown in FIG.

In FIG. 1, component numbers 1 to 4 are the same as those explained in FIG. 4, so explanations of their operations will be omitted. Note that the components numbered 1 to 4 are not limited to the configuration shown in FIG. and the first and second signals that occur at an arbitrary delay time from the edge of the reference clock.
It is only necessary to include a means for outputting a clock edge signal of.

Reference numerals 21 and 22 are delay elements, which are composed of, for example, an inductance and a capacitor. Delay element 21
delays clock edge signal 1 output from PEG 4, and delay element 22 delays clock edge signal 2.

A first DFF 23 inputs pattern data from the memory 3 to a D terminal, and introduces a clock edge signal 1 to a clock terminal via a delay element 21.

A pulse train signal having the desired format is obtained from this Q terminal.

A gate 24 performs, for example, an AND operation.

This gate 24 introduces the clock edge signal 2 through the delay element 22 into one terminal, and into the other terminal a control signal (RZ/NRZ) for controlling opening/closing of this gate. This control signal is similar to the signal applied to the selector in FIG. 4, and is applied from a controller (not shown).

25 is a second DFF, the D terminal is connected to "HIGH", the output of the gate 24 is introduced to the clock terminal, and the Q
The terminal is connected to the reset terminal of the first DFF 23, and its own reset terminal is connected to the Q@ child of the first DFF 24.

The operation of the circuit shown in FIG. 1 constructed as above will be explained with reference to FIG.

(A) The operation NR2 signal that outputs the NRZ signal is a signal that changes to “HIGH” or “0” of the pattern data at the rising edge of clock edge signal 1 (operation clock in FIG. 4) as described. It is. In this case, the control signal R applied to the gate 24
This gate 24 is closed with Z/NRZ set to "[O12" (the output of the gate 24 is locked to "toIA"), and the timing-adjusted clock edge signal 2 coming from the delay element 22 is not allowed to pass through.

Therefore, the DFF 25 does not operate, and only the DFF 23 receives the pattern data applied from the memory 3 (see Figure 2 (1)) and the clock signal 1 applied via the delay element 21 (see Figure 2). Operate. DFF
23 is the clock edge signal 1 applied to the clock terminal
Since the pattern data applied to the D terminal at one rising edge of is outputted, the NRZ signal shown in FIG. 2 (5) is obtained from the Q terminal of the DFF 23.

Here, clock edge signal 1 output from PEG J
Since the signal passes through the delay element 21, the pulse width that has passed through the delay element 21 is different from the pulse width of the output signal of the PEG 4 for the same reason as explained in FIGS. 6 and 17. However, the pulse @t1 of the NRZ signal obtained by the circuit in Figure 1
(See FIG. 2 (5)) is as designed. In this case, the design (setting of PEG4) only needs to specify the rising time of the clock edge signal 1, and the period t1 is NR
This is the pulse width of the Z signal and is not affected by the delay element 21. The reason is that the pulse width of the clock edge signal 1 is
This is because the pulse width of the R2 signal is not determined, but the DFF 23 changes in synchronization with one edge (rising edge in FIG. 2) of the clock edge signal 1. That is, if we focus on only the rising edges, they are always delayed by the same amount of delay in the delay element 21. Note that the timing of the clock edge signal 1 applied to F23 can be adjusted by using the delay element 21.
The rise and fall timings of the NRZ signal can be adjusted by this delay element 21'.

(B) Operation to output RZ double signal RZ double signal, as described, pattern data is “HIGH”
” and is at the “old Gtl” level only during the edge period of clock edge signals 1 and 2.

When outputting this signal, the control signal RZ/NRZ applied to the gate 24 is set to "HIGH" to open the gate 24. That is, the clock edge signal 2 of the PEG 4 passes through the gate 24 via the delay element 22 and is applied to the clock terminal of the DFF 25.

First, when the clock edge signal 1 rises as shown in FIG. 2 (2), the pattern data becomes "HI" as shown in FIG. 2 (1).
GH", the Q terminal of DFF 23 is
) becomes “HIGH”.

Next, when clock edge signal 2 rises, Figure 2 (3)
), this "HIGH" level is applied via gate 24 to the clock terminal of DFF 25. DFF
Since the D terminal of 25 is “HIGH”, the Q output is “HIGH”.
GH” (see Figure 2 (4)), this Q output is DF
Since it is added to the reset terminal of F23, DFF2
The Q output of No. 3 becomes "[0-"] (see FIG. 2 (6)).

Therefore, the Q output of the DFF 23 becomes "HIGH", and this "HIGH" is applied to the reset terminal of the DFF 25, so the Q output of the DFF 25 becomes "[0-"] in preparation for the input of the next signal (the (See Figure 2 (4)).

By the above operation, R of the pulse width t2 shown in FIG. 2 (6) is
1 signal is obtained. To summarize, the rising edge of the RZ multiplication signal operates on the rising edge of clock edge signal 1 applied to DFF 23, and the falling edge operates on the rising edge of clock edge signal 2 applied to DFF 23.
This is realized by a DFF 25 that operates on the rising edge of .

Here, the RZ multiplied signal obtained by the circuit shown in Fig. 1 is shown in Fig. 2 (6).
) and clock edge signals 1 and 2 (Fig. 2 (2)).

(3)) and the Q output of the mouth FF 25 (FIG. 2 (4)) will be explained.

The time from when the clock edge signal 1 rises to when the RZ times signal rises is TPo. 'rp o is the propagation delay time passing through one stage of flip-flops, and is usually 10
It is about S~2 ns. In this case, clock edge signal 1
is applied to the clock terminal of the DFF 23, so the DFF 23 is operating due to the edge operation.

Next, after clock edge signal 2 rises, DFF 2
The time until the Q output of No. 5 rises is also TPo.゛Then, from the rising edge of the Q output of DFF 25, DFF 23
The time until the Q output falls (RZ times signal falls) is also TPo. The operation of the DFF 23 at this time is based on the signal applied to the reset terminal, so it is a level operation, but since the previous time the DFF 23 operated at a level was at the rising edge before the clock edge signal 2, it takes time. Since the time has elapsed, 0FF23 operates after time TPo after the 0FFI25 signal is applied to the reset terminal (
fall).

As mentioned above, in the circuit of Figure 1, the clock edge signal 1.2
Since the RZ multiplication signal pulse width can be determined only by the rising edge of , the two clock edge signals 1.2 can be placed close enough that their "HIGH" periods overlap. Therefore, a signal with a narrower pulse width than the conventional example shown in FIG. 4 can be obtained.

Note that the reason why the pulse width of R1@ is not affected by the delay elements 21 and 22 and is as set is explained in the NIIZ signal, so the explanation will be omitted.

Effects of the Present Invention> As described above, according to the present invention, the following effects can be obtained.

(2) Since a delay element for timing adjustment is not included in the output stage of the DFF 23, which is the format output section, the pulse width of the output RZ multiplied signal and NRZ signal is maintained at the set value.

(2) Conventionally, the pulse width of the clock edge signal determined the minimum pulse width wti of the R7 signal, so it was necessary to use a clock edge signal with a very narrow pulse width.

Here, there is a problem that a signal with a narrow pulse cannot pass through the delay element if the band of the delay element is insufficient. However, in the present invention, since the RZ multiplication signal pulse width can be determined by the time difference between the rising edges of two clock edge signals, the pulse width of the clock edge signal can be widened. That is,
A signal with a duty of 50% can be used as the clock edge signal. As a result, an expensive broadband delay element for timing adjustment is not required.

(2) Since the minimum pulse width obtained in the present invention does not depend on the pulse width of the clock edge signal, it is possible to obtain a signal with a narrower pulse width than in the conventional example.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the waveform formatter circuit according to the present invention, FIG. 2 is a time chart of the circuit in FIG. 1, and FIG.
4 is a time chart of the circuit, FIG. 4 is a diagram showing a conventional example, and FIGS. 5 to 7 are diagrams for explaining the conventional example. 3...Memari, 4...PEG, 21.22...
Delay element, 23°25...DFF, 24...gate. +-~ 11!

Claims (1)

[Claims] Means (3) for generating pattern data consisting of any combination of "HIGH" and "LOW" at the cycle of the reference clock.
and means (4) for outputting first and second clock edge signals generated at an arbitrary delay time from the edge of the reference clock.
), and a first D-type flip-flop (hereinafter simply referred to as DFF) that inputs the pattern data to the D terminal and introduces the first clock edge signal to the clock terminal via the first delay element (21). A second clock edge signal is introduced into one terminal via the second delay element (22), and a control signal (RZ/@NRZ@) for controlling opening/closing of this gate is introduced into the other terminal. The gate and the D terminal are connected to “HIGH”, the output of the gate is introduced to the clock terminal, the Q terminal is connected to the reset terminal of the first DFF, and its own reset terminal is connected to the @Q of the first DFF. A waveform formatter circuit comprising a second DFF connected to the @ terminal.