JPH03186776A - Waveform formatting circuit - Google Patents

Abstract

PURPOSE:To increase the kinds of pulse train signals for a waveform circuit used for an LSI test, etc., and to widen the selecting range by controlling three clock edge signals coming from a PEG by a control signal. CONSTITUTION:Pattern data are generated by a reference clock 1 at the cycle of reference clock, and the 1st-3rd clock edge signals generating from the edges of reference clock 1 with arbitrary delay times are outputted by the PEG 4. By the 1st-4th AND gates 131-134, the opening/closing of gate are controlled with the 1st-3rd edge signals and control signal RC or RZ/-NRZ respectively. Next, outputs of the 1st and 2nd OR gates 141-142 having the inputs which are the outputs of the 1st-4th AND gate 131-134, are inputted respectively to the 1st FF 15 and the 2nd FF 16 wherein the terminal D is connected to HIGH, the output of 2nd OR gate 142 is introduced to the clock terminal, the terminal Q is connected to a reset terminal of the 1st FF 15 and the own terminal is connected to a terminal Q of the 1st FF 15.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a pulse train signal necessary for LSI testing in the field of, for example, an LSI tester, and allows the generation period and pulse width of the pulse to be set. This relates to a waveform formatter circuit.

<Prior Art> FIG. 3 is a circuit diagram of a conventional waveform formatter circuit, and FIG. 4 is a time chart of this circuit.

In the figure, 1 is a reference clock generator that generates a reference clock, 2 is a program counter (hereinafter simply referred to as PC) that counts this reference clock, and 3 is a memory that inputs the count value of PC2 as an address signal. 0, where pattern data is written, for example, address AD1 of memory 3. AD2, AD3. AD4...
1', "O", 1", "O"... is written, the reference clock C1, C2, C3, C4
... occurs, and the output of PC, 2 is "1", '0'1"
If it changes to "O"..., the pattern data shown in FIG. 4 (1) is output from the memory 3.Here, 1" is "H".
IGH "0" means "1014".

4 is a programmable edge generator (hereinafter simply P)
EG) and outputs two clock edge signals shown in FIG. 4 (3) and (4).

This PEG 4 has reference clocks C1, C2, C3,
The example of . . . is based on a preprogrammed delay time T1. After T2, 2
It outputs two clock edge signals 1°2.

5 is an RS flip-flop (hereinafter simply referred to as R3FF), to which clock edge signal 1 is applied to a set terminal and clock edge signal 2 is applied to a reset terminal, respectively. This R8FF 5 has "1110H" on the set terminal
When is input, HIGH' is output from Q terminal,
When ``HIGH'' is input to the reset terminal, ``LOW'' is output from the Q terminal. Therefore, the clock edge signals 1.2 shown in Figure 4 (3) and (4). An operating clock (see Fig. 4 (2)) with a pulse width equal to the difference in rise time (T2-11) is output from the Q terminal.Here, the reference clocks C1, C2, C3,
The delay time TI, T2 from ... can be controlled by P[G4.

6 is an ND gate which receives the pattern data from the memory 3 and the output of R5FF5, and outputs the logical product of the pattern data of FIG. 4(1) and the operation clock of FIG. 4(2). Such a signal is generally called RZ multiplied signal Retur.
n Zero) and the pattern data is 71110H.
This is a signal that goes to a HIGH level by the pulse width of the operating clock.

7 is a D-type flip-frog (hereinafter simply referred to as DFF), the pattern data from the memory 3 is input to the D terminal, and the output from the terminal of R3FF 5 is introduced to the clock terminal. At this time, DFF 7 operates at the edge of the operating clock output from the Q terminal of R8FF 5,
The state of the D terminal when this edge occurs is output to the Q terminal (see FIG. 4 (6)).

Such a signal is generally called an NRZ signal (Man Retu
rn2ero), the NRZ signal is the “HIG” signal of the pattern data at the rising edge of the operating clock.
This is a signal that changes to H" or 10-'. This NRZ
The signals are also the pattern data and operation clock σ shown in Figure 4 (1).
) Various formats can be created by changing the form.

At this time, the R7 signal is output from the AND gate 6, and the NR7 signal is output from 0FF7, but since the DFF 7 has a plurality of gates inside, the delay time of the output signal is longer than that of the gate 6. Here, the timing of the signal is adjusted by delay elements 81 and 82.

9 is a selector, which selects RZ by a control signal (RZ√NRZ).
Either of the double signal IIRZ signals is selected and output.

When performing waveform formatter using such a waveform formatter circuit, there were the following problems (details are specified in Japanese Patent Application No. 01-025238).■ Delay element 81.
The pulse waveform of the RZ flaw signal NR1 signal that passes through 82 causes waveform distortion, and the rise time and fall time are not the same, and the pulse width changes, causing the problem that the pulse width as set is not obtained. .

■ The operating clock output from the Q terminal of R5FF 5 is obtained from the rise time difference (T2 - Tl) between clock edge 1 and clock edge 2 (see Figure 4).
2) to (4)), the RS flip-flop prohibits input of "HIGH" level to both the set terminal and the reset terminal, so the time difference (T2-TI
) must always be larger than the pulse width of the clock edge, that is, the pulse width of the operating clock obtained from R8FF 5 cannot be smaller than the pulse width of the clock edge, which limits the formatted pulse width. There is a problem with this.

In order to solve such problems, the applicant filed the patent application No.
-025238 has been proposed as an invention.

FIG. 5 is a circuit diagram of the waveform formatter circuit proposed in Japanese Patent Application No. 01-025238, and FIG. 6 is a time chart of this circuit. In FIG. 0, the explanation of the same components as those in FIG. 3 will be omitted. In FIG. Delay element 84 delays clock edge signal 2 while delaying signal 1 .

10 is a D-type flip 70 tube, which inputs the pattern data from the memory 3 to the D terminal, and introduces the clock edge signal 1 from the PEG 4 to the clock terminal via the delay element 83. A pulse waveform having the required format is output from this Q terminal.

11 is a clock edge signal 2 from PEG 4 via a delay element 84, and a control signal (R2) that controls this gate.
/NR2) is an AND gate. This system
Signals are applied from a controller not shown.

12 is a D type flip-flop, the D terminal is connected to "old G", the output of AND gate 11 is introduced to the clock terminal, the Q terminal is connected to the reset terminal of 0FFIO, and its own reset terminal is connected to the Q of 0FFIO. connected to the terminal.

Next, the operation and effects of the invention disclosed in Japanese Patent Application No. 01-025238 will be explained.

First, when outputting a waveform based on the NRZ signal (Fig. 6 (5)), the control signal (R2/NR2) is set to 10-" and the AND gate 11 is closed. Therefore, the DFF 12 is OF
F, and the output from 0FFIO is the pattern data (
(see Figure 6 (1)) and clock edge signal 1 (see Figure 6 (1)) and clock edge signal 1 (see Figure 6 (1)).
2)), that is, the delay element 8
Since the pattern data is output at the rising edge of the clock edge signal 1 via 0FFIO, the output from the Q terminal of 0FFIO becomes as shown in FIG. 6 (5).

Here, since the clock edge signal 1 introduced into the clock terminal of DFrlO passes through the delay element 83, it has a different pulse width from the clock edge signal before passing through the delay element 83. However, the pulse width tl of the NR7 signal obtained by the circuit in Figure 5 (see Figure 6 (5)) is determined only by the rising edge of clock edge signal 1, and its period is the pulse width of the operating clock, so the delay It is not affected by the element 83.

Therefore, the delay element 83 uses the reference clocks CI, C2, C3.
Since only the delay time from ... is determined, the pulse width as set can be obtained.

Next, when outputting the waveform based on the RZ flaw signal (Figure 4 (6)), change the control signal (R2/NR2) to ``+11GII''.
” to open the AND gate 11. That is, the tally query signal 2 of PEG 4 is outputted via the delay element 84 to A.
The signal passes through the ND gate 11 and is applied to the tallock terminal of the DFF 12.

When the clock edge signal 1 rises as shown in Figure 6 (2), the pattern data will be changed as shown in Figure 6 (1).
The old G is ``, so the output from the Q terminal of DfFlo is ``
HIGH”.

Here, when the clock edge signal 2 rises as shown in FIG. 6(3), the clock edge signal 2 is connected to the AND gate 1.
1 and is input to the clock terminal of the DFF 12.

At this time, since the D terminal of the DFF12 is always at the "HIGH" level, the "IIIGH" level is output from the Qf terminal. Since this signal is input to the reset terminal of 0FFIO, the Q terminal of 0FFIO immediately becomes "10- ” level (see Figure 6 (6)) At the same time, 0FFIO
Q#1 child outputs “HIGH” level and DFF1
Input to the reset terminal of 2.

Since the reset signal becomes “HIGH”, it immediately turns to 0FF.
The Q terminal of No. 12 outputs the "10+4" level (see Figure 6 (4)). As a result, a pulse train signal having the format of pulse @t2 as shown in Figure 6 (6) can be obtained. .

At this time, the pulse width of the RZ output signal is determined only by the time difference between the rises of the tally edge signal 1 and the clock edge signal 2, so there is no limit to the pulse width of the obtained pulse train signal, and by adjusting the delay elements 83 and 84. Signals with any pulse width can be obtained.

<Problem A to be solved by the invention> In the invention proposal of this patent application No. 01-025238, RZ
Two types of waveform formats could be obtained using the two control signals, the double signal and the NF12 signal.

The present invention utilizes the advantages of the invention disclosed in Japanese Patent Application No. 01-025238, improves the invention, increases the types of pulse train signals used in LSI testing, etc., and provides a waveform formatter circuit that can widen the range of selection. The purpose is to provide

<Means for Solving the Problems> The present invention provides a waveform formatter circuit that generates a pulse train signal in which the pulse generation period and pulse width can be set. means for outputting three clock edge signals, first, second, and third, generated at an arbitrary delay time from the edge of the reference clock; and means for outputting the pattern data via an inverter. , a third clock edge signal via a delay element, and a control signal (RC) for controlling opening/closing of this gate.
a D gate; a second NO gate which receives as input the pattern data, a third clock edge signal via a delay element, and a control signal (112√NRZ) for controlling opening/closing of this gate; a third AND gate that receives the pattern data, the second clock edge signal via the delay element, and the control signal (RC); 2 clock edge signal and the control signal (R
C); a first OR gate that receives as inputs the output of the first AND gate; and the output of the fourth AND gate;
A second OR gate inputs the output of the AND gate and the output of the third AND gate, the pattern data is input to the D terminal, and the first clock edge signal is clocked through a delay element. into the terminal, and the first O
A first flip-flop which takes the output of the R gate as the input of the set terminal, and Dr@-j- are connected to °IIIGH"4; l:, and the output of the second OR gate is introduced to the clock terminal, and the Q
a second flip-flop whose terminal is connected to the reset terminal of the first flip-flop, and whose reset terminal is connected to the Q terminal of the first flip-flop; It is.

<Operation> According to the present invention, three types of waveform formatters can be created by controlling the pattern data generated in the cycle of the reference clock with three clock edge signals generated at arbitrary delay times from the edge of the reference clock. get. At this time, the clock edge signal is controlled by (RZ√N
This is done using two types of signals: RZI and (RC).

<Actual example> Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram of an embodiment of a waveform formatter circuit according to the present invention. FIG. 2 is a diagram showing a time chart of this circuit. Note that the same components as in FIGS. 3 and 5 are indicated by 85 in FIG.
, 86 and 87 are delay elements connected to the output line of the clock edge signal output from PEG4 (<Prior art>
(Explained in) Yes.

Reference numeral 131 indicates pattern data from the memory 3 via the inverter, a third clock edge signal (hereinafter referred to as clock edge signal 3) via the delay element 87, and a control signal (RC) for controlling the opening/closing of this gate. An AND gate 132 receives the pattern data from the memory 3 and the clock edge signal 3 via the delay element 87;
Control signal (RZ√NRZ) that controls the opening and closing of this gate
The ND gate 133 receives the pattern data from the memory 3, the clock edge signal 2 via the delay element 86, and the control signal fR that controls the opening/closing of this gate.
c) and NO gate 134 which receives the pattern data from the memory 3 via the inverter and the delay element 8.
This is a NO gate that receives as input the clock edge signal 2 via the gate 6 and a control signal (RC) for controlling the opening/closing of this gate.

141 is the output of AND gate 131 and AND gate 1
142 is an OR gate that receives the output of AND gate 132 and the output of ^ND gate 133 as input.

15 inputs pattern data to the D terminal, and a delay element 85
16 is a D-type flip-flop (hereinafter simply referred to as 0R8FF) which inputs the clock edge signal 1 via the clock terminal to the clock terminal, inputs the output of the OR gate 141 to the set terminal, and outputs the waveform format from the Q terminal. terminal is connected to "IIIGH", the output of the OR gate 142 is input to the clock terminal -, the Q terminal is input to the reset terminal of the DRSFF 15, and its own reset terminal is connected to the DRSFF 15.
It is a D-type flip-flop connected to the Q terminal of 15.

Next, the operation of the circuit of the present invention will be explained using FIGS. 1 and 2. To obtain a waveform format using the R2 signal and NR2 signal, set the control signal (RC) to "[014"] and switch the control signal (RZ/NnZ) to "HIGH" or "LO14" and start from DRSFF 15. Get waveform format. At this time, since the control signal (RC) is "1014", AND gates 131 and 133
134 and the OR gate 141 are turned off, and the clock edge signal 2 is not affected at all.

Therefore, the circuit has the same configuration as the circuit shown in FIG. 5, and the obtained waveform formats are also similar to those shown in FIG. 6 (5) and (6), so that FIG. 2 (5) and (6) are obtained. The operation at the time of outputting the waveform format obtained by the RZ signal and the waveform format obtained by the NRZ signal has been explained in the conventional example, and will therefore be omitted.

When obtaining a waveform format using an RC signal, set the control signal (RC) to "HIGH" and set the control signal (RZ√NR
Z) to "HIGH". Here, Fig. 2 (2)
, (3).

Delay elements 86, 85.8 from PEG 4 as in (4)
The operation when the clock edge signal 2, the clock edge signal 1, and the clock edge signal 3 rise in this order via the clock edge signal 7 will be explained.

When the pattern data output from the memory 3 at the timing of the reference clock is "1", the NO gate 131 and the ND gate 134 having an inverter are turned OFF. Here, when clock edge signal 2 rises, ^
Only the ND gate 133 is turned on, and the OR gate 142
becomes ON. As a result, the tarok terminal of 0FF16
HIGH" is input, and the HIGH level is output from the Q terminal. Here, the DR5FF15 is reset, so the Q terminal of the DRSFF 15 outputs the "HIGH" level. (Fig. 2 (7)-■) When the clock edge signal 1 rises as shown in Fig. 2 (3), that signal is input as is to the clock terminal of the DRSFF 15, and a "HIGH" level is output from the Q terminal. Ru. (Figure 2 (7)
)-■) When the clock edge signal 3 rises as shown in FIG. 2 (4), the AND gate 132 turns on and the OR
Gate 142 is also turned on. As a result, the "HIGH" level is again input to the clock terminal of the DFF 16, and the "old ridge" level is output from the Q terminal. Therefore, 0R3rF
15 is reset again, and a "[0-"] level is output from the Q terminal. At the same time, a "HIGH" level is output from the Q terminal and the OFF 16 is reset. (Figure 7 (7--) Next, when the pattern signal is "0", this time the AND gate 1
32 and AND gate 133 are turned off. At this time, when clock edge signal 2 rises in the same cycle,
^ND gate 134 is turned on, and OR gate 141 is turned on. As a result, DR8FF 15 is set and outputs a 'HIGH' level from the Q terminal. (Second
Figure (7)-■) Similarly, when clock edge signal 1 rises, DR3r
F15 is the content of the pattern data "10-" level
Output from the terminal. ((7)-■ in FIG. 2) When the clock edge signal 3 rises, the ND gate 131 is turned on, and the OR gate 141 is turned on. As a result, D again
R8FF 15 is set and “HIGH” from Q terminal
Output the level. (FIG. 2 (7)-■) Therefore, the time chart in one embodiment of the present invention is as shown in FIG. 2 (7).

As described above, in the present invention, by recycling the rise of these three clock edge signals, as shown in FIG. 2 (7).
You can get waveform formats like .

In the case of the present invention, as in the conventional example, since the waveform format is determined only by the rising edge of the clock edge signal, there is no restriction on the pulse width of the output waveform.

<Effects of the Invention> As explained in detail above, in the present invention, PEG
The three clock edge signals according to 4 are converted into a control signal (R
2/N112) and (RC) to selectively utilize the new waveform format (Fig.
)) can be obtained.

Similar to the invention proposed in Japanese Patent Application No. 01-025238, since the rise and fall of the waveform format is controlled only by the rise of the clock edge, there is no restriction on the pulse width of the clock edge, and the generated waveform format is There is no longer any restriction on pulse width, and pulse signals with various widths can be created.

In addition, since the RC format is gated at the bottom of the tank, format switching (ON T
)IE FLY) becomes possible.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of a waveform formatter circuit according to the present invention, FIG. 2 is a time chart of this circuit, and FIG. 3 is a circuit diagram of a conventional waveform formatter circuit.
The figure is a time chart of the circuit, FIG. 5 is a circuit configuration diagram of a waveform formatter circuit improved from the circuit of FIG. 3, and FIG. 6 is a time chart of the circuit shown in FIG. 1...Reference clock generator 2...Program counter 3...Memory 4...Programmable edge generators 85-87
...Delay element 131...First AND gate 132...Second AND gate 133...Third AND gate 134...Fourth NO gate 141...First OR Gate 142...Second OR gate 15...First flip-flop 16...Second flip-flop

Claims (1)

[Scope of Claims] In a waveform formatter circuit that generates a pulse train signal whose pulse generation period and pulse width can be set, means for generating pattern data consisting of an arbitrary combination of "HIGH" and "LOW" at the cycle of a reference clock. and means for outputting three clock edge signals, first, second, and third, generated at arbitrary delay times from the edge of the reference clock; and means for outputting the pattern data via an inverter and the third clock edge signal via a delay element. A first AN that receives as input the clock edge signal of
a D gate, a second AND gate which receives as input the pattern data, a third clock edge signal via a delay element, and a control signal (RZ√NRZ) for controlling opening/closing of this gate; and the pattern. a third AND gate that receives the data, a second clock edge signal via a delay element, and the control signal (RC); and the control signal (R
C); a first OR gate that receives as inputs the output of the first AND gate; and the output of the fourth AND gate;
A second OR gate inputs the output of the AND gate and the output of the third AND gate, and inputs the pattern data to the D terminal, and clocks the first clock edge signal through a delay element. into the terminal, and the first O
A first flip-flop which takes the output of the R gate as the input of the set terminal, the D terminal is connected to "HIGH", the output of the second OR gate is introduced into the clock terminal, and the Q terminal is connected to the first flip-flop. A waveform formatter circuit comprising: a second flip-flop connected to a reset terminal of the flip-flop, and having its own reset terminal connected to the @Q@ terminal of the first flip-flop.