JPH02207337A - Data processing system - Google Patents

Abstract

PURPOSE:To speed up the operation of a system including a low-speed access memory by replacing the operation of the low-speed access memory with the operation of a high-speed access memory when a processor is operated at high speed. CONSTITUTION:First, a clock switching control circuit 6 supplies a clock signals CLK2, which are obtained by internally dividing a system clock signal CLKS into two, as an operating clock signal CK to a microprocessor 1. The microprocessor 1 executes relatively a low-speed control operation in synchronization with the clock signals CLK2, reads out an operating system held by a low-speed access memory 2, and writes it to a high-speed access memory 3. Next, the microprocessor 1 executes the control operation in synchronization with the system clock signal CLKS. Thus the operation of the low-speed access memory 2 is replaced with operation of the high-speed access memory 3, and the operation of the system including the low-speed access memory 2 can be speed up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system including a low-speed access memory, and relates to a technique that is effective when applied to, for example, an emulator or a microprocessor board.

[Prior art]

The emulator includes a microprocessor equivalent to the target microprocessor, and controls the target system on behalf of the user by causing the microprocessor to execute a user program to be software debugged. At this time, the contents of the user program can be arbitrarily changed through a host system such as a system development device, the control state of the program can be traced, and the trace results can be checked at predetermined breakpoints while the target system is being updated. Assist with software debugging.

By the way, mask ROM (ROM for storing programs such as read-only memo) is used mainly in the central processing unit.
When emulating a target system using a so-called single-chip microcomputer that has M and the like mounted on a single semiconductor substrate, such a single-chip microcomputer may not open its internal bus to the outside, so it is necessary to transmit internal bus information. An evaluation-only chip is used that is capable of being output to the outside or does not have a ROM for storing programs. At this time, user programs necessary for operation are downloaded from the system development device to a substitute memory in the emulator, but for the operating system and the like, existing EPROM or EEPROM chips can be installed in the emulator and used.

An example of a document describing emulators is "Emulator Unit H8100EUAOIH User's Manual for Compact Microcomputer HMC8100 Series" published by Hitachi, Ltd. in September 1986.

[Problem to be solved by the invention]

However, EPROM (Electrically Programmable Read Only Memory) has a slower access speed than RAM (Random Access Memory).
If emulation is performed by directly accessing a chip or the like, it will not be possible to perform system debugging while satisfying the operating speed required of the target system. Therefore, consideration has been given to transferring necessary information such as the operating system from low-speed access memory to high-speed access memory such as RAM.

Even when such data transfer is performed in advance, the maximum access speeds of both memories are different to begin with.1 For example, when a processor that controls access to these memories performs synchronous bus control, such a processor does not have a wait function. In this case, or when the wait function cannot be used, it is necessary to transfer data by adjusting the operating speed of the processor at that time to the operating speed of the memory, which has a low access speed. Therefore, after data transfer is completed, it is necessary to switch the operating clock signal of the processor to a higher operating frequency according to the maximum operating speed of the high-speed access memory, but when switching the operating frequency,
Conventionally, no consideration was given to this, and the processor had to be reset and reinitialized.

An object of the present invention is to provide a data processing system that can easily increase the operating speed of a system that includes low-speed access memory.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a system including a low-speed access memory, the high-speed access memory is placed at an address that overlaps with the high-speed access memory, and a clock switching means is provided that can synchronize clock signals with different frequencies and switch and supply the clock signals to the processor. According to the selection state of the clock signal frequency by the means, it is determined whether to access the low-speed access memory or the high-speed access memory. When performing data processing using the information held in the low-speed access memory, the information in the low-speed access memory is transferred to the high-speed access memory in advance, and then the clock signal is switched to a high frequency to control the low-speed access memory. The system operates with fast access memory instead.

[For production]

According to the above-described means, when the processor operates at high speed, the operation of the low-speed access memory is replaced with the operation of the high-speed access memory, thereby achieving an increase in the operating speed of a system including the low-speed access memory. At this time, the low-speed access memory and the high-speed access memory are mapped to overlapping addresses and their operations are selectively controlled, so it is extremely easy to replace the operation of the low-speed access memory with the operation of the high-speed access memory. Furthermore, since the clock frequencies for the processors are switched and controlled in synchronization, there is no need to reset the processors when switching the clock signals.

〔Example〕

FIG. 1 shows a part of a microprocessor board which is an embodiment of the present invention. The microprocessor board shown in the figure is configured by mounting necessary semiconductor integrated circuit chips and TTL (transistor-transistor-logic) circuits on a wiring board, and for example, operates in synchronization with a clock signal. Centered on the microprocessor 1, low-speed access memory 2 such as EPROM
Peripheral circuits such as a high-speed access memory 3 such as an SRAM (Static Random Access Memory) are commonly connected to an address bus 4 and a data bus 5. Although the low speed access memory 2 is not particularly limited,
The operating system of the microprocessor 1 and the like are stored.

Although the microprocessor board of this embodiment is not particularly limited, it is applicable to a single board computer constituting an emulator. This microprocessor board has a user interface 23
It is possible to connect to a desired target system 24 via a system interface 25, and to a host system 22 via a system interface 25. Microprocessor 1 included in this microprocessor board
Although not particularly limited, it has the same control function as a target processor (not shown) for originally controlling the target system 24, and controls the target system 24 on behalf of the user via the user interface 23 while executing a user program. At the same time, when execution of the user program is stopped, the system program is executed to control the inside of the microprocessor board. In addition to the user interface 23 and system interface 25, the address bus 4 and data bus 5 include:
Emulation memory 2 for acting as data memory and program memory in the target system 24
8. To monitor the control state etc. when the microprocessor 1 is executing the user program, and to break the execution operation (emulation operation) of the user program when the state reaches a preset state. A break control circuit 29, a real-time trace circuit 3o that sequentially traces and stores various information given to the address bus 4 and data bus 5 when the microprocessor 1 is executing a user program, and a real-time trace circuit 3o for the microprocessor 1 to operate the system. A system memory 31 and the like for storing system programs and data are coupled to each other. The low-speed access memory 2 and high-speed access memory 3 constitute part of the emulation memory 28, and the low-speed access memory 2 includes an operating system for executing user programs. When the microprocessor 1 executes a user program, the emulation memory 28 is placed in an address space defined by the user program. On the other hand, when the microprocessor 1 executes a system program, the system memory 31 is located in an address space defined by the system program. The user program downloaded from the emulation memory 28 can be transferred to the emulation memory 28 and vice versa, and the data obtained by the emulation operation can be transferred from the emulation memory 28 to the system memory 31.
The data necessary for the emulation operation is transferred to the emulation memory 28 by transferring the data to the emulation memory 28 or vice versa.

When the microprocessor 1 of this embodiment executes a user program and performs an emulation operation, it must perform control operations according to the operating system held in its low-speed access memory 2. Since the microprocessor 1 does not have a wait function that can extend the operation cycle by inserting a wait state into the microprocessor 1, when performing a control operation while directly accessing the low-speed access memory 2, the operating speed of the microprocessor 1 is lower than that of the low-speed access memory 2.
cannot exceed the maximum operating speed of

This embodiment is intended to eliminate such restrictions.

When the microprocessor 1 operates at high speed, the high speed access memory 3 is operated in place of the low speed access memory 2. That is, a high-speed access memory 3 is arranged at an address that overlaps with the low-speed access memory 2, and a clock switching control circuit 6 is provided to synchronize and control switching of the operating clock signal frequency of the microprocessor 1. A decoder 7 is provided for selectively controlling the operation of the low-speed access memory 2 or the high-speed access memory 3 according to the selected state of the clock signal frequency when accessing addresses redundantly assigned to the high-speed access memory 2 and the high-speed access memory 3. be.

The clock switching control circuit 6 selectively controls the operating clock signal GK to be applied to the microprocessor 1 to either the system clock signal CLKs or the clock signal CLK2 obtained by internally dividing the system clock signal CLKs by two, and also controls the operating clock signal GK to be applied to the microprocessor 1. The switching timing of the signal CK is controlled to be synchronized with the system clock signal CLKs.

Whether to select system clock signal CLKs or clock signal CLK2 is determined by clock selection information C output from clock selection register 8 such as a D-type latch circuit.
Determined by 3EL level. The clock selection information C3EL is set to the clock signal CLK2 due to its low level.
Its high level instructs the selection of the system clock signal CLKs. This clock selection information C3EL is initialized to low level by assertion of the reset signal RESET outputted from the microprocessor 1, and is also passed through the data bus 5 when the register selection signal R8 outputted from the decoder 7 is asserted. It can be arbitrarily rewritten according to data supplied from the microprocessor 1.

The clock switching control circuit 6 includes, for example, as shown in FIG. 2, a multiplexer composed of three Nant gates 10 to 12, and a synchronization circuit mainly composed of a JK type rough flip-flop circuit 13.

The set terminal S of the JK type rough flip-flop circuit 13 is pulled up to the power supply terminal Vdd and is always disabled, and the reset terminal R is supplied with the above-mentioned reset signal RESET. A system clock signal CLKs is supplied to a clock terminal CLK as a control terminal, and when this is changed to a low level, the state of the input terminals J, influences the outputs Q, Q. The input terminal K has a ground terminal Vss.
A low level is always applied to the input terminal J, and the output of the NOR gate 14 which outputs the clock signal CLK2 and the inverted level of the clock selection information C3EL is applied to the input terminal J. The output terminal Q is coupled to the input terminal of one of the Nant gates 10, which functions as an output gate for the clock signal CLK2, and the output terminal Q
is coupled to the input terminal of the other Nantes gate 11, which functions as the output gate of the gate.

When the clock selection information C3EL is at a low level, the input terminal J of the JK flip-flop circuit 13 is fixed at a low level, so that the JK flip-flop circuit 13 is reset to the initial state achieved by the reset signal RESET. maintain the condition. As a result, the output of the Nant gate 11 is always at a high level, so that the clock signal CLK2 is selected as the operating clock signal CK and supplied to the microprocessor 1.

As shown in FIG. 3, when the clock selection information C3EL is rewritten to a high level at time t, the input terminal J of the JK flip-flop circuit 13 receives the clock signal CLK.
2 is applied, and this signal is taken in in synchronization with the timing at which the system clock signal CLKs changes to low level.

Therefore, the JK flip-flop circuit 13 operates at time t.
2, which causes Nantes Gate 1
As a result, the output of 0 is always at a high level, and as a result, the system clock signal CLKs is selected as the operating clock signal CK and is supplied to the microprocessor 1.

In this way, the switching timing of the operating clock signal GK from the clock signal CLK2 to the system clock signal CLKs is synchronized with the change of the system clock signal CLKs to the low level in the low level phase of the clock signal CLK2, so that When switching the operating clock signal GK at time t2, the system clock signal CLK
A clock pulse that is abnormally short compared to the pulse width of s is not generated. Therefore, even if the system is not reset when switching the operating clock signal CK of the microprocessor 1, no malfunction will occur.

The decoder 7 has logic for determining whether to access the low-speed access memory 2 or the high-speed access memory 3 depending on the frequency selection state of the operating clock signal CK by the clock switching control circuit 6. For example, the decoder 7 is supplied with a read signal RD, a write signal WR, an address signal, and clock selection information C3EL output from the microprocessor 1, and the low-speed access memory 2 and high-speed access memory 3 are The operation mode shown in the table is adopted.

That is, when address signals other than those redundantly assigned to low-speed access memory 2 and high-speed access memory 3 are supplied, the operations of both memories 2 and 3 are not selected. If address signals that are redundantly assigned to low-speed access memory 2 and high-speed access memory 3 are output from microprocessor 1, either one of memory 2
, 3 are selected. For example, if the clock selection information C3EL is at a low level at this time, that is, if the clock signal CLK2 with a relatively lower frequency is selected as the operating clock signal GK, a memory read operation is instructed by the read signal RD. Then, the chip select signal C81 and the output enable signal OE enable the read operation of the low-speed access memory 2, and conversely, when the write signal WR instructs the memory write operation, the chip select signal C82 and the read/write signal R are activated. /W
This enables the write operation of the high-speed access memory 3. On the other hand, when the clock selection information C3EL is at a high level, that is, when the system clock signals C and LKs with a relatively higher frequency are selected as the operation clock signal CK, a memory read operation is instructed by the read signal RD. When the chip select signal C82 and lead signal are
A read operation of the high speed access memory 3 is enabled by the write signal R/W. Note that if a memory write operation is instructed by the write signal WR while the clock selection information C3EL is at a high level, the write operation of the high-speed access memory 3 is performed by the chip select signal C8 and the read/write signal R/W. You can also instruct them to do so, but you can also override the instructions for such actions.

Next, the operation of the above embodiment will be explained with reference to FIG.

When the microprocessor 1 is operated at a high speed exceeding the maximum operating speed of the low-speed access memory 2 in the emulation operation, the frequency of the system clock signal CLKs is set to a required high frequency.

At this time, the frequency of the clock signal CLK2, which has a frequency that is half that frequency, becomes a relatively low frequency that does not exceed the maximum operating speed of the low-speed access memory 2 when the microprocessor 1 operates in synchronization therewith.

As shown in FIG. 4, first, the microprocessor 1
is the reset signal RESE according to the system program.
T is asserted, clock selection information csEL is initialized to low level, and the JK flip-flop circuit 13 is
Initialize to reset state. Thereby, the clock switching control circuit 6 supplies the clock signal CL K 2 to the microprocessor 1 as the operating clock signal CK. The microprocessor 1 performs a relatively low-speed control operation in synchronization with its clock signal CLK2, reads out the operating system held in the low-speed access memory 2 according to the operation mode shown in Table 1, and then transfers it to the high-speed access memory 3. When the necessary data transfer is completed by sequentially repeating this operation, the microprocessor 1 rewrites the clock selection information C3EL to a high level. As a result, when the microprocessor 1 performs an emulation operation while executing a user program, the control operation is performed in synchronization with the system clock signal CLKs having a relatively high frequency. In this operation, the operation of the low-speed access memory 2 is replaced by the operation of the high-speed access memory 3, and the operating speed of the system including the low-speed access memory 2 is increased.

According to the above embodiment, the following effects can be obtained.

(1) In a system including low-speed access memory 2,
A high-speed access memory 3 is arranged at an address that overlaps with the low-speed access memory 2, and a clock switching control circuit 6 is provided that can synchronize clock signals CLKs and CLK2 having different frequencies and switch and supply them to the microprocessor 1. Since it is determined whether to access the low-speed access memory 2 or the high-speed access memory 3 depending on the selected state of the clock signal frequency by the switching control circuit 6, the operation of the microprocessor processor 1 is synchronized with the system clock signal CLKs. At this time, the low speed access memory 2 is replaced with the high speed access memory 3, thereby increasing the operating speed of the system including the low speed access memory 2.

(2) At this time, since low-speed access memory 2 and high-speed access memory 3 are mapped to overlapping addresses and their operations are controlled alternatively, the operation of low-speed access memory 2 is replaced by the operation of high-speed access memory 3. It becomes extremely easy.

(3) Furthermore, since the operating clock frequency for the microprocessor 1 is synchronized and switching is controlled, it is not necessary to reset the microprocessor 1 when switching the frequency of the operating clock signal CK.

(4) When emulating a target system using a so-called single-chip microcomputer in which a ROM for holding a program is mounted on a single semiconductor substrate, use a dedicated evaluation chip that does not have a ROM for holding the program, When downloading the user program necessary for operation from the system development device to the substitute memory in the emulator, and installing an existing EPROM chip in the emulator for the operating system, etc., EPROM, which has a slower access speed than RAM etc. Since it is not necessary to directly access chips etc. for emulation, it is possible to perform emulation while satisfying the operating speed required by the target system and even the original operating speed of the single-chip microcomputer as the target processor. .

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, the present invention is not limited to processors that do not have a wait function, and the present invention can also be applied to cases where there are restrictions such that even if the processor has a wait function, the function cannot be used.

Furthermore, low-speed access memory is not limited to EPROM;
It may also be an EEPROM. Low-speed access memory and high-speed access memory can be distinguished based on the concept that their access speeds are relatively different.

Furthermore, the information stored in the low-speed access memory is not limited to the operating system, and can be changed to other appropriate information.

In the above explanation, the invention made by the present inventor was mainly applied to an emulator, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and the present invention is not limited to this, but is applicable to a microprocessor board that can be used for general purpose. The present invention can be widely applied to computer boards, etc. 6. The present invention can be applied at least to conditions where data processing is performed using information stored in a low-speed access memory.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when the processor operates at high speed, the operation of the low-speed access memory is replaced by the operation of the high-speed access memory, which has the effect of increasing the operating speed of a system including the low-speed access memory.

At this time, the low-speed access memory and the high-speed access memory are mapped to overlapping addresses, and their operations are selectively controlled, so it is possible to replace the operation of the low-speed access memory with the operation of the high-speed access memory in an extremely simple manner. can. Moreover, since the clock frequencies for the processors are switched and controlled in synchronization, it is possible to save the effort of resetting the processors when switching the clock signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a microprocessor board which is an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a clock switching control circuit. FIG. 3 is a timing chart for explaining an example of a clock switching operation, and FIG. 4 is a flowchart showing an example of a data transfer control procedure from a low-speed access memory to a high-speed access memory. DESCRIPTION OF SYMBOLS 1... Microprocessor, 2... Low-speed access memory, 3... High-speed access memory, 6... Clock switching control circuit, 7... Decoder, 8... Clock selection register, C3EL... Clock selection information, CLK
s...System clock signal, CLK...Clock signal, 11\I Figure

Claims (1)

[Claims] 1. A processor that operates in synchronization with a clock signal, a low-speed access memory and a high-speed access memory to which mutually overlapping addresses are assigned, and clock signals with different frequencies can be synchronized and switched and supplied to the processor. and selecting the operation of the low-speed access memory or the high-speed access memory according to the selected state of the clock signal frequency by the clock switching means when accessing addresses redundantly assigned to the low-speed access memory and the high-speed access memory. and control means for controlling the data processing system. 2. The processor includes the steps of causing the clock switching means to select a clock signal with a relatively low frequency, read accessing the low-speed access memory in synchronization with the clock signal selected in the step, and performing the steps of: After completing the step of write-accessing the read-accessed data to the high-speed access memory and the transfer of the required data from the low-speed access memory to the high-speed access memory, causing the clock switching means to select a clock signal with a relatively high frequency. 2. The data processing system according to claim 1, wherein the data processing system is capable of executing the steps.