JPH0220913A - register - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a register for temporarily storing digital information.

2. Description of the Related Art An example of the above-mentioned conventional register will be described below with reference to the drawings.

FIG. 2 shows the structure of a conventional register. Second
In the figure, 1 is a synchronous D flip-flop, 2 is a gate circuit, 3 is a synchronous clear or synchronous preset input, and 4 is a synchronous D flip-flop.
is a data input, 5 is a data output, and 6 is a clock input.

The operation of the conventional register configured as described above will be explained below. First, when the synchronous clear (preset) input 3 is disabled, the output of the gate circuit 2 is the same as the data output 4 and is output to the data output 6 in synchronization with the clock 6. When the synchronous clear manual power 3 is enabled, the output of the gate circuit 2 is o(
1) and is output to the data output 5 in synchronization with the clock 6.

A truth table as an example of operation is shown in Figure 3.

FIG. 3 shows the case of a synchronous clear input, in which the synchronous clear input is disabled at 1 and enabled at 0, and a positive edge trigger type is used as the 2 synchronous D flip-flops.

Problems to be Solved by the Invention However, with the above configuration, the delay time of the gate circuit or the setup time of the D flip-flop,
Due to the difference in hold time, when a change occurs in the synchronous clear (preset) input around the time when the gate circuit output is taken into the D flip-flop in synchronization with the clock, the data output is cleared (preset) and the data is not cleared (preset). The problem was that the output was too high.

In view of the above problems, the present invention is a register in which, even if the synchronous clear (preset) input changes at any point, all outputs are cleared (preset) or all data inputs are output as they are to data outputs. It provides:

Means for Solving the Problems In order to solve the problems, the register of the present invention includes a plurality of data synchronous D flip-flops, a control synchronous flip-flop having a synchronous clear or synchronous preset input, and a plurality of synchronous D flip-flops for control. A plurality of gate circuits each receiving the output of the data synchronous D flip-flop are provided, and the gate circuit forces the output of the data synchronous D flip-flop 70 by the output of the control synchronous D flip-flop. The value is set to 0 or 1.

Effects of the present invention With the above-described configuration, the data output is determined based on the output of the only synchronous D flip-flop for control, so even if the synchronous clear (preset) input changes at any point, all outputs are cleared (preset). The only things that can happen are either the data input is output as is, or the data input is output as is to the data output.

Embodiment Hereinafter, a register according to an embodiment of the present invention will be explained with reference to the drawings. FIG. 1 shows the structure of a register in a first embodiment of the present invention. In FIG. 1, 1 is a synchronous D flip-flop for data, 2 is a gate circuit, 3 is a synchronous clear (or synchronous preset) input,
4 is data input, 5 is data output, 6 is clock input,
7 is a synchronous D flip-flop for control.

The operation of the register configured as described above will be explained below with reference to FIG.

First, in synchronization with the clock, the data input 4 is outputted to the output of each flip-flop 1, and the synchronous clear (preset) input 3 is outputted to the data output 5 of the control synchronous D flip-flop 7. If the synchronous clear input is disabled by the output of the control synchronous flip-flop, the gate circuit 20 input is output as is to data output 6, and if the synchronous clear input is enabled, data output 5 is The output of the gate circuit 2 is forced to be o(1).

A truth table as an example of operation is shown in Figure 3.

Figure 3 shows the case of synchronous clear input.
” to disable, “0” to enable, and a positive edge trigger type synchronous D flip-flop is used.

As described above, according to this embodiment, there are a plurality of data synchronous flip-flops 70, a control synchronous D flip-flop having a synchronous clear or synchronous preset input, and a plurality of data synchronous flip-flops 70. A plurality of gate circuits are provided which receive each output of the knob as input, and the gate circuit is configured to forcibly set the output of the data synchronous D flip-flop to 0 or 1 by the output of the control synchronous D7 flip-flop. As a result, no matter what time the synchronous clear (preset) input changes, the only thing that will happen is that all the outputs will be cleared (preset) or all the data inputs will be output as they are to the data outputs.

Effects of the Invention As described above, the present invention provides a plurality of data synchronous D flip-flops, a control synchronous D flip-flop having a synchronous clear or synchronous preset input, and a plurality of data synchronous D7 flip-flops. A plurality of gate circuits having outputs as inputs are provided, and the gate circuit is configured to force the output of the data synchronous D flip-flop to about 0 or 1 by the output of the control synchronous D flip-flop. Therefore, even if the synchronous clear (preset) input changes at any point, the only thing that will happen is that all the outputs will be cleared (preset) or all the data inputs will be output as they are to the data outputs.

[Brief explanation of the drawing]

1... Synchronous clip for data 70 tabs, 2
...... Gate circuit, 3... Synchronous clear (
Preset input, 4...Data input, 6...
...Data output, 6...Clock input, 7.
...Control dose M formula % formula %

Claims (1)

[Claims] A plurality of synchronous D flip-flops for data, a synchronous D flip-flop for control having a synchronous clear or synchronous preset input, and a plurality of gate circuits each having each output of the plurality of synchronous D flip-flops for data as inputs. A register, wherein the gate circuit forcibly sets the output of the data synchronous D flip-flop to 0 or 1 based on the output of the control synchronous D flip-flop.