JPH02308616A - Edge detection circuit - Google Patents

Abstract

PURPOSE:To obtain an output pulse representing the leading edge and trailing edge without fail by using a D FF so as to detect the leading and trailing edges of an input pulse with an exclusive OR circuit. CONSTITUTION:A pulse (d) from an external input terminal 11 and a delay pulse (e) from a D FF are processed by an exclusive OR circuit 2 and a pulse (f) detecting the leading and trailing edges of the pulse (d) is outputted from an external output terminal 12. The pulse (f) is fed to a clock terminal C of a D FF 1 whose output inverse of Q is fed to the data terminal D and outputs the output Q5 as the delay pulse (e). No inverter is used for the delay pulse output and the output of the circuit 2 is fed back to obtain the constitution with the D FF 1, then even when the output of the circuit 2 approaches 0 limitless, the pulse (e) is outputted without fail and the leading and trailing edges of the input pulse is obtained without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital circuit used in electronic equipment and the like, and particularly to an edge detection circuit that detects rising and falling edges of a pulse.

[Conventional technology]

Conventionally, this type of edge detection circuit has used a method of detecting edges with an exclusive OR circuit (EX-OR circuit) 5 to obtain output pulses, as shown in FIG. That is, the input pulse d shown in FIG. 2 is applied to one of the input terminals of the EX-OR circuit 50, and the input pulse d is applied to the other input terminal.
The output pulse f shown in FIG. 2 was obtained by giving a delay width obtained by passing through two inverters 5 and 4.

[Problem that the invention seeks to solve]

In the conventional edge detection circuit described above, as shown in FIGS. 5 and 4, an input pulse d is applied from an external input terminal 21, and a pulse e output from an output point 22 of an inverter 6.4 rises at a time t. In this case, the delayed pulse θ with respect to the input pulse d
The delay is due to the inverter delay T2+T, (=t, -t, ), as explained earlier.

Also, the υ output pulse f from the external output terminal 26 is T3+T
,' (= T2 + T,), but is further delayed by the delay T2 of the EX-OR circuit 5 and becomes t.
, stand up.

Here, assuming that the delay of the inverters 5, 4 and the EX-OR circuit 5 is as close to "0" as possible, that is, T, +
Assuming that T3→0 and T2→0.

Since the expected value becomes 0 in the simulation, there is a drawback that the output pulse f becomes T3+T,=0 and cannot be obtained.

[Failure to solve the problem]

According to the present invention, edge detection detects the rising edges and falling edges of an input pulse using an output pulse obtained by taking the exclusive OR of an external input pulse and a delayed pulse obtained by delaying this input pulse. In the circuit, the means for obtaining the delayed pulse feeds back the output pulse to the clock terminal and inputs its inverted output to the output terminal.

There is obtained an edge detection circuit characterized in that it is constituted by a flip-flop circuit that uses the output from the output terminal as the delayed pulse.

〔Example〕 Next, the present invention will be explained with reference to two drawings.

FIG. 1 is a diagram showing an edge detection circuit of the present invention. DF
It is composed of F1 and EX-OR circuit 2. Input pulse dtl-EX-OR in Figure 2 from external input terminal 11
Insert into circuit 2 and again.

The pulse e in Fig. 2 is obtained from the output Q of DFFl.

It is inputted into the EX-OR circuit 2 and the exclusive OR of these two pulses e and f is taken, one of which is outputted from the external output terminal 12 as the external output f in Fig. 2, and the other is fed back. Used as a clock for DFF1.

FIG. 5 is a diagram showing the details of the rise in FIG. 1, and assumes that the input pulse d rises at tb. Next, the reason why the pulse e rises at t6 is Tb+T
c+toe 5 Delay Tb of EX-OR circuit 2 and clock operation T0=t6-t.

This is due to In addition, +Tc +Ta (=
t.

-to) clock width is Tb +Tc (= td-t
b) is equal to However, the reason why Tb"jc"b is delayed with respect to the input pulse d is that the KX-OR circuit 2
This is due to the delay.

Therefore, even if the delay caused by the EX-OR circuit 2 is as close to "o" as possible, that is, 0 in 'rb, the clock operation T0 exists, so an output pulse is always obtained.

〔Effect of the invention〕

As explained above, the present invention uses DFF to perform EX-OR
By detecting the output by the circuit, the delay on the simulator 1 is limited (even if it is close to "0", the expected value is obtained. In other words, the effect that the output pulse can be output by the clock operation of the DBE is be.

[Brief explanation of drawings]

FIG. 1 shows an edge detection circuit of the present invention, FIG. 2 shows a time chart at each point, and FIG. 5 shows a conventional edge detection circuit.
Figures 4 and 5 are detailed time charts of Figure 2.
FIG. 4 is a detailed time chart of the first rise 9 in FIG. FIG. 5 is a detailed time chart of the first rise 9 in FIG. Symbol explanation: 1...D type flip-flop (DFF)
, 2.5... exclusive OR circuit (EX-OR circuit),
5.4... Impark, ii, 2i... External input terminal, 12.23... External output terminal, 22... Output point, tl, ta, etc. are time axis + Tl + 'r
, etc. each indicate the time range. Figure 1 ¥ 2 Figure ¥ 4 Figure 5 Section ta tb tc tci ta
:1(1

Claims (1)

[Claims] (1) In an edge detection circuit that detects rising and falling edges of an input pulse using an output pulse obtained by taking the exclusive OR of an external input pulse and a delayed pulse obtained by delaying this input pulse, the delayed pulse means for obtaining a feedback input of the output pulse to a clock terminal;
An edge detection circuit comprising a flip-flop circuit which inputs its own inverted output to an input terminal and uses the output from the output terminal as the delayed pulse.