JPH0220920A - Output buffer - Google Patents

Abstract

PURPOSE:To optimize the dimension of an output buffer by constituting said output buffer of plural final stage transistors and plural control logical gates which are inputted to its pre-stage parts. CONSTITUTION:The title output buffer is constituted of plural final stage FETs 11 for driving one load capacity, plural pre-stage parts 12 which are inputted to its gates, and plural control logical gates 13 which are inputted to the pre- stage parts 12. When a numerical value which has added up the dimensions of the final stage transistors in output buffer circuits 15-17 is denoted as W, the dimension of the output buffer circuit 15, the dimension of the output buffer circuit 16, and the dimension of the output buffer circuit 17 are set to W/2, W/4 and W/4, respectively. When output control signals 18-20 are set to such a mode as all the final stage transistors of these output buffer circuits 15-17 are all operated, when the dimension is too large as a whole, the control signals 19, 20 are set to disable in accordance with necessity. In such a way, the dimension of the final stage transistors can be reduced as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer, and more particularly to an output buffer of an integrated circuit that drives a load capacitance in a signal output section.

[Conventional technology]

In recent years, the performance required of integrated circuits such as microprocessors is high speed operation and processing of large amounts of data. For this reason, output buffers with large dimensions are increasingly used as output circuits in order to quickly charge and discharge the load capacitance. Furthermore, data buses and the like tend to have more bits in order to process large amounts of data all at once. As a result, a large load capacity is charged and discharged at high speed, and the light and discharge current generates noise on the integrated circuit's internal power supply, GND, etc., which causes malfunction of the device. Therefore, it is difficult to unnecessarily increase the dimension of the output buffer in order to increase the speed, and it is extremely difficult to design an optimal output buffer in consideration of the speed standard of the integrated circuit.

[Problem to be solved by the invention]

The conventional output buffer described above charges and discharges the load capacitance at high speed, which may introduce noise into the power supply, GND, etc., and also needs to satisfy high-speed speed standards, so the dimensions of the output buffer are The design is extremely difficult.

Furthermore, even if a large-dimensional output buffer can be designed without malfunction, if high-speed operation is not required, this may lead to an unnecessary increase in current consumption, which is not preferable.

[Means to solve the problem]

The output buffer of the present invention is composed of a plurality of final stage FETs that drive one load capacitance, a plurality of front stage parts input to the gate thereof, and a plurality of control logic gates input to the front stage part. The gates are configured to receive a common data signal and different passage control signals.

〔Example〕

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Reference numeral 11 denotes the final stage transistor, which is composed of CMO3.The P-channel source is connected to the power supply, the N-channel (hereinafter referred to as "ch") source is connected to GND, the drain terminal is connected to the output terminal, and the load capacitance is 14. 1
Reference numeral 2 designates a buffer in front of the final stage transistor, which is input to the gates of the final stage transistors P-ch and N-ch. 13 is a gate for controlling the final stage transistor, which is controlled by passage control signals 18, 19, and 20, and is connected to data signal 2.
It outputs 1. Output buffer circuit 15.16
．． Reference numeral 17 has the same configuration as the circuit described above, and only the dimension of the final stage transistor 11 is different.

In this embodiment, when the pass control signals of the output control signals 18, 19 and 20 are all at high level, the final stage transistors in the output buffer circuits 15, 16, and 17 are set to P-ch according to the value of the output data signal 21 , N-ch is turned on, charging and discharging the load capacity.

Here, if the total dimension of the final stage transistors in the output buffer circuits 15, 16, and 17 is W, then the dimension of the output buffer circuit 15 is W/2. The dimension of the output buffer circuit 16 is W/
4. The dimension of the output buffer circuit 17 is also set to W/4. This is necessary if the overall dimension is too large when the output control signals 18, 19, and 20 are set to a mode in which all the final stage transistors of the output buffer circuits 15, 16, and 17 operate. By setting the control signals 19 and 20 to disable according to this, the dimension of the final stage transistor can be reduced as a whole.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

The configurations 11 to 17 are the same as the embodiment shown in FIG.

22 is a NOR type decoder; decoder 23.
When the inputs to 24 are 0 and 0, respectively, and the output control signal 25 is high level, the decoder output line, that is, the output buffer passage control signal 27 becomes active, and when the decoder input is 1 and 1, respectively, and the output control signal 25 is high level, the decoder output line, that is, the output buffer passage control signal 27 becomes active. When the signal 25 is at high level, the decoder output line and the output buffer passage control signal 26 become active.0 When all the input lines to the "○" mark in the figure become active, the output signal lines 26 and 27 become active.
becomes active. The decoder power lines 23, 24 are each connected to an external terminal of the integrated circuit.

When operating a large capacitive load at high speed, the input 23.2 should be set to maximize the output buffer dimension.
4, and if only a small capacitive load needs to be driven and data output delay is acceptable, inputs 23 and 24 should be set so that the output buffer dimension is as small as necessary. gives the optimal dimension of the output buffer.

〔Effect of the invention〕

As explained above, according to the present invention, the dimension of the output buffer can be adjusted using a control signal, and thereby the dimension of the output buffer can be optimized in consideration of load capacity, speed, etc. effective.

Furthermore, when high-speed operation is not required, low current consumption can be achieved by reducing the charging and discharging current of the load capacitor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the invention, and FIG. 2 is a circuit diagram of another embodiment of the invention. 11... Output final stage transistor, 12... Buffer, 13... Output control logic gate, 14... Load capacitance, 15, 16. 17... Output buffer circuit, 18...
...15 output buffer output control signal, 19...1
6 output buffer output control signal, 20...17 output buffer output control signal, 21... data signal, 2
2...NOR type decoder, 23°24...
Output buffer control input, 25... Output passing control signal, 26... Output control signal for the 16 output buffers, 27
...Output control signal of 17 output buffers/lJ, t
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l 2t--A 1 tie each 1

Claims (1)

[Claims] It is composed of a plurality of sets of final stage transistors that drive one load capacitance, a plurality of sets of front stage parts input to the gates thereof, and a plurality of sets of control logic gates input to the front stage parts, and the logic gates include An output buffer to which a common data signal and individually controllable passing control signals are input.