JPH02233018A - Output buffer - Google Patents

Abstract

PURPOSE:To adjust separately P-channel and N-channel transistors(TRs) of the dimension of the final stage of an output buffer by adopting the constitution such that the final stage N-channel and P-channel TRs, plural pre-stages controlling the TRs separately and plural control gates inputting to the pre-stage are provided. CONSTITUTION:CMOS TRs are adopted for the final stage TRs 11, 12 and a source of a P-channel TR connects to a power supply and a source of an N-channel TR connects to GND. The load capacitor 15 is driven by the TRs. A buffer 13 connects to each gate of the final stage TRs 11, 12. An output control logic gate 14 is controlled by output control signals 16, 17 and outputs a data signal 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer, and more particularly to an output buffer of an integrated circuit that drives a load capacitance in a signal output section.

[Conventional technology]

In recent years, the performance required of integrated circuits such as microprocessors includes high-speed operation and processing of large amounts of data. Therefore, as output circuits, output buffers with large dimensions are increasingly used in order to charge and discharge the load capacitance at high speed. Furthermore, there is a tendency for data buses and the like to become multi-bit because of the need to process a large amount of data all at once. As a result, a large load capacity is charged and discharged at high speed, and the charging/discharging current causes noise on the power supply, GND, etc. inside the integrated circuit, which causes malfunction of the device. Therefore, it is difficult to unnecessarily increase the dimension of the output buffer in order to increase the speed, and in the case of CMOS, determining the ratio of the dimensions of the output buffer's P-ch} transistor and N-ch} transistor is also difficult due to the generation of through current. This poses a problem, and it is extremely difficult to design an optimal output buffer dimension in consideration of the speed standard of the integrated circuit.

[Problem to be solved by the invention]

The conventional output buffer described above charges and discharges the load capacitance at high speed, which may generate noise in the power supply, GND, etc., and the dimension design of the output buffer is extremely difficult in order to satisfy high-speed speed standards. It has become very difficult.

Further, in the case of CMOS, it is difficult to determine the dimension ratio of the P-ah and N-ch final stage transistors for the above-mentioned reasons.

[Means to solve the problem]

A plurality of N-ch, P-ch final stage transistors that drive the load capacitance of one output buffer of the present invention, and an N-ch
, P-ch separately, and a plurality of control gates that are input to the front stage, and a common gate signal and different pass control signals are input to the control gates. The configuration is as follows.

Therefore, the dimensions of the final stage transistor of the output buffer can be adjusted separately for P-ch and N-ch.

〔Example〕 FIG. 1 is a circuit diagram of an embodiment of the present invention.

11.12 is the final stage transistor, which is composed of CMOS, with a P-channel source for the power supply and an N-channel for the GND.
A channel (hereinafter referred to as ch) is connected, a drain terminal is connected to an output terminal, and a load capacitor 15 is driven. 13
is input to the gate of each of the final stage transistors 11 and 12. 14 is a gate for controlling the final stage transistor;
．． It is controlled by 17 output control signals and outputs 18 data signals.

In this embodiment, when all l60 passing control signals are at high level and all 17 passing control signals are at low level 17-<L, P-ch,
N-ch } Either one of the transistors is turned on, charging and discharging the load capacitance.

Here, when the maximum operating speed of the output buffer is required, and the dimensions of the P-ch, N-ch h} transistors are set as Wp and Wn, respectively, 3
The dimensions of the 11 and 12 output final stage transistors may be set to approximately Wn/3 and Wp/3, respectively.

If the control signal in 16.17 is applied to enable all three output final stage transistors in 11.12 and data output operation is performed, if the load capacitance is large, the power supply and GND will be Noise is generated due to load capacitance charging/discharging current, through current, etc., which may lead to malfunction of the integrated circuit. In this case, by setting any of the control signals 16 or 17 to disable as necessary, the dimension as an output buffer can be reduced,
The ratio of the P ch * N ch dimensions can be changed.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

The configurations 21 to 25 are almost the same as in the first embodiment.

In this embodiment, the number of divisions of the final stage transistors is changed from 3 to 4. (Increasing the number of divisions allows the dimensions to be set more precisely.) In this case, the number of output control signals increases, but as in this example, the number of output control signals increases.
If the control signals of 6.27 are decoded by the decoder 28, there is an advantage that the number of control signals can be reduced.

〔Effect of the invention〕

As explained above, in the present invention, the size of the output buffer can be adjusted separately for the P-ch} transistor and the N-ah} transistor by the control signal, and this allows the size of the output buffer to be adjusted in consideration of the load capacitance speed, etc. This has the effect of dimensional optimization.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the invention, and FIG. 2 is a circuit diagram of another embodiment of the invention. 1l...P-channel output final stage transistor, 12...N-channel output final stage transistor, 13...buffer, 14...output control logic gate and 15...load capacity, 16,1
7... Output control signal, 18... Data signal, 2l... Output final stage transistor (P-
ch), 22... Output final stage transistor (N-ch), 23... Buffer, 24... Output control logic game, 27... Output Control signal, 25...Load capacitance, 26, 28...Data signal,...Decoder.

Claims (1)

[Claims] By multiple sets of final stage P-channel and N-channel transistors that drive one load capacitance, multiple sets of front stage parts input to the gates thereof, and multiple sets of control logic gates input to the front stage parts. 1. An output buffer comprising: a common data signal and a pass control signal capable of independently controlling the P-channel and N-channel transistors in the final stage;