JPH02209754A - Electrode wiring of integrated circuit device - Google Patents
Electrode wiring of integrated circuit deviceInfo
- Publication number
- JPH02209754A JPH02209754A JP3047189A JP3047189A JPH02209754A JP H02209754 A JPH02209754 A JP H02209754A JP 3047189 A JP3047189 A JP 3047189A JP 3047189 A JP3047189 A JP 3047189A JP H02209754 A JPH02209754 A JP H02209754A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wiring
- circuit device
- electrode wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 5
- 229910008484 TiSi Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は集積回路装置の電極配線法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an electrode wiring method for integrated circuit devices.
［従来の技術］
従来、集積回路装置の電極配線法は、Ｓ１０゜［発明が
解決しようとする課題］
しかし、上記従来技術によると電極配線間隔や多層配線
の配線間隔がサブ、ミクロン領域になると、８１０□等
の絶縁膜の誘電率が大体６程度であるために、配線間電
気容量が大となり、集積回路の動作速度を上げることが
できないと云う課題があった。[Prior Art] Conventionally, the electrode wiring method for integrated circuit devices is S10° [Problem to be Solved by the Invention] However, according to the above-mentioned conventional technology, when the electrode wiring spacing or the wiring spacing of multilayer wiring reaches the sub-micron range, , 810□, etc., has a dielectric constant of about 6, so the capacitance between wirings becomes large, and there is a problem that the operating speed of the integrated circuit cannot be increased.
本発明は、かかる従来技術の課題を解決し、集積回路装
置の電極配線の配線間隔がサブ・ミクロン領域となって
も配線間電気容量が増大せず、集積回路装置の動作速度
を向上させることができる新しい電極配線法を提供する
事を目的とする。The present invention solves the problems of the prior art, and improves the operating speed of the integrated circuit device without increasing the capacitance between the wires even if the spacing between the electrode wires of the integrated circuit device is in the sub-micron range. The purpose is to provide a new electrode wiring method that allows for
［課題を解決するための手段］
上記課題を解決するために、本発明は、集積回路装置の
電極配線法に係り、集積回路装置における配線をエアー
・アイソレーションして配すると共に、パッド部に於て
は、絶縁膜を配する手段をとる事、及び前記配線をタン
グステン配線となす手段をとる。[Means for Solving the Problems] In order to solve the above problems, the present invention relates to an electrode wiring method for an integrated circuit device, in which the wiring in the integrated circuit device is arranged with air isolation, and the pad portion is In this case, measures are taken to arrange an insulating film, and measures are taken to make the wiring a tungsten wiring.
［実施例コ 以下、実施例により本発明を詳述する。[Example code] Hereinafter, the present invention will be explained in detail with reference to Examples.
第１図は本発明の一実施例を示す半導体集積回路装置の
要部の断面図である。すなわち、Ｓｉ基板１の表面には
、拡散層２及び半導体表面保護膜としての５−ｉ０２膜
やＳｉ、Ｎ４膜等から成る第１の絶縁膜４が形成される
と共に、前記拡散層２のコンタクト部にはフンタクト抵
抗を下げるためのＴｉＳｉ膜６が形成され、更に、その
上に第１のＷ配線５がサブ・ミクロン巾と間隔でもって
Ｗ又はＴｉＷ又はＴ１上のＷ配線としてエアー・アイソ
レーションされて形成されて成り、該第１のＷ配線５の
上に更に第２のＷ配線がエアー・アイソレーションして
成る。尚、第２のＷ配線２は、パッド部に於て、第２の
絶縁膜６の上にまたがって形成されて成り、該第２のＷ
配線７の表面又は表面と連らなって第２の絶縁膜乙の上
でＡｔパッド８が形成されて成り、外部リード取り出し
口を形成して成る。Ｗ配線のエアー・アイソレーション
部は、ホト・レジスト膜等にて予しめ埋められているが
、後程アッシング処理や加熱処理（ある種の有機物ｊ摸
は４００℃程度の加熱で蒸発させる事ができる。）して
形成することとなる。又、本例の如く必ずしも多層配線
構造をとる必要のない事は云うまでもない。FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device showing an embodiment of the present invention. That is, on the surface of the Si substrate 1, a diffusion layer 2 and a first insulating film 4 made of a 5-i02 film, Si, N4 film, etc. as a semiconductor surface protection film are formed, and a contact of the diffusion layer 2 is formed. A TiSi film 6 is formed on the surface of the TiSi film 6 in order to lower the physical resistance, and furthermore, a first W wiring 5 is formed on it with a sub-micron width and a spacing as a W wiring on W or TiW or T1 for air isolation. A second W wiring is further formed on the first W wiring 5 by air isolation. Note that the second W wiring 2 is formed in the pad portion so as to straddle the second insulating film 6.
An At pad 8 is formed on the surface of the wiring 7 or on the second insulating film B continuous with the surface, and forms an external lead extraction port. The air isolation part of the W wiring is filled in advance with a photoresist film, etc., but it is later filled with ashing treatment and heat treatment (certain organic substances can be evaporated by heating to about 400 degrees Celsius). ). Furthermore, it goes without saying that it is not necessarily necessary to adopt a multilayer wiring structure as in this example.
［発明の効果コ
本発明によりサブ・ミクロン配線間を誘電率１のエアー
・アイソレーションする事ができ、集積回路装置の配線
電気容量を小さくする事ができ、集積回路装置の動作速
度を向上する事ができる効果がある。[Effects of the Invention] According to the present invention, it is possible to provide air isolation with a dielectric constant of 1 between sub-micron interconnections, thereby reducing the interconnect capacitance of integrated circuit devices and improving the operating speed of integrated circuit devices. It has the effect of being able to do things.
第１図は本発明の一実施例を示す半導体集積回路装置の
要部の断面図である。
１・・・・・・・・・Ｓ１基板
２・・・・・・・・・拡散層
３・・・・・・・・・ＴｉＳｉ層
４・・・・・・・・・第１の絶縁膜
５・・・・・・・・・第１のＷ配線
６・・・・・・・・・第２の絶縁膜
７・・・・・・・・・第２のＷ配線
８・・・・・・・・・Ａｔパッド
以上FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device showing an embodiment of the present invention. 1...S1 substrate 2...Diffusion layer 3...TiSi layer 4...First insulation Film 5...First W wiring 6...Second insulating film 7...Second W wiring 8...・・・・・・At pad or more
Claims (2)
ションされて配されて成ると共にパッド部に於ては、絶
縁膜を介して配されて成る事を特徴とする集積回路装置
の電極配線法。(1) An electrode wiring method for an integrated circuit device, characterized in that the wiring in the integrated circuit device is arranged in an air-isolated manner, and in the pad portion, the wiring is arranged through an insulating film.
なす事を特徴とする請求項１記載の集積回路装置の電極
配線法。(2) The electrode wiring method for an integrated circuit device according to claim 1, characterized in that the wiring in the integrated circuit device is made of tungsten wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3047189A JPH02209754A (en) | 1989-02-09 | 1989-02-09 | Electrode wiring of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3047189A JPH02209754A (en) | 1989-02-09 | 1989-02-09 | Electrode wiring of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02209754A true JPH02209754A (en) | 1990-08-21 |
Family
ID=12304782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3047189A Pending JPH02209754A (en) | 1989-02-09 | 1989-02-09 | Electrode wiring of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02209754A (en) |
-
1989
- 1989-02-09 JP JP3047189A patent/JPH02209754A/en active Pending
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