JPH02210831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH02210831A
JPH02210831A JP3216189A JP3216189A JPH02210831A JP H02210831 A JPH02210831 A JP H02210831A JP 3216189 A JP3216189 A JP 3216189A JP 3216189 A JP3216189 A JP 3216189A JP H02210831 A JPH02210831 A JP H02210831A
Authority
JP
Japan
Prior art keywords
region
film
semiconductor film
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3216189A
Other languages
Japanese (ja)
Inventor
Masanori Ishii
正典 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3216189A priority Critical patent/JPH02210831A/en
Publication of JPH02210831A publication Critical patent/JPH02210831A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To surely perform anodic oxidation when the connection position of an anode is arbitrary by covering the periphery of an element forming region or a circuit forming region of a semiconductor film, with an insulating film, and stretching said insulating film over the electrode connection position. CONSTITUTION:The periphery of an element forming region or a circuit forming region 6 of a conductive semiconductor film 1 is covered with an insulating film 4, which is stretched over an electrode connection region 7. As a result, current flows always from an electrode 8 to the element forming region or the circuit forming region 6 through the conductive semiconductor film 1 in the region where the insulating film 4 is formed. Thereby, even when the electrode 8 is connected with a region whose film thickness is the thinnest or a region whose impurity concentration is the lowest, anodic oxidation of a region whose film thickness is thick or a region whose impurity concentration is high can surely be performed.

Description

【発明の詳細な説明】 〔概 要〕 半導体基板の上にエピタキシャル成長させた半導体膜の
表面を陽極酸化する工程を含む半導体装置の製造方法に
関し、 導電性半導体膜における電極の接続位置にかかわらず、
陽極酸化を確実に行わせることを目的とし、 基板上に形成した導電性半導体膜における素子形成領域
または回路形成領域の周囲を絶縁膜により覆うとともに
、該絶縁膜を、上記導電性半導体膜における電極接続領
域の近傍まで延設し、該電極接続領域に電極を接続して
上記導電性半導体膜の上記素子形成領域または回路形成
領域の表面を陽極酸化し、上記導電性半導体膜の上記素
子形成領域または回路形成領域を薄層化する工程を含み
構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device including a step of anodizing the surface of a semiconductor film epitaxially grown on a semiconductor substrate, regardless of the connection position of the electrode in the conductive semiconductor film,
In order to ensure that anodic oxidation is performed, the periphery of the element formation region or circuit formation region in the conductive semiconductor film formed on the substrate is covered with an insulating film, and the insulating film is used as the electrode in the conductive semiconductor film. extending to the vicinity of the connection region, connecting an electrode to the electrode connection region, and anodizing the surface of the element formation region or circuit formation region of the conductive semiconductor film; Alternatively, the structure includes a step of thinning the circuit forming region.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置の製造方法に関し、より詳しくは
、半導体基板の上にエピタキシャル成長させた半導体膜
を陽極酸化する工程を含む半導体装置の製造方法に関す
る。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a step of anodizing a semiconductor film epitaxially grown on a semiconductor substrate.

〔従来の技術〕[Conventional technology]

半導体膜に不純物を混入する方法としては、半絶縁性半
導体基板上にイオン注入方法により不純物イオンを注入
する第一の方法、MBE法によりエピタキシャル成長さ
せる第2の方法、及び液相または気相法によりエピタキ
シャル成長させる第3の方法に大別できる。
Methods for mixing impurities into a semiconductor film include a first method of implanting impurity ions onto a semi-insulating semiconductor substrate by an ion implantation method, a second method of epitaxial growth using an MBE method, and a liquid phase or vapor phase method. It can be roughly divided into the third method of epitaxial growth.

第1の方法によれば、不純物濃度及び深さを均一に制御
することができるという利点があるがイオン注入によっ
て半導体膜の結晶性が劣化するといった問題を有する。
The first method has the advantage that the impurity concentration and depth can be controlled uniformly, but has the problem that the crystallinity of the semiconductor film deteriorates due to ion implantation.

また、第2の方法は均一性、結晶性とも問題はないが量
産性が悪くコストが高くなる。
Further, although the second method has no problems with uniformity or crystallinity, it has poor mass productivity and increases cost.

これに対し、第3の方法は、結晶性、量産性に優れ一般
的に広く用いられている。しかし、不純物の分布や膜の
厚さが不均一になり、この半導体膜を用いて半導体装置
を製造した場合、動作電流にばらつきが発生するという
欠点がある。
On the other hand, the third method has excellent crystallinity and mass productivity, and is generally widely used. However, the distribution of impurities and the thickness of the film become non-uniform, and when a semiconductor device is manufactured using this semiconductor film, there is a drawback that variations in operating current occur.

このため、不純物濃度と膜の厚さの積で近似することに
より動作電流を均一化する手段として、エピタキシャル
法により不純物を混入した半導体膜を成長させた後に、
その導電性半導体膜の表面を陽極酸化して均一な動作電
流を流す動作層を形成することが行われている。
Therefore, as a means of making the operating current uniform by approximating the product of impurity concentration and film thickness, after growing a semiconductor film with impurities mixed in by epitaxial method,
The surface of the conductive semiconductor film is anodized to form an operating layer through which a uniform operating current flows.

また、GaAs F E Tの場合には、ゲート電極形
成領域のみ動作層となる半導体膜の表面をエツチング除
去してリセスを形成し、その下の半導体膜を所定の厚さ
に薄くすることも行われている。このリセスの形成のた
めのエツチングだけでは、リセスに形成したショットキ
電極による空乏層がリセスの周囲まで広がると、そのリ
セスの周囲の部分の半導体膜の厚さに応じて耐圧が変わ
るので、耐圧が均一になるように、リセスの形成の前に
半導体膜全面を陽極酸化して均一な厚さになるようにし
ている。
Furthermore, in the case of GaAs FET, it is also possible to remove the surface of the semiconductor film, which will become the active layer, by etching only the gate electrode formation region to form a recess, and then thin the underlying semiconductor film to a predetermined thickness. It is being said. If the depletion layer formed by the Schottky electrode formed in the recess spreads to the periphery of the recess, the withstand voltage will change depending on the thickness of the semiconductor film around the recess. In order to make the thickness uniform, the entire surface of the semiconductor film is anodized before forming the recess to make the thickness uniform.

陽極酸化は、第4図に示すように、エピタキシャル成長
させた半導体層40の上方から可視光を照射しながらこ
の半導体層40に直流電源の陽電極41を接続し、電界
液の中でその表面を酸化させるものであって、この方法
によれば、半導体層40表面に発生する空乏層42の上
部から酸化が進み、酸化された膜43が厚くなるにつれ
てその空乏層42も下方に移動することになる。
As shown in FIG. 4, anodic oxidation is performed by connecting an anode 41 of a DC power source to an epitaxially grown semiconductor layer 40 while irradiating visible light from above, and then irradiating the surface of the epitaxially grown semiconductor layer 40 in an electrolytic solution. According to this method, oxidation proceeds from the upper part of the depletion layer 42 generated on the surface of the semiconductor layer 40, and as the oxidized film 43 becomes thicker, the depletion layer 42 also moves downward. Become.

このため、不純物濃度が均一であって膜厚が不均一な半
導体層40を陽極酸化する場合には、第4図(a)・に
示すように、半導体膜40のうち最も膜厚が厚い領域A
に陽電極41を接続すると、半導体膜40の表面近傍に
一様に空乏層42が発生して空乏層42の上部が酸化さ
れることになる。
Therefore, when anodizing a semiconductor layer 40 with a uniform impurity concentration and non-uniform film thickness, as shown in FIG. 4(a), the thickest region of the semiconductor film 40 is A
When the positive electrode 41 is connected to the semiconductor film 40, a depletion layer 42 is uniformly generated near the surface of the semiconductor film 40, and the upper part of the depletion layer 42 is oxidized.

この場合、膜厚の薄い領域Bはど空乏層42がバッファ
層45に早く到達して陽電極41からの電流を遮ること
になるため(第4図(b))、膜厚の薄い領域Bでは酸
化が早期に停止する一方(第4図(C))、膜厚の厚い
領域Aでは陽極酸化が続行し、酸化膜43の厚さが増大
することになる。
In this case, in the thin region B, the depletion layer 42 reaches the buffer layer 45 earlier and blocks the current from the anode 41 (FIG. 4(b)). In this case, the oxidation stops early (FIG. 4(C)), while the anodic oxidation continues in the thick region A, resulting in an increase in the thickness of the oxide film 43.

したがって、陽極酸化された膜43を除去することによ
り、半導体膜40の膜厚を均一にすることが可能になる
Therefore, by removing the anodized film 43, the thickness of the semiconductor film 40 can be made uniform.

〔発明が解決しようとする!!i!題]しかし、陽極電
極41を膜厚の薄い領域Bに接続した場合には、第5図
に見られるように、膜厚の薄い領域Bにおいては空乏層
42が短時間でその底部のバッファN45に達すること
になるために、陽電極41から膜厚の厚い領域Aへの電
流の流れはその空乏層42によって阻止されることにな
り、膜厚の厚い領域Aの酸化を早期に停止させる結果、
膜厚を均一にすることができなくなるといった問題が発
生する。
[Invention tries to solve! ! i! However, when the anode electrode 41 is connected to the thin region B, as shown in FIG. As a result, the flow of current from the positive electrode 41 to the thick region A is blocked by the depletion layer 42, which results in the oxidation of the thick region A being stopped early. ,
A problem arises in that the film thickness cannot be made uniform.

もとより、膜厚の厚い部分に陽電極を接続すれば良いが
、非破壊状態で最も膜厚の厚い位置を発見するのは不可
能である。
Of course, it is possible to connect the positive electrode to the thickest part of the film, but it is impossible to find the thickest position in a non-destructive manner.

本発明は、このような問題に鑑みてなされたものであっ
て、陽電極の接触位置にかかわらず陽極酸化を完全に行
わせることができる半導体装置の製造方法を提供するこ
とを目的とする。
The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that allows complete anodic oxidation regardless of the contact position of the anode.

〔課題を解決するための手段〕[Means to solve the problem]

上記した課題は、基板3上に形成した導電性半導体膜1
における素子形成領域または回路形成領域6の周囲を絶
縁膜4により覆うとともに、該絶縁膜4を、上記導電性
半導体膜1における電極接統領域7の近傍まで延設し、
該電極接続領域7に電極8を接続して上記導電性半導体
膜1の上記素子形成領域または回路形成領域6を陽極酸
化し、上記導電性半導体膜の上記素子形成領域または回
路形成領域6を薄くする工程を有することを特徴とする
半導体装置の製造方法により解決する。
The above-mentioned problem is solved by the conductive semiconductor film 1 formed on the substrate 3.
The periphery of the element formation region or circuit formation region 6 is covered with an insulating film 4, and the insulating film 4 is extended to the vicinity of the electrode connection region 7 in the conductive semiconductor film 1,
An electrode 8 is connected to the electrode connection region 7 and the element formation region or circuit formation region 6 of the conductive semiconductor film 1 is anodized to thin the element formation region or circuit formation region 6 of the conductive semiconductor film. The present invention is solved by a method for manufacturing a semiconductor device characterized by having a step of:

〔作 用〕[For production]

本発明において、導電性半導体膜1のうちの素子形成領
域又は回路形成領域6の周囲を絶縁膜4により覆うとと
もに、この絶縁膜4を電極接続領域7に延設するように
しているために、絶縁膜4が形成された領域にある導電
性半導体膜1を通して電極8から素子形成領域又は回路
形成領域6に常時電流を流すことができることになる。
In the present invention, since the periphery of the element formation region or circuit formation region 6 of the conductive semiconductor film 1 is covered with the insulating film 4, and this insulating film 4 is extended to the electrode connection region 7, A current can be constantly passed from the electrode 8 to the element formation region or circuit formation region 6 through the conductive semiconductor film 1 in the region where the insulating film 4 is formed.

この結果、導電性半導体lI21のうち最も膜厚の薄い
領域に電極8で接続したり、最も不純物濃度の低い領域
に電極8を接続しても、膜厚の厚いfII域や不純物濃
度の高い領域の陽極酸化を確実に行うことが可能になる
As a result, even if the electrode 8 is connected to the thinnest region of the conductive semiconductor lI21 or the electrode 8 is connected to the region with the lowest impurity concentration, the thick fII region or the region with high impurity concentration This makes it possible to reliably perform anodic oxidation.

〔実施例〕〔Example〕

(a)発明の一実施例の説明 第2図は、陽極酸化の対象となる円板状の半導体ウェハ
を示す平面図と断面図であって、図中符号1は、ノンド
ープ化合物半導体のバッファN2を介して半絶縁性半導
体基板3の上にエピタキシャル成長されたn型の半導体
膜で、このn型半導体膜1は、気相法、液相法等によっ
て形成されたガリウム砒素(GaAs)等の化合物半導
体からなり、その中に含有するシリコン(Si)等の不
純物は膜成長と同時に均一に混入するように形成されて
いる。
(a) Description of one embodiment of the invention FIG. 2 is a plan view and a sectional view showing a disk-shaped semiconductor wafer to be anodized, and reference numeral 1 in the figure indicates a buffer N2 made of a non-doped compound semiconductor. This n-type semiconductor film 1 is an n-type semiconductor film epitaxially grown on a semi-insulating semiconductor substrate 3 via a compound such as gallium arsenide (GaAs) formed by a vapor phase method, a liquid phase method, etc. It is made of a semiconductor and is formed so that impurities such as silicon (Si) contained therein are uniformly mixed in at the same time as the film grows.

次に、上記した半導体ウェハを用いた本発明の一実施例
を第1.2図に基づいて説明する。
Next, an embodiment of the present invention using the above-described semiconductor wafer will be described based on FIG. 1.2.

まず、n型半導体膜1の上に気相成長法により二酸化シ
リコン(Sing)膜4を形成するとともに、このSi
O2膜4の上にレジスト5を塗布する。そして、このレ
ジスト5を露光処理、現像処理し、n型半導体膜1内方
の複数の半導体素子形成領域6及びn型半導体11!J
1周縁に設けた電極接続領域7の上方にレジスト5の窓
を形成した後(第1図(a))、このレジスト5をマス
クとして弗酸系エツチング液によりSiO□膜4をエツ
チングすると、半導体素子形成領域6の周囲に5i02
膜4が残存するとともに、電極接続領域7からn型半導
体膜1が露出することになる(第1図(b))。
First, a silicon dioxide (Sing) film 4 is formed on the n-type semiconductor film 1 by a vapor phase growth method, and this Si
A resist 5 is applied on the O2 film 4. Then, this resist 5 is exposed and developed to form a plurality of semiconductor element forming regions 6 inside the n-type semiconductor film 1 and the n-type semiconductor 11! J
After forming a window of resist 5 above the electrode connection region 7 provided at one periphery (FIG. 1(a)), the SiO□ film 4 is etched using a hydrofluoric acid etching solution using the resist 5 as a mask, thereby forming a semiconductor. 5i02 around the element formation region 6
While the film 4 remains, the n-type semiconductor film 1 is exposed from the electrode connection region 7 (FIG. 1(b)).

次に、レジスト5を除去した後に、第1図(c)に示す
ように、n型半導体基板1の電極接続領域7にクリップ
状の陽電極8を接続した状態で、酒石酸水溶液にプロピ
レングリコールを加えた電界液9に半導体基板3を浸漬
する。
Next, after removing the resist 5, propylene glycol is added to the tartaric acid aqueous solution while the clip-shaped positive electrode 8 is connected to the electrode connection area 7 of the n-type semiconductor substrate 1, as shown in FIG. 1(c). The semiconductor substrate 3 is immersed in the added electrolyte 9.

そして、上記した陽電極8に直流電源lOの正極を接続
するとともにミ電界液9に浸漬したプラチナよりなる陰
電極11を直流電源10の負極に接続する。
Then, the positive electrode of a DC power supply 1O is connected to the above-mentioned positive electrode 8, and the negative electrode 11 made of platinum immersed in the electrolyte 9 is connected to the negative electrode of the DC power supply 10.

この状態で、第1図(d)に示すようにSiO□膜4の
上方から可視光を照射すると、その表面に空乏層12が
発生し、電界液9に浸されたその半導体素子形成領域6
においては、その表面から酸化が進行してGa2O3,
AsO□の酸化膜13が生成され、時間の経過とともに
その厚みが増し、これにともなって空乏1112がバッ
ファ層2方向に移動することになる(第1図(e))。
In this state, when visible light is irradiated from above the SiO□ film 4 as shown in FIG.
, oxidation progresses from the surface to Ga2O3,
An oxide film 13 of AsO□ is formed, and its thickness increases with the passage of time, and as a result, the depletion 1112 moves toward the buffer layer 2 (FIG. 1(e)).

ところで、SiO□膜4により覆われたn型半導体膜1
の領域ではその表面が酸化せず、その下の空乏W412
がバッファM2まで達することはないために、この領域
を通して各半導体素子形成領域6に常時電流を供給でき
ることになる。
By the way, the n-type semiconductor film 1 covered with the SiO□ film 4
In the region, the surface is not oxidized and the depletion W412 below it is
Since the current does not reach the buffer M2, current can be constantly supplied to each semiconductor element forming region 6 through this region.

この結果、n型半導体膜lのうち膜厚が薄い領域Bにお
いては、その下の空乏層12により電流の流れが遮られ
て陽極酸化が停止する場合であっても、SiO□膜4が
形成された領域を通って陽電極8から膜厚の厚い領域A
に電流が流れることになり、その領域Aにおける陽極酸
化は、空乏層12がバッファ層2に達するまで行われる
ことになる(第1図(f))。
As a result, in the thin region B of the n-type semiconductor film l, even if the current flow is blocked by the depletion layer 12 below and the anodic oxidation is stopped, the SiO□ film 4 is formed. from the positive electrode 8 through the thick region A.
A current flows through the region A, and anodic oxidation is performed in the region A until the depletion layer 12 reaches the buffer layer 2 (FIG. 1(f)).

したがって、素子形成領域6における酸化されないn型
半導体膜1の膜厚は均一となる。
Therefore, the thickness of the unoxidized n-type semiconductor film 1 in the element formation region 6 becomes uniform.

この段階で、n型半導体膜1上層の酸化膜13を20%
濃度の塩酸によって選択的に除去するとともに、SiO
□IFJ4をフォトエチング法等により除去する(第1
図(g))。
At this stage, the oxide film 13 on the n-type semiconductor film 1 is reduced to 20%.
While selectively removing with concentrated hydrochloric acid, SiO
□Remove IFJ4 by photo etching method etc. (first
Figure (g)).

陽極酸化により膜厚が均一化されたGaAs n型半導
体膜1では、キャリア分布が均一になるため、この上に
AuG5/Ni/Auによってソース、ドレイン電極を
形成し、^lによってゲート電極を接合すれば、特性の
均一なGaAsショットキー接合型のFETが形成され
ることになる。
In the GaAs n-type semiconductor film 1 whose film thickness has been made uniform by anodic oxidation, the carrier distribution becomes uniform, so source and drain electrodes are formed using AuG5/Ni/Au on this film, and a gate electrode is bonded using ^l. In this way, a GaAs Schottky junction FET with uniform characteristics can be formed.

なお、この実施例では、半導体素子形成領域6の周囲に
絶縁膜を形成して陽極酸化をするものであるが、半導体
素子形成領域6と配線形成領域を含む半導体回路形成領
域の周囲に絶縁膜を形成して半導体回路形成領域を陽極
酸化してもよい。
In this embodiment, an insulating film is formed around the semiconductor element formation region 6 and anodized. However, an insulating film is formed around the semiconductor circuit formation region including the semiconductor element formation region 6 and the wiring formation region. The semiconductor circuit forming region may be anodized by forming a semiconductor circuit forming region.

(b)本発明のその他の実施例の説明 上記した実施例は、n型半導体膜l中の不純物濃度が均
一な場合について説明したが、不純物濃度が不均一に形
成されたn型半導体膜を陽極酸化する場合には、第3図
(a)に示すように、陽極酸化の際にn型半導体膜21
に発生する空乏層25の厚さは不純物濃度が高い領域C
では薄くなるため、第3図(b)に示すように陽極酸化
される深さが増して酸化膜26が厚くなり、不純物濃度
が薄い領域りに比べて酸化されない膜の厚さが薄くなる
(b) Description of other embodiments of the present invention In the embodiments described above, the case where the impurity concentration in the n-type semiconductor film l is uniform is explained. In the case of anodic oxidation, as shown in FIG. 3(a), the n-type semiconductor film 21 is
The thickness of the depletion layer 25 generated in the region C where the impurity concentration is high is
Therefore, as shown in FIG. 3(b), the depth of the anodic oxidation increases and the oxide film 26 becomes thicker, and the thickness of the unoxidized film becomes thinner than in the region where the impurity concentration is low.

この結果、陽極酸化を終えた状態では第3図(c)に示
すように、半導体素子形成領域または半導体回路形成領
域のn型半導体膜21の膜厚が各領域毎に不均一となる
が、そのキャリア数は面方向に対してほぼ均一に分布す
ることになるため、ここに形成される半導体装置の動作
特性を均一にすることが可能になる。
As a result, as shown in FIG. 3(c) after anodization, the thickness of the n-type semiconductor film 21 in the semiconductor element formation region or the semiconductor circuit formation region becomes non-uniform in each region. Since the number of carriers is distributed almost uniformly in the plane direction, it is possible to make the operating characteristics of the semiconductor device formed here uniform.

なお、図中符号22はバッファ層、23は半絶縁性半導
体基板、24はSiO□膜、28は陽電極を示している
In the drawing, reference numeral 22 indicates a buffer layer, 23 indicates a semi-insulating semiconductor substrate, 24 indicates a SiO□ film, and 28 indicates a positive electrode.

ところで1、以上述べた2つの実施例は、膜厚が不均茅
純物濃度が不均一な場合について説明したが、双方とも
不均一な場合にも同様な現象が生じ、不純物の分布は面
方向に対してほぼ均一となる。
By the way, 1. In the above two embodiments, the case where the film thickness is non-uniform and the impurity concentration is non-uniform is explained, but the same phenomenon occurs even when the film thickness is non-uniform, and the impurity distribution is uniform. It becomes almost uniform in the direction.

また、上記した実施例では、半導体素子または回路を形
成しない領域をSi0g膜4.24により覆ったが、窒
化膜、PSG膜、フォトレジストその他の絶縁膜により
覆うこともできる。
Further, in the above-described embodiment, the region where no semiconductor element or circuit is formed is covered with the SiOg film 4.24, but it can also be covered with a nitride film, a PSG film, a photoresist, or other insulating film.

さらに、上記したn型半導体層l、21をGaAsによ
り形成したが、^lGaAs、 InGaAs等の化合
物半導体により形成する場合にも上記実施例を適用する
ことができる。
Furthermore, although the n-type semiconductor layers 1 and 21 described above are formed of GaAs, the above embodiments can also be applied to cases where they are formed of compound semiconductors such as GaAs and InGaAs.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、半導体膜のうち素子
形成領域又は回路形成領域の周囲を絶縁膜により覆うと
ともに、この絶縁膜を電極接続位置に延設するようにし
たので、絶縁膜が形成された領域の半導体膜を通して複
数の半導体形成領域に常時M、流を流すことができるこ
とになり、陽極電極の接続位置を任意としても、陽極酸
化を確実に行うことが可能になる。
As described above, according to the present invention, the periphery of the element formation region or the circuit formation region of the semiconductor film is covered with an insulating film, and this insulating film is extended to the electrode connection position, so that the insulating film is It is possible to constantly flow a current M to a plurality of semiconductor formation regions through the semiconductor film in the formed region, and it becomes possible to perform anodization reliably even if the connection position of the anode electrode is arbitrary.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(g)は、本発明の一実施例を断面で示
した工程図、 第2図(a)、(b)は、半導体ウェハの一例を示す平
面図と断面図、 第3図(a)〜(c)は、本発明のその他の実施例を断
面で示した工程図、 第4図(a)〜(d)は、従来方法の第1の例を示す断
面図、 第5図(a)、(b)は、従来方法の第2の例を示す断
面図である。 (符号の説明) 1.21・・・n型半導体l!J(導電性半導体膜)、
2.22・・・バッファ層、 3.23・・・半絶縁性半導体基板、 4.24・・・Si0g膜(絶縁It’り、5・・・レ
ジスト、 6.26・・・半導体素子形成領域、 7・・・電極接続領域、 8・・・陽電極、 9・・・電界液、 10・・・直流電源、 11・・・陰電極、 12゜ 25・・・空乏層、 13・・・酸化膜。
FIGS. 1(a) to (g) are process diagrams showing an example of the present invention in cross section; FIGS. 2(a) and (b) are a plan view and a sectional view showing an example of a semiconductor wafer; FIGS. 3(a) to (c) are process diagrams showing other embodiments of the present invention in cross section, and FIGS. 4(a) to (d) are sectional views showing a first example of the conventional method. , FIGS. 5(a) and 5(b) are cross-sectional views showing a second example of the conventional method. (Explanation of symbols) 1.21...n-type semiconductor l! J (conductive semiconductor film),
2.22...Buffer layer, 3.23...Semi-insulating semiconductor substrate, 4.24...Si0g film (insulating It' layer), 5...Resist, 6.26...Semiconductor element formation Region, 7... Electrode connection region, 8... Positive electrode, 9... Electrolyte, 10... DC power supply, 11... Negative electrode, 12°25... Depletion layer, 13... ·Oxide film.

Claims (1)

【特許請求の範囲】 基板上に形成した導電性半導体膜における素子形成領域
または回路形成領域の周囲を絶縁膜により覆うとともに
、 該絶縁膜を、上記導電性半導体膜における電極接続領域
の近傍まで延設し、 該電極接続領域に電極を接続して上記導電性半導体膜の
上記素子形成領域または回路形成領域の表面を陽極酸化
し、上記導電性半導体膜の上記素子形成領域または回路
形成領域を薄層化する工程を有することを特徴とする半
導体装置の製造方法。
[Claims] Covering the periphery of an element forming region or a circuit forming region in a conductive semiconductor film formed on a substrate with an insulating film, and extending the insulating film to the vicinity of an electrode connection region in the conductive semiconductor film. connecting an electrode to the electrode connection region, anodizing the surface of the element formation region or circuit formation region of the conductive semiconductor film, and thinning the element formation region or circuit formation region of the conductive semiconductor film; A method for manufacturing a semiconductor device, comprising a step of layering.
JP3216189A 1989-02-09 1989-02-09 Manufacture of semiconductor device Pending JPH02210831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3216189A JPH02210831A (en) 1989-02-09 1989-02-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3216189A JPH02210831A (en) 1989-02-09 1989-02-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02210831A true JPH02210831A (en) 1990-08-22

Family

ID=12351214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3216189A Pending JPH02210831A (en) 1989-02-09 1989-02-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02210831A (en)

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