JPH02214211A - Data output circuit - Google Patents

Abstract

PURPOSE:To output an output of a selector while keeping simultaneous state of each channel by connecting an intermediate register so as to be latched by the output of the selector. CONSTITUTION:An LEN signal output means 52 outputs an LEN signal for a period when a last channel is outputted as a data updatable period and an RLD signal representing the timing just after data of all channels having the simultaneous state are arranged and the LEN signal are used for the adjustment. That is, a selector 50 selects either the RLD signal or the LEN signal to give a latch timing to the intermediate register, when the LEN signal is active at the output of the RLD signal, the RLD signal is selected and when the LEN signal is not active, the LEN signal is selected. Thus, the inside and the outside of the device are synchronized and simultaneous performance of each channel is kept.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a data output circuit suitable for a device in which data of multiple channels is sequentially and periodically output from a single port based on internal timing of the device. Regarding.

Analog-digital (A/D) with a resolution of 14 bits or more when processing audio signals digitally
A converter is required. In recent years, A/D converters in this field have been replacing successive approximation type ones with oversampling type ones, which are suitable for high-density integration.This type of device is equipped with a digital filter in the final stage. However, in order to reduce the circuit scale, this digital filter is generally shared by both the left and right channels. Therefore, the conversion results of both channels are periodically output so that the respective outputs are updated alternately.

The present invention refers to a data output circuit particularly suitable for such devices.

[Conventional technology]

FIG. 4 is a diagram showing an example of a typical oversampling type A/D converter 200. The analog signals of both channels are converted into digital signals of one to several bits by ΔΣ converters 201 and 202 (digital low-pass filter 20
In step 3, high frequency components are removed, resulting in a 16-bit digital signal, which is stored in result registers 101 and 10, respectively.
2. The data stored in the result registers 101 and 102 is based on the signal CHC applied from outside the device.
The signal is multiplexed by a multiplexer 121 based on the signal and 5CLK, converted into a serial signal by a shift register 122, and output.

[Problem to be solved by the invention]

Here, the ΔE converters 201 and 202, the digital low-pass filter 203, and the result registers 101 and 102 are connected to the frequency divider 20 based on the mask clock MCLK supplied from the outside.
It is driven by a control clock formed by 4.

On the other hand, the multiplexer 121 and shift register 122 use the channel clock CHCK supplied from outside the device.
and a signal generated by the timing generation circuit 205 based on the shift clock 5CLK.

The reason for this is to synchronize data transmission and reception with devices other than the A/D converter 200, such as a digital signal processor (DSP), so CHCK and 5CLK are frequency-divided into MCL by other devices. It is made by Therefore, even though the basic clock is common, the clocks are divided independently, so the phase relationship is not guaranteed, and the problem arises that the simultaneity of the left and right channel signals cannot be maintained.

FIG. 5 is a diagram for explaining this relationship in detail. The (1) column and (2) column are the result registers 101, respectively.
and 102, and the (3) column and (5) column are diagrams showing two timings of the C) ICK signal. Here, it is assumed that an external request is made to start outputting L channel data at the rising edge of the CHCK signal, and starting outputting R channel data at the falling edge of the CHCK signal. Then, (1) (2
) The data output based on the relationship between the signals in (3) and (3) is as shown in column (4), and in this case, Ln and RnLn+
It is assumed that a pair is formed such as l and Rn+l, and simultaneity is maintained. The phase relationship between the inside and outside of the device is (
1) If the relationship between the signal in (2) and (5) exists, the output will be as shown in column (6), and Ln -1, Rn, and Ln
A problem arises in that a pair is formed like Rn+1(7) and the simultaneity of both channels cannot be maintained.

Therefore, it is an object of the present invention to provide a system that allows data to be transmitted and received even when the phase in which multiple channels of data are formed within a device is not guaranteed to match the phase in which data is transmitted and received between devices.
An object of the present invention is to provide a data output circuit capable of outputting each channel while maintaining simultaneity.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of a data output circuit according to the present invention. In this figure, the data output circuit of the present invention includes the same number of result registers 10 that are sequentially and periodically updated with data from a plurality of channels based on the internal timing of the device 20, and all result registers within the period. RLD indicating the timing immediately after 10 was updated
RLD signal output means 16 that outputs a signal; and output means 12 that selects any one of the result registers 10 at a timing synchronized with an external signal 14 from outside the device and sequentially and periodically outputs it to the outside of the device. a data output circuit for a device 20 comprising: an equal number of intermediate registers 50 connected to latch and supply the outputs of the plurality of result registers 10 to the output means 12;
and L representing the period during which data can be updated based on the external signal 14.
LEN signal output means 52 that outputs the EN signal, and the LEN signal at the timing when the RLD signal is output.
Status check means 54 that latches and outputs the signal status
and a selector that selects and outputs the RLD signal while the state check means 54 latches the on state of the LEN signal, and selects and outputs the LEN signal while the state check means 54 latches the off state. 56, and is characterized in that it is connected so that the intermediate register 50 is latched by the output of the selector 56.

[For production]

The LEN signal output means 52 outputs the LEN signal during a period during which data can be updated, for example, during the output of the last channel, and the RLD signal representing the timing immediately after the data of all channels with simultaneous data is collected and this LEN signal are output. Adjustments are made with. That is, the selector 56 is R
Either the LD signal or the LEN signal is selected to provide the latch timing to the intermediate register, but if the LEN signal is active when the RLD signal is output, the RLD signal is selected; if it is not active, the RLD signal is selected. L
EN signal is selected. By doing so, the internal and external parts of the device are synchronized and the synchronization of each channel is maintained.

〔Example〕

FIG. 2 is a circuit diagram showing one embodiment in which the data output device according to the present invention is applied to a data output circuit of a 16-bit two-channel oversampled A/D converter;
Figures A and 3B are time charts in which the states of signals at each section indicated by A- in Figure 2 are shown in columns (A) to (K), respectively, and are diagrams for two cases. Second
In the figure, the data of the channel and R channel output from the digital filter 203 are respectively stored in the result register 101.
and 102, and are further time-division multiplexed in a multiplexer 121 via intermediate registers 501 and 502, respectively, converted into a serial signal in a 16-pit shift register 122, and output. Also, from outside the device, the MC, which serves as the basic clock for the entire system,
5CLK (column (B) in Figure 3), which determines the output timing for each bit of serial data, and CHCK (Figure 3 (A)), which determines whether the data is L channel data or R channel data. ) column) is supplied. The signal RLD output from the RLD signal output means 16 in FIG. 1 corresponds to the latch signal (column (F) in FIG. 3) for the result register 102 that is latched later than the result register 101 in FIG. .

The LEN signal output hand 52 in FIG.
21.52? , 528 , AND gate 522 , E
This is realized by an OR gate 523, a counter 525, and a NANO gate 526. Here flip flop 5
27.degree. 528 and NANO gate 526 constitute a circuit for forming a signal that resets the value of counter 525 (column (D) in FIG. 3) to 0 at the rise of CHC.

The counter 525 is counted up at the rising edge of 5CLK. The input of the FOR gate 523 is 2 of the counter.
The 2nd and 23rd digit outputs are connected, and the ANDN gate 522 outputs the 2nd and 2nd digit outputs of the counter.
Since 4-digit output is connected, AND game) 522
The output is that the digits 22 and 23 of the counter are 0 and 1 or 1 and 0.
And when the 24th digit is 1, that is, when it is 20 to 27, it becomes H. Output of flip-flop 521 (Fig. 3 (
Column E) becomes 1 during a period delayed by one clock, that is, when the counter value is between 21 and 28.

The state checking means 54 in FIG.
1, the selectors 56 are each realized by selectors 561.

NAND gate 208 and flip-flop 206 form a signal for loading data into shift register 122. Since the 2° to 24 digit output of the counter 525 is connected to the input of the NANO gate 208,
Its output becomes L during the period when the value of the counter 525 is 15 or 31, and the inverted output of the flip-flop 206 (column (J) in FIG. 3) is delayed by one clock when the value of the counter 525 is 16 or O. It becomes H. The switching signal for multiplexer 121 is provided by flip-flop 20.
The non-inverted output of the flip-flop 207 is connected to the non-inverted output of the flip-flop 207, which has the non-inverted output of the flip-flop 207 as the clock input, and the ['HCK signal as the data input.

Therefore, at the falling edge of the signal for loading data into the shift register 122, the CHCK signal is sometimes high, and sometimes becomes high (column (K) in Fig. 3).
.

Figure 3A shows a low level at the rise of the RLD signal (column (F)).
This is a timing chart when the EN signal (column (E)) is H.
This is a timing chart when the

First, to explain FIG. 3A, the RLD signal (F)
R channel data is set in the result register 102 in synchronization with the falling edge of , and the data is determined at the rising edge (H). At this time, it is assumed that the data of the channel at the same time has already been determined in the result register 101 as well. At this time (when RLD (F) rises), L
Since EN (E) is H, the flip-flop 541
The inverted output of is L, and the selector 501 selects the 8-man power, that is, the RLD signal (F). Therefore, the output (G) of the selector 561 changes at almost the same timing as the RLD signal (F). Then, RLD signal (F
) at the rising edge of intermediate registers 501 and 502
Data of the same time channel and R channel are respectively set in (I).

Since this timing is necessarily located in a certain period when the CHCK signal (A) is active, the multiplexer 12 is controlled by the multiplexer switching signal (K) and the data load signal (J).
1 Furthermore, data is loaded into the shift register 122 in the correct order and output (column (C) in FIG. 3A).

Next, to explain FIG. 3B, RLD signal (F)
Since LEN (E) is set at the rising edge of A, the inverted output of the flip-flop becomes H, and the selector 501
Select the input, ie, the LEN signal (E). Therefore, the output (G) of the selector 561 changes at the same timing as the LEN signal (E). Then, if the difference between the time when data is loaded into the result register 101 and the time when data at the same time is loaded into the result register 102 is sufficiently smaller than the width of the LEN signal (E), the LEN signal (E) ) will no longer interrupt, so data at the same time is always set in intermediate registers 501 and 502. - Regarding the relationship with the outside, the rise time of the LEN signal is always CHCK.
Since the signal (A) is for a certain period, it is correctly output (C) as in the case of FIG. 3A.

〔Effect of the invention〕

As described above, according to the present invention, the simultaneity of each channel is maintained regardless of the relationship between the phase of data of multiple channels output inside the device and the phase of data requested from outside the device. A data output circuit capable of outputting data is provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIGS. 3A and 3B are timing diagrams showing the operation of the circuit in FIG. 2 in two cases. 4 is a diagram showing an example of an A/D converter using an oversampling method, and FIG. 5 is a diagram for explaining problems with the conventional method. In the figure, 101, 102... result register, 121... multiplexer, 122... shift register, 501, 502... intermediate register, 525... counter.

Claims (1)

[Claims] 1. The same number of result registers (10) that are sequentially and periodically updated with data of multiple channels based on internal timing of the device (20), and all result registers within the period. (10) RLD signal output means (
16), and an output means (12) that selects any one of the result registers (10) at a timing synchronized with an external signal (14) from outside the device and sequentially and periodically outputs it to the outside of the device. a data output circuit for a device (20) comprising an equal number of intermediate registers (50) connected to latch and supply the outputs of the plurality of result registers (10) to the output means (12); and a LEN signal output means (52) for outputting a LEN signal representing a period in which data can be updated based on the external signal (14);
Status check means (5) that latches and outputs the signal status
4), while the state check means (54) latches the on state of the LEN signal, selects and outputs the RLD signal;
The selector (56) selects and outputs the LEN signal while the off state is latched, and the selector (56) selects and outputs the LEN signal.
6) A data output circuit characterized in that the intermediate register (50) is connected so as to be latched by the output of the data output circuit.