JPH02214314A - Bias circuit - Google Patents

Abstract

PURPOSE:To regulate a drain voltage of each FET with one variable resistor with well balance simultaneously while keeping a drain current constant by supplying the drain current from a constant current source. CONSTITUTION:A transistor(TR) 1 and a constant current elements IS1 are connected to an FET1, a drain current of the FET1 is decided by the constant current element IS1 and the drain voltage of the FET1 is set by the regulator of the base voltage of the TR 1. The emitter of the TR 1 connects to a drain of the FET1 and a collector is connected to a gate of the FET1 and a prescribed voltage is fed to the base. Moreover, the constant current element IS1 is provided between the connecting point of the drain of the FET1 and the emitter of the TR 1 and a power supply and a prescribed current is supplied. Let the base current of the TR 1 be VB1, then the drain voltage VDS of the FET1 is made constant. Moreover, the drain current IDS is constant depending on the constant current source IS1. In such a case, the gate voltage VGS of the FET1 is controlled automatically by the TR 1 so that the drain voltage VDS of the FET1 reaches the said setting value.

Description

[Detailed Description of the Invention] [Summary] Regarding a bias circuit for a field effect transistor (FET), the present invention provides a bias circuit in which the drain voltage can be set independently while keeping the drain current of the FET constant, and there are few adjustment points. In a field effect transistor (hereinafter abbreviated as FET), the emitter is connected to the drain of the FET, the collector is connected to the gate of the FET, and a constant voltage is supplied to the base. A constant current element is provided between a connection point between the drain of the FET and the emitter of the transistor and a power supply, and the constant current element determines the drain current of the FET and adjusts the base voltage of the transistor to control the FET. Configure by setting the drain voltage of .

(Industrial Application Field) The present invention relates to a bias circuit for a field effect transistor (FET), and more particularly to a bias circuit for an FET for matching characteristics of a plurality of FETs.

In the case of a balanced amplifier, which splits the input into two and amplifies each using an FET, then synthesizes the respective outputs to obtain the desired output, or splits the input into two and inputs one to a mixer to perform frequency conversion. , when monitoring the input level of a mixer FET by measuring the output of the other, it is necessary to match the outputs of the two FETs, but in this case adjustment is performed using the drain voltage V D of the FET.
This is done by setting the S r drain current to 10 g.

At this time, there is a need for a bias circuit that can keep the drain current has constant and vary the drain voltage VDS independently of IDS, and that requires as few adjustment parts as possible.

[Conventional technology]

FIG. 3 shows an example of the configuration of a conventional balanced amplifier.

The input high frequency signal is branched into two by the hybrid H1 and amplified by FETs, FETz, respectively. FET,,FET
The respective outputs of t are combined in a hybrid Ht to produce the desired output. In this case FET+, F
ET! In each bias setting circuit consisting of a resistor R1, a variable resistor VR, and a resistor R2, a variable resistor VR provided in the gate circuit of Each drain voltage vns can be set by setting each to a predetermined value and adjusting variable resistors VR, VR4 provided in the drain circuit.

The circuit shown in FIG. 3 has the following various problems.

(1) In order to set the drain current tos, the gate voltage VaS must be adjusted. FETs have variations and often require adjustment,
The drain current 103 must be measured, and adjustment is troublesome.

(2) Since variable resistors are expensive, it is not preferable to use a large number of them.

(3) When a large signal is input, the gate current is 1. s flows, the gate voltage ■G3 changes, and therefore the drain current ■.

, changes. Particularly in the case of a mixer, in order to keep the amplified output level constant, the local oscillator input power is often applied until it reaches saturation, but in this case, if the main level of the oscillator changes due to temperature changes, etc., the gate current will increase. 8. Gate voltage■
, 3. The drain current ID3 also changes, and fluctuations in the output level of the oscillator may be amplified instead.

Therefore, while keeping the drain current IDS constant,
A bias circuit that can change the drain voltage independently of S has been desired.

FIG. 4 shows an example of a conventional bias circuit, showing the drain voltage VOS and drain current 111 of the FET.
1 shows a bias circuit in which the gate voltage VaS is automatically adjusted so that the voltage VaS remains constant.

In the circuit of FIG. 4, when the positive power supply voltage VD (l is constant and the negative power supply voltage VCC is constant, the FE
Drain voltage of TI■. , is vB=V, ,+0,
Determined by 6 V. The current flowing through resistor R4 is FET.

The current is shunted to the transistor TrI, but most of the current flows to the transistor TrI.
Since the current flows through the FET, the drain voltage VOS of the FET is determined by the resistor R4 when the power supply voltage is constant. At this time, FE
The gate voltage of T,■. , are automatically controlled by the transistors Tr,l so that the drain voltage VOS has the above-mentioned value.

[Problem to be solved by the invention]

In the conventional bias circuit shown in FIG. 4, the drain voltage is ■. , is the power supply voltage■. If D+VG is constant, it is set by the ratio of resistors RI and R2. drain voltage V
When t13 is changed, the drain current ■Ds also changes, but if the drain voltage VI,1 is constant, the drain current I□ is determined independently of the drain voltage VOS by changing the resistor R4. In this way, in the circuit of Figure 4, the drain voltage is ■. , cannot be determined independently of the drain current ll1s.

The present invention aims to solve the problems of the prior art, and provides a bias circuit that can independently set the drain voltage VDS while keeping the drain current IDS of the FET constant and has fewer adjustment points. The purpose is to

[Means to solve the problem]

As shown in FIG. 1, the present invention includes a field effect transistor FET, which includes transistors Tr,
and a constant current element Is, the drain current of the FET is determined by the constant current element r3+, and the drain voltage of the FET is set by adjusting the base voltage of the transistor Tr. Here, the transistor Tri has an emitter connected to the drain of the FET, a collector connected to the gate of the FET, and a constant voltage supplied to the base.

The constant current element ISl is provided between a connection point between the drain of the FET and the emitter of the transistor Tr and a power supply and supplies a constant current.

[For production]

In the circuit shown in FIG.
Let the base voltage of the FET be V□.

The drain voltage V0 is Vos:VH+ + 0. 6 V and becomes constant. Further, the drain current IDS has a constant value determined by the constant current source I□. In this case, FET,
The gate voltage VCS of the FET is automatically controlled by the transistor Tr so that the drain voltage v0 of the FET becomes the above-mentioned set value.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention.

FETI, FETz, FETz,...
are N-channel FETs, FET2, FETt
' is a FET whose characteristics should match the FET.

'pr, Trz, Tr2' --- and R
,,R,.

R2', . . . are FET, , FET, , respectively.
The pnp transistor and resistor that constitute the bias circuit of FET, , . . . , CHD is a constant current diode, and VR is a variable resistor. Tri, Tr4゜Tr4
', . . . are transistors constituting a mirror circuit, and the transistors Tr4, . . . Make the currents of Tr4, . . . match the same.

In the circuit of FIG. 2, FETI, FETI.

The drain voltage of pE'rz,... is the resistance V
The drain current is determined by adjusting R1, and the drain current is determined by the current of the constant current diode CHD.

Therefore, if we use the circuit shown in Figure 2, FETI, FETz,
While keeping the drain currents of F E Tz ', . . . constant, the respective drain voltages can be balanced (changed) simultaneously by adjusting the variable resistor VR.

Note that in the circuit of FIG. 2, the transistor Tr.

Tr4. Instead of using a current mirror circuit consisting of Tr,', . . ., the transistor Tr3 is removed,
The transistors Tr, 7r4, . . . may be replaced with constant current elements. The constant current diode CRD can be replaced with other constant current elements such as FETs, l-transistors, ICs, etc.

Further, the transistors Tr, the resistors R, and the FET may be removed and the cathode of the constant current diode CRD may be grounded, and furthermore, the constant current diode CRD+ may be replaced with a resistor.

Furthermore, in the circuit of FIG. 2, FETI, FET,.

FETt, . . . are P-channel FETs,
Transistor Trt + Tri + Trz
',-"",Tr,.

Tr4. The polarities of the power supplies VDD+VGG may be reversed by using Tr4', . . . as npn) transistors.

Although it is omitted in Fig. 2, when used in a balance amplifier or mixer circuit, for example, each FE
Needless to say, required high frequency circuits are connected to the gate side and drain side of T, respectively.

〔Effect of the invention〕

As explained above, according to the present invention, in the bias circuit in which the gate voltage is automatically adjusted so that the drain voltage of a plurality of FETs becomes a set value, the drain current is supplied from a constant current source. The drain voltage of each FET can be adjusted simultaneously and in a well-balanced manner using only one variable resistor while keeping the drain current constant, and therefore adjustment is easy and economical.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing an example of the configuration of a conventional balance amplifier fi, and Fig. 4 is a diagram showing a conventional balance amplifier fi. FIG. 3 is a diagram showing a configuration example of a bias circuit. FET+, FETz, FETz',...: Field effect transistor (FET) T r lr T r z * T r z r ”
” * T ry + T r 4Tr4 '+ ・
...: Transistor IS+: Constant current source CHD,: Constant current diode VR, ~VR,: Variable resistor RI "" R4+ Rt' + ...: Resistor H
1, H2: Hybrid patent applicant Fujitsu Co., Ltd. Agent Patent attorney Kugobe Tamamushi (1 other person) <Vo. Figure 1 shows the basic configuration of the present invention. Figure 1 shows a conventional balanced amplifier. Figure 3 shows an embodiment of the present invention. Figure 2 shows a conventional bias circuit. Figure 4 shows a conventional bias circuit.

Claims (1)

[Claims] Field effect transistor (hereinafter abbreviated as FET) (FET_
In 1), a transistor (Tr_1) whose emitter is connected to the drain of the FET, whose collector is connected to the gate of the FET, and whose base is supplied with a constant voltage; and the drain of the FET and the emitter of the transistor (Tr_1). a constant current element (IS_1) provided between a connection point and a power supply, the constant current element (IS_1)
In addition to determining the drain current of the transistor (Tr_
A bias circuit characterized in that the drain voltage of the FET is set by adjusting the base voltage of 1).