JPH022177A - Field effect transistor with floating gate - Google Patents

Abstract

PURPOSE:To reduce variation in electric characteristics and to improve producibility by separating a gate into a fixed gate and a floating gate through a low density layer of a polarity opposite to that of a gate at a channel section. CONSTITUTION:At an enhancement type power MOS FET, the gate is separated into a fixed gate PG and a floating gate P at the lower part of a channel through a low density layer N- of a polarity opposite to that of the gate. This separation is made by lamination of a low density layer N- through epitaxial growth. The distance therebetween is at most twice as much as a depletion layer (d). In case of incidence X, light of energy h is directed externally through a floating gate to generate pairs of electron and hole. Electrons flow out to a drain side D and holes flow partially to the fixed gate PG and partially to the floating gate P to generate photocurrent (Iop). The photocurrent (Iop) reaches to the gate P where holes are collected. This increases the potential of the floating gate P to form a channel.

Description

[Detailed description of the invention] A) Industrial application field The present invention relates to field effect transistors.

Compared to bipolar transistors, this transistor (hereinafter simply referred to as FET) controls its output current by gate voltage rather than base current, and is highly efficient, and has recently been used for switching purposes.

It is used in application fields that require high speed, such as inverter drive. For example, it has been used as an efficient driver as the main switching element of a switching regulator or as the main drive section of a PWM inverter circuit.

B) Conventional technology Conventional enhancement type power MOS FET N-ch
An example is shown in FIG.

As shown in Fig. 2, conventionally only fixed gate PG was used.
The channel F portion near the surface is compensated by ion implantation technology or the like to form a low channel concentration (Pch). By lowering this channel concentration (Pch), the sensitivity of the channel F to the gate voltage was improved and high output was obtained. The sensitivity increases approximately in proportion to the channel concentration (Pch).

In the figure, S<-> is the source terminal, D(+)
is the drain terminal, G is the gate terminal, A is the gate electrode, B
indicates a source electrode, C indicates a passivation film, and E indicates an n+ source region.

C) Problem to be solved by the invention However, in the conventional method, compensation is made from a fixed gate concentration (PG) to a channel concentration (Pch).
h, it is difficult to control compensation to Pch, and Pch
Due to concentration variations, there were large variations in gate threshold voltage and on-resistance (RO5ON), as well as large variations in output current.

In this way, in the conventional method, it is necessary to rank the products in production, and it is difficult to aim for the required output.

Furthermore, the response speed was also difficult to control because the gate concentration (PG) could not be increased independently of the channel concentration (Pch).

The present invention was developed in view of the shortcomings of the prior art, and it is possible to improve productivity by aligning the gate threshold voltage to lower the on-resistance, and by aligning the output current as desired. This also guarantees high speed performance due to the high gate concentration. Furthermore, since the floating gate provides high sensitivity, it can also be driven by directly introducing light into the gate.

D) Means for Solving the Problem Therefore, in the present invention, instead of forming a channel by compensating the gate channel portion with the gate, the gate is provided between the fixed gate PG and the floating gate 1-P with a polarity opposite to that of the gate. A high-sensitivity gate drive FET is created by stacking low-concentration layers N-, for example, by epitaxial growth, separating the two, and using the high sensitivity of the floating gate with the floating gate side as the channel side.
That is.

Alternatively, by making light incident on the floating gate P portion of the FET and changing the potential of the floating gate using a photocurrent, it is configured as a light-driven FET that can be directly driven by light.

Here, of course, the floating gate P and the fixed gate PG are used to maintain the withstand voltage, and the gate is set narrower than 2d.

E) Effect With the above configuration, a channel is formed as the potential of the floating gate P changes, but if the floating gate P is a fixed gate)
Since it is not connected to the PG, the threshold voltage is low, and therefore the output current is easy to obtain and has high sensitivity. Further, due to the good controllability of the low concentration layer N- in the channel portion, a device exhibiting excellent controllability can be obtained.

F) Embodiment FIG. 1 shows an example of the N-ch type as an embodiment of the present invention. Although the shape is shown as T-MOS, it is not limited to this, and may be V-MOS or other shapes. In this example, a light-driven type is shown.

In the case of a gate drive type, the gate electrode A may be formed corresponding to the floating gate PK.

In FIG. 1, parts having the same functions as those in FIG. 2 are designated with the same reference numerals. Note that since the passivation film C is of a light-driven type, it is formed of a material that can transmit light here. Furthermore, as clearly shown in Fig. 1, in the enhancement type power MOS FET, the gate is separated from the fixed gate PG and the floating gate PK at the bottom of the channel via a low concentration layer N- having the opposite polarity to the gate. . As described above, this separation can be performed by stacking the low concentration layer N- by epitaxial growth. The distance between them is less than twice the depletion layer d.

Consider the case where there is incident light X in the above.

First, light with an energy circle ν enters from the outside through the floating gate P, creating a hole/hole bear.

Electrons flow to the drain (D) side, holes flow partly to the fixed gate PC, and partly to the floating gate P, causing a photocurrent (
lop).

The photocurrent (lop) reaches the floating gate P, and the floating gate P
At the same time as accumulating K holes, the potential of the floating gate P is increased,
Form a channel.

Then, an electron current flows from the n0 type source region E and flows out to the drain (N-) through the bottom of the channel. At this time,
Some of the holes are absorbed in the channel. Then, the electron current (IE) flowing to the drain (N-) is multiplied and becomes the drain current ID to the drain electrode D.
(+) Reach K.

In this way, an output current of 10 is obtained.

When the incident light X is blocked, the photocurrent (top) stops, and the diffusion potential Vd between the floating gates P and N- quickly recovers as electron-hole pairs recombine within the channel. , the drain current also stops accordingly. Therefore, the higher the floating gate concentration (P), the faster the response. Here, in a normal power MOS FET, the channel Pch and PG) are continuous and connected to the source electrode B, so the sensitivity is low, but in this FET, the floating MOS FET is N
The sensitivity is high because it is separated by -.

According to this example, there are the following advantages.

(i) Floating gate) Low threshold voltage and good sensitivity due to the provision of P.

(11) These sensitivities and threshold voltages can be easily made uniform due to the good controllability of the low concentration layer N-, and the range for each rank is narrow.

(iii) Good sensitivity naturally leads to low on-resistance.

(1) Since the gate concentration (Pc, P) can be taken independently of N-, it can be made high, and the minority carrier combination time in the gate can be shortened, resulting in faster response.

(V) Also, the breakdown voltage can be maintained within the range of the channel length.

(vi) Due to its high sensitivity, it is possible to perform not only gate voltage driving but also optical direct driving by providing a light introduction window in the gate.

If a freewheel diode is attached to (V+D and fixed gate) P, it is also possible to protect from reverse bias between the drain and source.

Note that the present invention is not limited to the N-ch type, but can also be complementary to the P-ch type. Also, these FETs
It is also possible to use it for MOS IC.

F) Effects of the Invention According to the present invention, there is little variation in electrical characteristics;
A useful field effect transistor having various advantages such as improved productivity can also be provided.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part showing an embodiment of the present invention, and FIG. 2 is a sectional view of a main part showing a conventional example. ! 'G...Fixed gate, P...Floating gate, F...
- Channel, N-...Low concentration layer.

Claims (1)

[Claims] 1. A field effect transistor with a floating gate, which is an enhancement type field effect transistor, in which the gate is separated into a fixed gate and a floating gate through a low concentration layer with a polarity opposite to that of the gate in the channel part. type transistor.