JPH0221809Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention is a circuit used to prevent two pulse signals that change in phase with each other from being transmitted when there is a dropout or waveform disturbance. It is related to.

FIG. 1 is a block diagram showing an output circuit of a flowmeter, etc. used for process measurement, etc., and is a block diagram showing the output circuit of a flowmeter, etc. used for process _measurement , _etc .. After connecting open contact A and normally closed contact B, both contacts A and B are driven simultaneously according to the measured flow rate, etc., to generate two pulse signals that change in opposite phase to each other, and then to the waveform shaping circuit WF. Waveform shaping, noise component removal, etc. are performed using the pulse signals S ₁ and S ₂ .

However, due to poor contact or chattering of either or both contacts A and B,
Either one or both of the pulse signals S ₁ and _{S 2} may be missing, or waveform disturbances such as ringing may occur as shown in the waveform diagram in Figure ₂ . etc., there was a drawback that a counter receiving a pulse output with a dropout or waveform disturbance would perform an erroneous counting operation. For this reason, it has conventionally been necessary to provide a low-pass filter (not shown) at the input stage of the waveform shaping circuit WF to remove ringing caused by chatter or the like.

The present invention has the purpose of eliminating all of the above drawbacks of the conventional art, that is, the fault of a counter that receives pulse signals with missing or waveform disturbances and the like, resulting in erroneous counts. are held individually in response to the first clock pulse, and one of the two holding outputs is held in response to a second clock pulse having a frequency that is an integral multiple of 2 of the frequency of the first clock pulse. Both pulse signals in a normal state can be detected by detecting a mismatch between the holding output and either one of the holding outputs, detecting a mismatch between both holding outputs, and then detecting a match between the two mismatch detection outputs. Extremely effective, with a pulse output corresponding only to
A pulse signal error prevention circuit is provided.

The details of the present invention will be explained below with reference to FIG. 3 and subsequent figures showing embodiments.

Fig. 3 is a block diagram, and Fig. 4 is a timing chart showing the waveforms of each part in Fig. 3. Pulse signals S ₁ and S ₂ are generated at a frequency of, for example, 500Hz by a latch circuit LAT as a first holding circuit. In response to the rising edge of the first clock pulse CLK _{1 a} having A mismatch between the two is detected here, and an output e which becomes "H" (high level) when the two do not match is obtained.

On the other hand, one of both holding outputs c and d c
is also applied to one input of the D-type flip-flop circuit (hereinafter referred to as FFC) FF ₁ as the second holding circuit and the EXOR gate G ₂ used as the second gate circuit. In response to the rising edge of the output pulse i, which occurs in response to the rising edge of the second clock pulse CLK ₂ b,
The held output c is held in FFC·FF ₁ , and this held output f is given to the other input of EXOR gate G ₂ .

Therefore, in the EXOR gate _G2 , a mismatch between the held outputs c and f is detected, and when the two do not match, an output g that becomes "H" is obtained.

The outputs e and g are the third gate circuit.
This is applied to the AND gate _G3 , where a match between the two is detected and an output h which becomes "H" when both are "H" is obtained, and this is sent to the FFC/FF as the third holding circuit. ₂ , it is held in response to the rise of the clock pulse CLK ₂ b, becomes the output pulse i, and is sent to the output OUT.

By repeating the above operations,
In FFC/FF ₁ , the current holding output c is
Even when the current holding output c changes from “L” (low level) to “H”, the holding output f remains “L”, and even when the current holding output c changes from “H” to “L”, the holding output f remains “L”. “H”
Therefore, by FFC・FF ₁ , the holding output c
The state immediately before is maintained.

Therefore, the output g of the EXOR gate _G2 becomes "H" only when the current state of the holding output c does not match the previous state, and thereby the pulse signal S
1 repeats "H" and "L".

Furthermore, since the output e of EXOR gate _G1 becomes "H" due to the mismatch between both holding outputs c and d, this confirms that the pulse signals _S1 and _S2 are in opposite phases to each other. It is done.

Therefore, the output h of the AND gate _G3 is "H" on the assumption that the state of the pulse signal S1 is different between the current state and immediately before, and that the pulse signals _S1 and _S2 are in opposite phases. Therefore, the output h is
It corresponds only to the pulse signals S ₁ and S ₂ in the normal state, and omissions and waveform disturbances in the pulse signals S ₁ and S ₂ do not appear in the output h.

However, the output h has a latch circuit LAT to
Spiked pulses may appear due to delay time differences in signal transmission in AND gate _G3 , so the output h is sampled and held according to clock pulse _CLK2b , and the pulse output i from which the spiked pulses have been removed is I am assuming that I will get it.

Note that the above is a case where the configuration is performed using positive logic values, but the same applies to the configuration using negative logic, and the holding output d may be held and held in FFC/FF ₁ and also provided to EXOR gate G ₂ , etc. However, the present invention can be modified in various ways.

As is clear from the above explanation, according to the present invention, when there is a dropout or waveform disturbance in two pulse signals that change in phase with each other, a pulse output with these removed can be obtained. etc., there will be no counting error. Therefore, unlike the conventional method, there is an advantage that there is no need for a low-pass filter for removing disturbances in the waveforms of the two pulse signals that change in phase with each other. Additionally, by monitoring the presence or absence of interruptions in pulse output, it is possible to detect missing pulse signals and disturbances in waveforms, which is highly effective in devices that handle two pulse signals that change in phase with each other. .

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the output circuit of a flow meter, etc. Figure 2 is a waveform diagram of a pulse signal that causes ringing, Figure 3 is a block diagram showing an embodiment of the present invention, Figure 4 is Figure 3. 2 is a timing chart showing the waveforms of various parts in FIG. LAT...Latch circuit, FF ₁ , FF ₂ ...FFC (D
type flip-flop circuit), G ₁ , G ₂ ……EXOR
(exclusive OR) gate, G ₃ ...AND gate,
S ₁ , S ₂ ... Pulse signal, CLK ₁ , CLK ₂ ... Clock pulse.

Claims (1)

[Scope of utility model registration request] a first holding circuit that individually holds first and second pulse signals that change in phase with each other in accordance with a first clock pulse;
and a first gate circuit that detects a mismatch between the two holding outputs corresponding to the second pulse signal, a second holding circuit that holds either one of the holding outputs according to the output pulse, and the holding output. a second gate circuit that detects a mismatch between a held output of the circuit and either one of the held outputs; and a third gate circuit that detects a match between both outputs of the first and second gate circuits. and a third holding circuit that holds the output of the gate circuit in response to a second clock pulse having a frequency that is an integral multiple of 2 of the frequency of the first clock pulse and sends out the output pulse. Error prevention circuit for pulse signals.