JPH02219235A - Manufacture of field effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a field effect semiconductor device free of irregularity of impurity concentration and region length by a method wherein, after a polysilicon layer surface is oxidized for a semiconductor substrate and then the oxidized part is eliminated, impurity is supplied. CONSTITUTION:A semiconductor substrate 1 to which impurity for forming a drain region 5 and a source region 6 is supplied is used] said substrate 1 is subjected to treatment for oxidizing the surface of a polysilicon layer 3. After an oxidized part 3a of the polysilicon layer surface is eliminated, a small amount of impurity is supplied, thereby forming a low concentration impurity region 5a for LDD (lightly doped drain) structure on the end of the drain region 5. In this case, the impurity concentration of the low concentration impurity region is determined only by the impurity amount supplied to the substrate surface. For example, it is easy to supply impurity to the substrate surface by ion implantation so as to exactly obtain a specified amount. Thereby, the irregularity of impurity concentration in the low concentration region can be reduced, and the irregularity of region length also is reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a field effect semiconductor device.

(Prior Art) FIG. 2 (111 is a conventional MOS) transistor (field effect semiconductor device) is shown.

In a MOS transistor, a drain region (N'' region) 51 and a source region (N'' region) 52 are formed on the surface of a semiconductor substrate 50, and an insulating region is formed in a channel region CH between both head regions 51 and 52 of the semiconductor substrate 50. A polysilicon gate electrode 54 is formed through the layer 53, and in addition, a low impurity concentration region (N- region) 51a is formed between the end of the drain region 51 and the channel region CH. A low impurity concentration region (N- region) 52a is also formed between the end of the region 52 and the channel region CH. Therefore, this MOS) transistor is
(Lightly Doped Drain) structure, and characteristic fluctuations caused by hot electrons are suppressed.

The above-mentioned MOS) transistor is manufactured as follows.

First, as shown in FIG. 2 (al), the field oxide film 6
A thin gate oxide film (insulating layer) 53 is formed on the surface of the element forming region A which is surrounded and separated by the field reversal prevention region 62 and the field inversion prevention region 62 .

Next, as shown in FIG. 2 (bl), after forming the polysilicon gate electrode 54, low impurity concentration regions (N- regions) 51' and 52 are formed by ion-implanting impurities (arsenic) in a self-aligned manner. ' to form.

After this, as shown in FIG. 2(c), a silicon nitride film 63 is laminated, and as shown in FIG. While forming the sidewalls 64 so that they remain, impurity (phosphorous) is ion-implanted and diffused using the gate electrode 54 and the sidewalls 64 as masks, as shown in FIG. 2 (dl). A region 51 and a source region 52 are formed.After that, by removing the sidewall 64, the MO3I-
A transistor is obtained.

[Problem to be solved by the invention]

The MO3I-transistor described above is provided with a low impurity concentration region for the LDD structure and has a gentle impurity concentration profile, which relaxes the electric field and suppresses characteristic fluctuations caused by hot electrons. Impurity concentration and shape (length) must be strictly controlled. Since this low impurity concentration region also functions as a parasitic resistance, for example, if the impurity concentration is too low, a problem arises in that the on-resistance increases significantly. Therefore, in the low impurity concentration region, it is not enough just to have a low impurity concentration, but the concentration and length must be controlled so that the electric field is relaxed and at the same time the resistance value does not become too high.

However, in the conventional manufacturing method described above, the characteristics of the obtained semiconductor device are not stable due to large variations in concentration and length. This is because, on the one hand, the concentration and length in the low impurity concentration region are greatly affected by the shape of the sidewall, and on the other hand, there is a wide variation in the shape of the sidewall formed by reactive ion etching. This is because variations in the sidewalls directly result in variations in impurity concentration and length.

In view of the above circumstances, it is an object of the present invention to provide a method for manufacturing a field effect semiconductor device with less variation in impurity concentration and region length in a low impurity concentration region for an LDD structure.

[Means to solve the problem]

In order to solve the above problems, a method for manufacturing a field effect semiconductor device according to the present invention uses a semiconductor substrate as shown in FIG.
), a polysilicon layer 3 for forming a gate electrode is formed to cover a region to be a low impurity concentration region for an LDD structure and a channel region, and impurities 4 for forming a drain region and a source region are formed. Using the supplied semiconductor substrate, as shown in FIG. 1(C), the surface of the polysilicon N3 is oxidized on this semiconductor substrate, and then, as shown in FIG. 1(d), After removing the oxidized portion 3a on the surface of the polysilicon layer, a small amount of impurity is supplied to form a low impurity concentration region 5a for the LDD structure at the end of the drain region 5.

As the field effect semiconductor device of the present invention, for example, MO
S) A transistor may be mentioned, but it is not limited thereto. M.O.
S) In the case of transistors, there are also N-channel and P-channel transistors. Furthermore, the semiconductor device may be of a C-MOS (C-MOS) transistor configuration having both N-channel and P-channel types.

As for the method of oxidizing the polysilicon layer, it is preferable that the oxidation rate of the polysilicon layer be faster than the diffusion rate of impurities for forming source and drain regions. Examples of such oxidation methods include low temperature and high pressure steam oxidation.

The low impurity concentration region for the LDD structure generally needs to be between the end of the drain region and the channel region, but the low impurity concentration region may also be formed between the source region and the channel region.

[For production]

In the method for manufacturing a field effect semiconductor device of the present invention, an LDD
Structural low impurity concentration regions are formed by supplying impurities to the area where the oxidized portions of the polysilicon layer have been removed. Therefore, the impurity concentration in the low impurity concentration region is
In fact, it is determined only by the amount of impurities supplied (eg, ion implanted) to the substrate surface. For example, it is easy to supply impurities to the substrate surface in an accurate predetermined amount by ion implantation. Therefore, in the semiconductor device obtained by the present invention, variations in impurity concentration in the low concentration impurity region are reduced.

On the other hand, the length of the low impurity concentration region is determined by the thickness of the oxidized part on the surface of the polysilicon layer (more precisely, the side surface) and the amount of impurity used to form the drain region during oxidation of the surface of the polysilicon layer. Determined by diffusion distance. This is because the low impurity concentration region is a region of the substrate surface below the oxidized portion into which impurities for forming the drain region have not substantially diffused into the region. The precision with which the oxidized parts are removed is also relevant, but this is a problem because the oxidized parts of the polysilicon layer are more easily etched than the non-oxidized parts, making it easier to selectively remove only the oxidized parts. do not have. Therefore, if the thickness of the oxidized part and the diffusion distance can be controlled accurately,
The region length in the low impurity concentration region can be accurately set to a predetermined value, and this can be easily done by setting the oxidation conditions (oxidation temperature, oxidation time, etc.). Therefore, in the obtained semiconductor device, there is little variation in the length of the low impurity concentration region.

〔Example〕

Hereinafter, an example of a method for manufacturing a field effect semiconductor device according to the present invention will be described in detail with reference to FIGS. 1(al to 1e).

First, as shown in Figure 1(a), field oxidation 1u
A gate oxide film 2 is formed on the surface of an element formation region A of a semiconductor substrate 1, which is surrounded by a field reversal prevention region 12 and a field inversion prevention region 12 and is isolated from the region.

Note that the field oxide film 11 and the field inversion prevention region 12 are formed as follows. First, the surface of the semiconductor substrate 1 is covered with a thermal oxide film with a thickness of approximately 500 nm, and a silicon nitride film is laminated on top of this by low-pressure CVD, and this silicon nitride film is patterned to form only the portions that will become element formation regions. The silicon nitride film is left behind. Using the remaining silicon nitride film as a mask, boron implantation and selective oxidation are performed to form field oxide film 11 and field inversion prevention region 12. Next, if the silicon nitride film portion is exposed by etching, the element formation area A is formed.
Can be done.

After forming the gate oxide film 2 in the element formation region A, as shown in FIG. ) 3 to 1p thick
Using this polysilicon layer 3 (and field oxide film 11) as a mask, phosphorus is ion-implanted (supplied) as an impurity 4 for forming source/drain regions.
do.

Subsequently, as shown in FIG. 1c), the surface of the polysilicon N3 is oxidized by low-temperature, high-pressure steam oxidation, and then the oxidized portion 3a formed on the surface of the polysilicon layer is removed using a wet etching method. After that, the first
As shown in Figure Fdl, impurity (arsenic) is supplied to form a low impurity concentration region (N
- regions) 5a and 6a are formed. Note that during low-temperature, high-pressure steam oxidation, the impurity (phosphorous) ion-implanted earlier is diffused and activated to form the drain region (N+ region 5 and source region (N+ region 6). The polysilicon portion that remains after removing the portion 3a is the gate electrode 7.
It becomes.

In the case of low-temperature, high-pressure steam oxidation, the oxidation rate of the polysilicon layer is considerably faster than the diffusion rate of the impurity 4, so the difference in distance is large and a sufficient amount of the low impurity concentration region under the oxidized portion 3a is secured. can do. Of course, methods other than low-temperature, high-pressure steam oxidation may be used to oxidize polysilicon N3.

After that, as shown in FIG. 1, the drain region 5,
By forming an oxide film 2' on the surfaces of the source region 6 and low impurity concentration regions 5a and 6a, an N-channel MOS transistor having a so-called LDD structure is completed.

〔Effect of the invention〕

In the method for manufacturing a field effect semiconductor device of the present invention, an LDD
Since there is little variation in the impurity concentration and region length of the structural low impurity concentration region, semiconductor devices with stable characteristics can be manufactured with a high yield.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are schematic cross-sectional views showing the steps of manufacturing a MOS transistor by an example of the method according to the present invention, and FIGS. 2(a) to 2(e) are
FIG. 2 is a schematic cross-sectional view showing the steps of manufacturing a MOS transistor by a conventional method. 1... Semiconductor substrate) 3... Polysilicon 5... Drain region 6... Source region 2... Gate oxide film (Insulating layer contact 3a... Oxidized portion 5a... Low impurity Concentration region 7...polysilicon gate electrode

Claims (1)

[Claims] 1. In a semiconductor substrate in which a source region and a drain region are formed in the surface portion, a polysilicon gate electrode is formed in a channel region provided between the two regions via an insulating layer, and a polysilicon gate electrode is formed between the end of the drain region and the channel region. In obtaining a field effect semiconductor device in which a low impurity concentration region is formed between regions, a polysilicon layer for forming a gate electrode is formed as a semiconductor substrate to cover the region to be the low impurity concentration region and the channel region. Using a semiconductor substrate to which impurities for forming the drain region and source region have been supplied, the semiconductor substrate is subjected to a process of oxidizing the surface of the polysilicon layer, and then the surface of the polysilicon layer is oxidized. 1. A method of manufacturing a field effect semiconductor device, characterized in that impurity supply for forming the low impurity concentration region is performed after the portion is removed.