JPH0221933U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a pulse width modulation type integral type AD conversion circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation. 10...Pulse width modulation type integrating circuit, 20...
...Counter, 30...Clock generator, 4
0...FIFO memory, 50...Adder, 10...
...Subtractor.

Claims (1)

[Claims for Utility Model Registration] A pulse width modulation type integrating circuit that obtains a pulse width modulation signal corresponding to an input voltage, and a counter clock that counts a counter clock while the pulse width modulation signal is active and is cleared every reference clock. a reference clock to be applied to the integrating circuit, a counter clock having a frequency that is an integral multiple of the frequency of the reference clock, and a clock generator that generates a clear signal synchronized with the falling edge of the reference clock; a FIFO memory that takes in an output and outputs it in a first-in, first-out manner; an adder that adds the output of the counter to other data; and a value that subtracts the output value of the FIFO memory from the value of the output of the adder, and adds that value to the adder. The pulse pulse is composed of a subtracter which is inputted as other data of the device, and AD conversion data corresponding to the input voltage can be obtained from the subtracter, which is updated every cycle of a reference clock. Integral type AD conversion circuit using width modulation method.