JPH02220163A - Selecting device for data transfer request - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to cope with the increase of the number of input/output devices and to prevent a conflict fault due to an element delay from occurring by using a ROM and an address register in place of a gate circuit and an FF. CONSTITUTION:The data transfer requests given from the input/output devices 10-1n are selectively outputted to a data transfer processing circuit 2 via a data transfer request selector consisting of a ROM 3, an address register 4, and a register control circuit 5. Thus the circuit constitution is simplified with use of the ROM 3 and the register 4 in place of a gate circuit and an FF. Then it is possible to cope with the increase of the number of input/output devices just with increase of the number of bits and to prevent such a conven tional conflict fault which is caused by an element delay from occurring.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for transferring data from the input/output device with the highest priority when there are competing data transfer requests from input/output devices with predetermined priorities. The present invention relates to a data transfer request selection device that selects a transfer request and selects the data transfer request if there is no conflict among the data transfer requests.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example of this type of data transfer request selection device.

This data transfer request selection device has five input/output devices 11.
It selects the data transfer request from 112, 113. has been done.

The priority of data transfer requests of the input/output devices 11o to 114 is that the input/output device ff111o has the lowest priority, and the input/output device V4 device 11 has the lowest priority.
1 112.113. T14 is the highest.

The data transfer request receiving FF 134 is the data transfer request WA.
16ah' et al. (7) Input/output WAe11a f) 7'-9
The transfer request is sent from the FF control circuit 15 to the set clock 18.
The data transfer request response signal is held by the data transfer request output line 204 and output to the data transfer processing circuit 12 via the data transfer request output line 204, and a data transfer request response signal is output to the input/output device 114 via the data transfer request response line 174.

The gate circuit 143 outputs the data transfer request of the input/output device 113 that is output to the data transfer request output line 163 when the data transfer request of the input/output device 114 is not output to the data transfer request output line 164 . The data transfer request receiving FF 133 receives the data transfer request of the input/output device 113 output from the gate circuit 143 with a set clock 1.
8 and outputs it to the data transfer processing circuit 12 via the data transfer request output line 203, and outputs a data transfer request response signal to the input/output device 113 via the data transfer request response line 173. The gate circuit 142 connects the input/output device 111 to the data transfer request lines 16a and 163, respectively.
4. When the data transfer request of 113 is not output, the data transfer request of the input/output device 112 outputted to the data transfer request output line 162 is output. The data transfer request receiving FF 132 receives the data transfer request of the input/output device 112 output from the gate circuit 142 using a set clock 18.
It is held by the data transfer request output line 202 and output to the data transfer processing circuit 12, and a data transfer request response signal is output to the input/output device 112 by the data transfer request response 1i1172. When there is no data transfer request from the input/output device 114.113.112 on the data transfer request lines 16a and 163.162, the gate circuit 141 transmits the data of the input/output device ff111.1 output to the data transfer request line 161. Output a transfer request.

The data transfer request receiving FF 131 is a gate circuit 141.
The data transfer request from the input/output device 5f11t output from the input/output device 5f11t is held by the set clock 18, and the data transfer request output 11201 outputs the data transfer request processing circuit 12IC, and the data transfer request response line 171 inputs the data transfer request response signal. Output to the output device 111.

The gate circuit 14° connects data transfer request lines 16a, 16
3, 162.

When there is no data transfer request from input/output device 1a, 13.12.11 to 161, data transfer request line 16o IZ
Outputs the data transfer request of the input/output device ll1o that has output the specified output. The data transfer request receiving FF 13o holds the data transfer request of the input/output device ff11o output from the gate circuit 14o using the set clock 18, and outputs the data transfer request IQ20.

A data transfer request response signal is output to the data transfer request processing circuit 12 through the data transfer request response line 17o, and a data transfer request response signal is output to the input/output IIa 11o.

Note that FFs 13o to 134 for receiving data transfer requests are F.
F, ill I11 reset signal 19 from circuit 15
It is reset by .

[Problem to be solved by the invention]

The conventional data transfer request selection device described above requires a gate circuit and a flip-flop to correspond to the input/output devices, and the gate circuit that can correspond to the input/output @ position decreases the priority level as the number of input/output devices increases. As the amount of hardware increases, contention failures due to element delays occur, and a countermeasure circuit is required, which leads to the disadvantage that the amount of hardware increases further and the circuit configuration becomes more complex.

(Means for Solving the Problems) The data transfer request selection device of the present invention has a priority level assigned to each bit, and inputs the priority level so that the priority level increases sequentially from the lower bits to the upper bits. an address register to which a data transfer request line from an output device is connected, which stores a data transfer request using a set clock and is cleared by a reset signal; a circuit that outputs the set clock and the reset signal; The output is used as an address, and each bit of the data output is connected to the data transfer request output line of each input/output device so that the priority increases from the lower bit to the upper bit, and the data transfer request of the address register is stored. The ROM has a ROM in which data is stored such that only the data transfer request output line corresponding to the most significant bit of the bits in the data transfer request output line is enabled.

[Effect]

By using ROM and address registers instead of gate circuits and FFs, the circuit configuration is simplified, and even if the number of input/output devices increases, it can be handled simply by increasing the number of bits, eliminating contention problems caused by element delays as in the past. There was no occurrence of

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the data transfer request selection device of the present invention, FIG. 2 is a diagram showing data in ROM a,
FIG. 3 is a time chart showing the operation of this embodiment.

In this embodiment, input/output devices 1o, 11.12, . . . 1
It selects a data transfer request from n and outputs it to the data transfer processing circuit 2, and consists of a ROM 3, an address register 4, and a register control circuit 5.

The priority of data transfer requests for input/output devices 'r11 o~1n is input/output device! 11o is the lowest, input/output hvtN11*
The input/output device [1n is the highest. The address register 4 is composed of (n+1) bits, and each of the 0 bit, 1 bit, 2 bit, . . . n bits has a data input/output device a 1 o.

11 12,... Data transfer request line 60 from 1n
．． 61 62. ..., 6n are connected, the data transfer request is set to be stored by the set clock 8 from the register control circuit 5), and cleared by the reset signal 9 (
reset). The ROM 3 uses the output of the address register 4 as an address, and the data output consists of (n+i) bits: 0 bit, 1 bit, 2 bit, 3 bit, .
..., n bits are each data transfer request output line 10o
.

101.102.103, . . . , 10n to the data transfer request processing circuit 2, and transfer request response lines 7o, 71.72.7s, . . . , 7n to the input/output devices 1o, 11.12.1a*..., connected to In. In this ROM 3, as shown in FIG.
~3 has 21 bits, and addresses 4~7 have 22 bits.
``1'' is included only in .... Of the bits in which "1" is stored in the address register 4, "1" is stored only in the data output bit corresponding to the most significant bit.

Next, the operation of this embodiment will be explained with reference to FIG.

It is assumed that after the reset signal 9 is output at time to and the address register 4 is reset, data transfer requests are output from the input/output devices 12, 10 at times t, t2, respectively. When the set clock 8 is output at time t3, a data transfer request is stored in 2 bits and 0 bits of the address register 4. The address of address register 4 based on this storage is rlolJ, that is, “5” in decimal value.
Therefore, rl 00J is output to H in the ROM 37)"3, a data transfer request is output to the data transfer request processing circuit 2 through the data transfer request output line 102, and a transfer request response signal is input through the data transfer request response line 72. It is sent back to the output device 12. As a result, the input/output device 12 turns off the data transfer request signal and starts data transfer.

On the other hand, when the data transfer process of the input/output device 12 ends at time t4, the data transfer request processing circuit 2 outputs a reset signal 9 at time t5 to reset the address register 4. When the next set clock 8 is output at time to, since the data transfer request has been output from the input/output device 1o to the data transfer request line 6o, the data transfer request is stored in bit O of the address register 4, and this data transfer request is stored in bit O of the address register 4. Since there is no other data transfer request, the address of address register 4 is "・
...001", and address "1" from R,0M3
data is read and data transfer request output II 10
o outputs a data transfer request to the data transfer processing circuit 2, and a data transfer request response [17o outputs a data transfer request response signal to the input/output device t! 11o, and thereafter the same processing as in the case of the input/output device 12 described above is performed.

〔Effect of the invention〕

As explained above, the present invention simplifies the circuit configuration by using ROM and address registers instead of gate circuits and FFs, and even if the number of input/output terminals increases, it can be handled simply by increasing the number of bits. This also has the effect of preventing contention failures due to element delays.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the data transfer request selection device of the present invention, FIG. 2 is a diagram showing data in the ROMa of FIG. 1, and FIG. 3 is a time chart showing the operation of this embodiment.
FIG. 4 is a block diagram of a conventional data transfer request selection device. 10-1n...I/O device, 2...Data transfer request processing circuit, 3...ROM, 4...Address register, 5...
Register control circuit, 60-6n...Data transfer request line, 70-7n...Data transfer request response line, 8...Set clock, 9...Reset signal, 10o-10n...Data transfer request output line. Patent applicant [Ippon Denki Co., Ltd. Agent Patent attorney Atsushi Uchi

Claims (1)

[Claims] 1. When data transfer requests from input/output devices with predetermined priorities conflict, the data transfer request from the input/output device with the highest priority is selected, and the data transfer request is If there is no conflict, the data transfer request selection device selects the data transfer request, and the data transfer request selection device selects the data transfer request with one priority corresponding to each bit so that the priority increases sequentially from the lower bit to the upper bit. an address register to which a data transfer request line from an input/output device is connected, which stores a data transfer request using a set clock and is cleared by a reset signal; a circuit that outputs the set clock and the reset signal; The output of the register is used as an address, and each bit of the data output is connected to the data transfer request output line of each input/output device so that the priority increases in order from the lower bit to the upper bit. A data transfer request selection device comprising a ROM in which data is stored such that only the data transfer request output line corresponding to the most significant bit of the stored bits is enabled.