JPH02220471A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To relax a warp of a wafer and to realize a high-density integration by a method wherein a groove which is deeper than the surface of a high- concentration oxygen layer formed inside a semiconductor layer is formed in a substrate and the high-concentration oxygen layer is transformed, by heat treatment, into an oxide buried layer which has been buried in the substrate. CONSTITUTION:A groove 14 which is deeper than the surface of a high- concentration oxygen layer 12 formed inside a semiconductor layer is formed in a substrate 11; the high-concentration oxygen layer 12 is transformed, by heat treatment, into an oxide buried layer 15 which has been buried in the substrate. As a result, a stress caused in a plane orientation of a wafer by a volume swelling of the high-concentration oxygen layer 12 during an annealing operation used to transform the high-concentration oxygen layer 12 into a silicon oxide film is absorbed by the groove 14 used to isolate the high-concentration oxygen layer 12 in each chip. Thereby, a warp of the wafer after the heat treatment is relaxed; a high-density integration can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device in which elements are formed in a semiconductor layer on an insulating layer.

(Prior Art) In recent years, with the dramatic development of semiconductor technology, higher integration and higher performance of semiconductor devices have been promoted. In line with this trend, dielectric isolation technology for devices is being developed for the purpose of improving performance. This dielectric isolation technology minimizes junction 'flffi' and interconnect capacitance to increase speed, and also eliminates the latch-up phenomenon of bulk CMO8.
0n3apphire) technology and Sol (Sili
Con Onln 5rlator) technology, etc.

The Sol technology forms elements in a semiconductor film, such as a silicon film, formed on an insulating film, and is cheaper and has a simpler manufacturing process than the SO8 technology.

It is known that a transistor formed by this Sol technology (hereinafter referred to as "SO2 transistor") has an extremely small parasitic capacitance and high soft error resistance.

In addition, silicon group (hereinafter referred to as rso) formed on the insulating film
It has been reported that by forming M film (referred to as IIJ), the mobility in the transistor is increased and the switching characteristics are improved.

As a manufacturing method of the 801 layer in such Sol technology, for example, SIM OX (Separati
onby I nplatod Qxygen)
There is a law. The 81M0X method is a method in which oxygen ions are implanted into a silicon substrate at high energy, and a buried oxide film is formed by annealing after the implantation. This technique has excellent controllability and reproducibility because it uses ion implantation.

However, when a buried oxide film is formed by annealing after oxygen ion implantation, silicon is heat-treated and oxidized, so that silicon expands in volume. This results in
Stresses were generated in the wafer in the vertical and horizontal directions, causing warpage. Furthermore, due to warping of the wafer,
A large stress was applied to the 801 layer on the buried oxide film.

(Problems to be Solved by the Invention) As described above, in the conventional method of forming the 801 layer by oxygen ion implantation, warpage occurs in the silicon wafer. For this reason, it becomes difficult to perform mask alignment with sufficient accuracy in the step 43 of forming an element after forming the 801 layer. Therefore, this results in a decrease in reliability and a deterioration in yield. Furthermore, if the mask alignment cannot be performed with high precision, fine processing becomes difficult, which becomes a hindrance to increasing the density.

In addition, the warping that occurs on the wafer causes a large amount of stress.
orr, it will affect the characteristics of 5oi8. For this reason, a problem arises in that the characteristics of the element formed in the 801 layer deteriorate.

Therefore, the present invention has been made in view of the above, and its purpose is to improve reliability and yield by alleviating wafer warpage that occurs in semiconductor substrates during heat treatment, and to achieve high-density integration. An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to perform the following steps.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, in a method for manufacturing a semiconductor device in which an element is formed on a substrate having a semiconductor layer provided on an insulating film, a semiconductor layer of the substrate is provided. forming a high concentration oxygen layer in the semiconductor layer by implanting high concentration wI elementary ions into the semiconductor layer, forming a groove deeper than the surface of the high concentration oxygen layer in the substrate, and then performing heat treatment on the semiconductor layer. The method further comprises a step of forming the high concentration oxygen layer into an oxidized buried layer buried in the substrate.

(Function) This invention forms a groove deeper than the surface of the high concentration oxygen layer before heat treating the high concentration oxygen layer formed in the semiconductor substrate, and this groove alleviates stress generated in the substrate during heat treatment. I try to do that.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1<a> to 1(d) show manufacturing steps in a method for manufacturing a semiconductor device according to an embodiment of the present inventionvl'
It is an iFi side view. In the manufacturing method shown in the figure, in the process of forming elements in 8011, grooves are formed along the chip dicing lines on the surface where the annealing process is performed by heat treatment after oxygen ion implantation. I'm trying to relieve stress.

First, oxygen ions are implanted into, for example, a P-type silicon substrate 11 at a concentration of about 10 cr3 at a relatively high acceleration energy of 120 KeV. This allows a high concentration of oxygen to be deposited at a predetermined depth in the silicon substrate 11! ! form 12. (Figure 1(a)).

Next, after applying a photoresist material 13 to the entire surface of the substrate 11, this photoresist material 13 is patterned using an appropriate mask. Thereafter, an etching process is performed using the patterned photoresist material 13 as a mask, and grooves 14 are formed along the dicing lines on the substrate 11, and the depth thereof is set to the high concentration oxygen layer 12.
Form it to the extent that it reaches the bottom. At this time, the range of the oxygen ions injected into the silicon substrate 11 using the above acceleration voltage is approximately 0.3 μm, and the spread width is approximately 0.08 μm, so the depth of the groove 14 is approximately 0.3 μm. In order to reach the bottom of 12, it is sufficient to etch substrate 11 to a depth of about 0.4 μl.

J3, if the width of the opening of the mask is, for example, 1 μl,
The aspect ratio of the groove is 0.4, which does not affect subsequent steps (FIG. 2(b)).

Next, after removing the photoresist material 13,
Annealing is performed in a nitrogen atmosphere at a temperature of about 1%, with a high temperature of 1%! The diatomic layer 12 is made into a silicon oxide film. As a result, the silicon oxide film buried layer 1 is formed in the silicon substrate 11.
5 is formed, and a so rsi 6 of single crystal silicon is formed on top of this buried Wj 15 (FIG. 1(C)).

Next, an element isolation oxide film 17 is formed by a radiation-based element isolation technique, such as the Locos method. after that,
Sol1il 6 is oxidized to form a gate oxide film 18 with a thickness of, for example, 2QrvF1 degree, and polycrystalline silicon is deposited on this gate oxide film 18 to form a polycrystalline silicon model with a thickness of about 0.3μ. form. Subsequently, this polycrystalline silicon film and gate oxide film 18 are buttered,
A polysilicon gate electrode 19 of the SOT transistor is formed on the 801 layer 16 in the element formation region. In succession,
For example, by ion implantation technology, the source region and drain region 20 of the SO transistor are formed, and then wiring is formed to form the SOI transistor (Fig. 1(d)).
).

In such a manufacturing process, high 1111a1%! During annealing to convert the base layer into a silicon oxide film, stress generated in the plane direction of the wafer due to the volume expansion of the high concentration oxygen layer causes the grooves 14 separating the nfar II MMB of each chip.
absorbed by. This causes warping of the wafer and
OIII! ! 16 can be alleviated. Therefore, mask alignment can be performed with sufficient accuracy, and deterioration of device characteristics can also be prevented. As a result, fine processing becomes possible and reliability is improved, making it possible to manufacture semiconductor devices with good yields.

Further, since the grooves 14 are formed on the dicing line of the wafer, an area for forming the grooves 14 in each chip is not required. For this reason,? Forming W14 does not increase the chip area.

FIGS. 2(a) to 2(d) are high-level views of the manufacturing process showing another embodiment of the present invention. The feature of this embodiment is that a groove 14 similar to that of the above-mentioned embodiment is formed in a region to be an element isolation region, and the groove 14 combines stress reduction and element isolation.

That is, the difference from the above-described embodiment is shown in FIG. 2(b).
), by etching the area that will become the element isolation region, a groove 14 is formed in the area that will become the element isolation region, and as shown in FIG. The SOI transistor is formed in the SOXM16 which is separated from the surrounding area. The rest is the same as the embodiment described above, and in FIG. 2, the same parts as in FIG. 1 are designated with the same reference numerals.

In such an embodiment, in addition to being able to obtain the same effect as the above-mentioned embodiment, since elements are separated by 71114, interaction between elements can be extremely reduced. become able to.

Note that the present invention is not limited to the above-mentioned embodiments, and for example, as long as the grooves are intended to relieve the stress applied to the wafer during heat treatment, there are no limitations on the structure such as the formation area and depth. do not have.

[Effects of the Invention] As explained above, according to the present invention, before the high concentration oxygen layer formed in the semiconductor substrate is heat-treated, a groove deeper than the surface of the high concentration oxygen layer is formed, and Since the stress generated in the substrate during heat treatment is alleviated, it is possible to alleviate warping of the wafer after heat treatment. Thereby, it is possible to provide a method for manufacturing a semiconductor device that improves reliability and yield and enables high-density integration.

[Brief explanation of the drawing]

FIG. 1 shows steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a sectional view showing steps in a method for manufacturing a semiconductor device according to another embodiment of the present invention. 11...Semiconductor substrate. 12...High concentration oxygen layer. 13...Photoresist material. 14...Groove. 15...Silicon oxide film buried layer. 16...5OIIPI. 17... Oxide film for element isolation. 18...Gate oxide film. 19...Gate electrode. 20... Source and drain region.

Claims (1)

[Scope of Claims] In a method of manufacturing a semiconductor device in which an element is formed on a substrate having a semiconductor layer provided on an insulating film, highly concentrated oxygen ions are implanted into the semiconductor layer of the substrate to form a high concentration of oxygen ions in the semiconductor layer. forming a groove deeper than the surface of the high concentration oxygen layer in the substrate; and then performing heat treatment to convert the high concentration oxygen layer into an oxide buried layer embedded in the substrate. A method for manufacturing a semiconductor device, characterized by comprising the steps of: