JPH02222294A - Burst signal generating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a burst signal generation circuit incorporated in, for example, a video signal processing circuit for a video camera.

(Prior Art) For example, a color encoder section of a video signal processing circuit of a video camera is provided with an NTSC color burst signal generation circuit.

FIG. 6 shows a conventional color burst signal generation circuit.

Input terminal 1 is supplied with a (B-Y) modulated carrier, and input terminal 2 is supplied with a (RY) modulated carrier. (
After the amplitude of the modulated carrier (RY) is adjusted in the gain control circuit 3, the phase of the modulated carrier is inverted in the adder 5 (B-
Y) Added vector to modulated carrier.

As a result, a burst signal is obtained at the output terminal 6.

FIG. 7 shows the above burst signal generation circuit in more detail.

A (B-Y) modulated carrier is supplied between terminals 1a and 1b, and a (RY) modulated carrier is supplied between terminals 2a and 2b. Terminals 1a and 1b are connected to the bases of transistors Q71 and 072, respectively, which constitute the first differential amplifier DI. The common emitters of transistors Q71 and 072 are connected to constant current source Ill, and transistor Q
The collector of transistor Q71 is connected to power supply line 10, and the collector of transistor Q72 is connected to power supply line 10 via load resistor R73.

On the other hand, among terminals 2a and 2b, terminal 2a is connected to transistor Q74. Q75, terminal 2b is connected to the common base of transistor Q73. Connected to the common base of Q 7B.

Transistors Q73 and Q74 form the second differential amplifier D2.
The transistors Q75 and Q7G constitute a third differential amplifier D3. Transistors Q73 and 074
The common emitter of transistor Q77 is connected to the collector of transistor Q77, and the common emitter of transistors Q75 and Q76 is connected to the collector of transistor 078. Transistors Q77 and Q78 constitute a fourth differential amplifier D4, and the emitters of transistors Q77 and Q78 are connected to a common constant current source 112 through resistors R74 and R75, respectively.

A burst phase control voltage is supplied between the bases of transistors Q77 and Q78 via terminals 11a and llb. On the other hand, the common collectors of transistors Q73 and Q75 are connected to the power supply line 10, and the common collectors of transistors Q74 and Q75 are connected to the power supply line 10.
78 collectors are commonly connected to the power supply line 10 via a load resistor R13.

Transistor Q72. The collector connection of Q74.076 functions as an adder circuit, and the adder output is led out to terminal 5.

The operation of the above circuit will be explained. In the NTSC system, the burst signal has a (B-Y) modulated carrier at 0 degrees (de
g), since the phase is 180 degrees, basically it is sufficient to invert the (BY) modulation carrier and output it. Here, when referring to the phase of a signal, it is referred to with reference to the case where the (B-Y) modulation carrier is set to 0 degrees.

Since the phase of the output burst signal needs to have an appropriate phase relationship with the phase of the modulated chroma signal that is orthogonally modulated with the modulating carrier, the burst signal is created using the modulating carrier, but the modulating chroma Since the signal and the burst signal are generated separately, there is a possibility that they will be out of phase with each other. When this phase shift occurs, it appears as a hue shift on the playback screen. To prevent this, it is necessary to adjust the phase of the burst signal.

First, the (B-Y) modulated carrier supplied between terminals 1a and 1b is derived from the collector of transistor Q72 with phase inversion. Then, for phase adjustment, it is output from the collector of transistor Q74 or Q76 (R
-Y) It is combined with the modulated carrier and phase: A adjustment is performed.

Here, when the phase control voltage between terminals 11a and 11b is at the center (base potential difference of transistors Q77 and Q78 is O), the gains of differential amplifiers D2 and D3 with opposite polarities are the same, and their outputs cancel each other out. Therefore, the output terminal 5 has an inverted output of the (B-Y) modulated carrier,
In other words, a burst signal with a phase of 180 degrees appears.

Here, when the burst phase control voltage is adjusted and the collector current to transistor 077 increases, the (RY) modulated carrier component is vector added to the collector output of transistor Q72, and the phase of the burst signal is shifted. Furthermore, when the collector current of transistor Q78 increases in differential amplifier D4, the inverted component of the (R-Y) modulated carrier is vector added to the collector output of transistor Q72, and the phase of the burst signal is shifted in the opposite direction. .

As a result, the phase of the burst signal is controlled around 180 degrees.

FIG. 8 shows the phase relationship between each modulation carrier and the burst signal in the NTSC system using vectors.

Here, if the constant current source If and the current amount of 12 are equal,
The variable phase amount of the burst signal is ±45 degrees.

Now, let us consider a case where the above-described burst signal generation circuit is used as a PAL system circuit.

This is because video cameras have recently become commercially available products, so there is a demand for circuits compatible with the PAL system. Furthermore, when the burst signal generation circuit is integrated into an integrated circuit, it is more advantageous in terms of cost to manufacture a circuit that can be adapted by switching than to manufacture each circuit separately for each system.

FIG. 9 shows the vector phase relationship of the (B-Y) modulated carrier, (R-Y) modulated carrier, and burst signal in the PAL system.

In the case of the PAL system, the (RY) modulation carrier is inverted every horizontal period (hereinafter referred to as IH), and the burst signal also swivels ±45 degrees around 180 degrees in synchronization with this. Therefore, the center phase of the burst signal for each horizontal period is 180±45 degrees. Therefore, at 90 degrees (R-Y
) When a modulated carrier is input, this output amplitude is expressed as (B
-Y) By combining both signals so as to be the same as the inverted output of the modulated carrier, a burst signal with a phase of 180-45 degrees can be obtained. Furthermore, in order to obtain a 180+45 degree burst signal, when a 270 degree (R−Y) modulated carrier is input, the inverted output of the (B−Y) modulated carrier may be combined.

However, in order to obtain a variable phase amount of ±45 degrees around the center phase of the PAL burst signal, if a circuit as shown in FIG. 7 is used, a constant current source If, 12 When the currents are respectively It and I2 having the same sign, the relationship l<<I2 is required, which is not practical in terms of circuit design. Further, the direction of control by the phase control voltage is performed around a 180 degree vector. For example, if a burst signal with a phase on the 135 degree side is adjusted by +5 degrees, a burst signal with a phase on the 225 degree side will be adjusted to 15 degrees.

Therefore, if there is a steady phase error between the modulated chroma signal and the burst signal, a phenomenon occurs in which when the phase of one burst signal is adjusted, the phase of the other burst signal shifts. However, since the PAL system is originally a system that can cancel the above-mentioned phase error during demodulation, it has the advantage that a small phase error is unlikely to cause a nine-hue shift. Further, if one phase error is canceled during demodulation, the amplitude becomes smaller, but if the original phase error is small, the amplitude reduction rate can also be small.

(Problem to be Solved by the Invention) However, as the number of circuit blocks that separately process the modulated chroma signal and the burst signal increases, the phase error between each circuit increases accordingly. As a signal processing block,
Various additional functions can be considered, such as a circuit with a fader function and a circuit with a negative/positive function.

For example, when looking at the phase per stage of a differential amplifier, if the output load resistance is 10 Ω and the parasitic capacitance at the output point is 0.5 pF, the phase error occurs at 4.43 MHz.
(color subcarrier frequency of the PAL system) is about 8 degrees, which is a large value. For this reason, although the PAL system is resistant to phase errors, 1) For example, in a device such as a video camera that is a signal transmitter, there is a possibility that the burst signal phase of the encoded chroma signal already has a phase error. It should be avoided as much as possible. Furthermore, as the phase error increases, the amplitude reduction rate during demodulation also increases.1For example, a burst signal with a phase error of 10 degrees will be reduced by 1.5%, but if the phase error is 20 degrees, the amplitude will be reduced by 680%. .

As described above, various problems occur when the phase error between the modulated chroma signal and the burst signal becomes large, but to avoid this, it is preferable to perform burst phase adjustment appropriately. However, as described above, although the burst phase adjustment function in the conventional burst signal generation circuit is good for the NTSC system, it is insufficient when applied to the PAL system.

Therefore, the present invention is flexible and can be applied to both the NTSC system and the PAL system.

It is an object of the present invention to provide a burst signal generating circuit which can reduce manufacturing costs and can appropriately obtain the variable amount and variable direction of the burst signal phase symmetrically about the center phase for both types.

[Structure of the Invention] (Means for Solving the Problems) This invention provides a 2Fi modulation carrier for orthogonally modulating a color difference signal, and uses this carrier to obtain a reference center phase burst signal. a second addition circuit that is supplied with one adder circuit and the two types of modulation carriers, and uses the carriers to obtain a correction signal that has a phase different by approximately 90 degrees from the phase of the output burst signal of the first adder circuit; A circuit. Then, the amplitude of the output correction signal of this second adder circuit is controlled by the gain control circuit according to the burst phase control input to obtain an adjustment correction signal, and this:A
A third addition circuit adds the difference correction signal and the output burst signal from the first addition circuit to obtain a final burst signal.

(Function) With the above means, first, since the first and second adder circuits always obtain a signal with a constant phase, it is possible to obtain a stable burst signal with a center phase and a correction signal. Furthermore, the center phase burst signal and the correction signal have a 90 degree relationship. As a result, if the third addition circuit adds the adjusted correction signal with the amplitude of the correction signal adjusted to the burst signal of the center phase, the phase of the output burst signal is always adjusted symmetrically with respect to the center phase. obtained as a signal.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the basic configuration of an embodiment of the present invention. An input terminal 21 is supplied with a (B-Y) modulated carrier, and an input terminal 22 is supplied with a (RY) modulated carrier.

Here, a (BY) modulation carrier and a (RY) modulation carrier are introduced into the first addition circuit 23. Similarly, a (B-Y) modulation carrier and a (R-Y) modulation carrier are introduced to the second adder circuit 22 as well.

The first adder circuit 23 connects the (B-Y) modulated carrier and the (R
-Y) This is a circuit that uses a modulated carrier to obtain a center phase burst signal. Further, the second addition circuit 24 is
This circuit uses a (B-Y) modulated carrier and a (R-Y) modulated carrier to obtain a correction signal with a phase orthogonal to the center phase burst signal (a phase different by 90 degrees).

In the NTSC mode, the first adder circuit 23
) The modulated carrier is inverted and output, and in PAL mode n
The vector calculation output of +-(B-Y)+(R-Y)l is obtained on line (n+1), and +-(B-Y)-(R
-Y)) to obtain the vector calculation output. Therefore, the output vector of the first adder circuit 23 is as shown in FIG. 2(A) or (
E) or (1).

The second adder circuit 24 is (R-Y) in the NTSC mode.
The modulation carrier is derived, and in PAL mode, the vector calculation output of + (B-Y) + (R-Yll is obtained on the n line, and (+(B-Y) = (R-
Y) Obtain the vector calculation output of l. Therefore, the output vector of the second adder circuit 24 is either (B) or (
F) or (J) as shown by the solid line.

The output (correction signal) of the adder circuit 24 of tj12 is supplied to the gain control circuit 25. The gain control circuit 25 has a terminal 2
The gain is controlled according to the burst phase control voltage from 6, and an adjustment correction signal is output.

This 3! The I adjustment correction signal and the burst signal from the first adder circuit 23 are added to an adder 27, and the adder 2
A final burst signal is output from 7 and guided to an output terminal 28. When the gain control circuit 25 performs gain control on the correction signal, the amplitude is controlled within the range shown by the solid line and broken line in (B), (F), or (J) of FIG.

2C shows the center phase of the burst signal in the NTSC mode, which is in the same direction as the vector shown by the solid line in FIG. 2A.

The condition for obtaining this center phase is when the gain in the gain control circuit 25 is zero. However, the same figure (B
), when the correction signal is adjusted within the range of the solid line and the broken line, the phase of the burst signal is varied within the range of the vector shown by the solid line and the broken line in FIG. 2(D).

(G) in FIG. 2 shows the center phase of the n-line burst signal in PAL mode.

This is the same direction as the vector shown by the solid line in FIG. The conditions for obtaining this center phase are as follows:
This is when the gain at 5 is zero.

However, as shown in Figure (F), the correction signal is 3! in the range between the solid line and the broken line. When J is adjusted, the phase of the burst signal is
CH) in FIG. 2 is varied within the range of vectors shown by solid lines and broken lines.

(K) in FIG. 2 shows the center phase of the n-line burst signal in PAL mode.

This is the same direction as the vector shown by the solid line in FIG. The conditions for obtaining this center phase are as follows:
This is when the gain at 5 is zero.

However, when the correction signal is adjusted within the range of the solid line and the broken line as shown in (J) in the same figure, the phase of the burst signal is varied within the range of the vector shown in the solid line and the broken line in (H) of Fig. 2. Ru.

Note that in the PAL mode, the gain control circuit 25 switches the phase of the adjustment correction signal for each IH in accordance with the phase of the burst signal. However, as will be described later, if the phase of the correction signal from the adder circuit 24 is inverted and output for each IH in accordance with the phase of the burst signal, there is no need to switch the phase of the output in the gain control circuit 25. .

As described above, according to this embodiment, the adder circuits 23 and 24 create a burst signal and a correction signal, but they are created using a (B-Y) modulated carrier and a (R-Y) modulated carrier in common. are doing. Moreover, the created burst signal and the correction signal are set to have a phase difference of 90 degrees.

As a result, if the correction signal is amplitude-adjusted in the gain control circuit 25 and then added to the burst signal, the final output burst signal is as shown in (C), (G), (K), and (D) in FIG.
, (H), and (L), phase adjustment of ±45 degrees around the center phase is easily performed. Moreover,
The phases of the burst signals of the n line and the (n+1) line can be adjusted in the same direction by adjusting the gain of the gain control circuit 25 around the determined center phase.

FIG. 3 shows the circuit of FIG. 1 in more detail.

A (B-Y) modulated carrier is supplied between input terminals 21a and 2lb, and (B-Y) is supplied between input terminals 22a and 22b.
RY) modulated carrier is supplied.

The output current of the adder 231 constituting the first adder circuit 23 is converted into a voltage by the load resistor R1 and is output to the output terminal 28. During this derivation, an adjustment correction signal from the gain control circuit 25 is added.

On the other hand, output currents having opposite phase relationships are derived from the adder 241 constituting the second adder circuit 24, and are converted into voltages by load resistors R2 and R3, respectively. Note that resistance R2
The power supply side terminals of R3 and R3 are connected to the power supply line 30 via resistor R4.
It is connected to the.

The output terminal of the resistor R2 is connected to the common base of transistors Q2 and Q3 that constitute the gain control circuit 25. Further, the output terminal of the resistor R3 is connected to the common base of the transistors Ql and Q4. The collectors of transistors Q1 and Q3 are connected to power supply line 30, and transistor Q
The collectors of Q2 and Q4 are connected to one end of resistor R1 as an output node. The common emitters of transistors Q1 and Q2 are connected to the collectors of transistors Q5 and Q7, and the common emitters of transistors Q3 and Q4 are connected to the collectors of transistors Q6 and Q8.

Here, a switching signal that is inverted every IH in the PAL mode is supplied between the common bases of transistors Q6 and Q7 and the common bases of transistors Q5 and Q8. Further, the common emitters of transistors Q5 and Q6 are connected to the collector of transistor Q9, and the common emitters of transistors Q7 and Q8 are connected to the collector of transistor QIO. The emitters of transistors Q9 and QIO are connected to constant current source If via resistors R5 and R6, respectively. A burst phase control voltage is provided between the bases of transistors Q9 and QIO.

Gain control circuit 25 is configured as described above.

Now, assume that the currents flowing through the collectors of transistors Q9 and QIO are equal. Further, the switching signal turns on transistors Q5 and QB, and turns off transistors QB and Q7. Then,
The opposite phase outputs from the collectors of transistors Q2 and Q4 have equal amplitudes, and as a result, the gain control circuit 25
The gain of is zero.

Next, assume that, for example, the current flowing through the collector of the transistor QIO becomes larger than the current flowing through the collector of the transistor Q9. Also, as before, transistor Q5
and QB is on, and QB and Q7 are off. Then, since the collector output of the transistor Q4 has a larger amplitude than the collector output of the opposite output of the transistor Q2, an adjustment correction signal of one phase (positive phase) is obtained as the output of the gain control circuit 25. In this state, if the current flowing through the collector of the transistor QIO is further increased, the amplitude of the adjustment correction signal is increased.

Next, in the above state, when the IH inversion switching signal is switched,
As a result, transistors Q5 and QB are turned off, and QB and Q
7 is turned on. Then, transistor QIO1Q7
, the current in the path of Q2 increases, so the gain control circuit 2
As the output of No. 5, an adjustment correction signal of the other phase (reverse phase) is obtained. In this way, positive phase and negative phase adjustment correction signals are obtained from the gain control circuit 25 for each IH, and the amplitudes of the signals are determined by the transistor Q9. It can be adjusted by the QIO collector current.

Note that the load resistor R1 is simply a resistor for level shifting, and may be a diode, for example.

FIG. 4 shows a specific example of the first addition circuit or the second addition circuit.

A (B-Y) modulated carrier is supplied between the input terminals 1a and lb, and a (R-Y) modulated carrier is supplied between the input terminals 2a and 2b.

Terminal 1a connects terminal 1b to the base of transistor Q12.
is connected to the base of transistor Qll.

Further, the terminal 2a is connected to the base of the transistor Q13, and the terminal 2b is connected to the base of the transistor Q14.

The collectors of transistors Qll and Q13 are connected to one output terminal 41, and the collectors of transistors Q12 and Q14 are connected to the other output terminal 42.

The common emitter of transistors Qll and Q12 is a constant current source! 2 and the collector of transistor Q15. The common emitters of transistors Q13 and Q14 are connected to the collector of transistor Q1B. The common emitters of transistors Q15 and QlB are connected to constant current source I3.

And between the bases of transistors Q15 and 016, N
A switching signal is provided to switch between TSC and PAL modes.

In NTSC mode, transistor Q15 is on,
Transistor 01B is turned off. As a result, the carriers being supplied to the differential amplifier formed by transistors Qll and 014 are taken out from the output terminals 41 and 42. PAL
mode, transistor Q15g is turned off and QlB
turns on. As a result, transistors Qll and Q12
The differential amplifier formed by transistors Q13 and Q14 is driven by constant current source 12, and the differential amplifier formed by transistors Q13 and Q14 is driven by constant current source 12.
3. As a result, two types of modulated carriers are added and output. However, in this case,
Constant current [12 and I3 current must be I2-13.

In the above adder circuit, the collector of the transistor Q15 may be connected to the power supply, but the format shown in FIG. 4 has the advantage that the output DC level can be kept constant.

As described above, according to the system of the present invention, the NTS
A similar burst phase variable range can be obtained in C and PAL modes, and in PAL mode,
The phase control direction for the n line and the (n+1) line is the same, and the burst phase adjustment is also fine. This means that the phase error between the modulated chroma signal and the burst signal phase can be corrected accurately.

Furthermore, in the PAL mode, when the phase control input is at the center, the output of the gain control circuit is always zero, so in the NTSC and PAL modes, the output burst signal of the first adder circuit 23 becomes the final burst signal as it is. is derived to the output terminal as This means that the final burst signal passes through only one stage of the differential amplifier, as shown in FIGS. 3 and 4, and that less phase rotation is required.

The invention is not limited to the embodiments described above.

In the PAL mode, the gain control circuit 26 is provided with means for inverting the burst phase for each IH. However, the phase inversion means may be provided in the second addition circuit 24.

FIG. 5 shows an example in which the second adder circuit 24 is provided with phase inversion means. In this case, as a system, transistors Q5 to Q8 in the gain control circuit are deleted, the common emitters of transistors Ql and Q2 are directly connected to the collector of transistor Q9, and transistors Q3. The common emitter of Q4 may be directly connected to the collector of transistor QIO.

The adding circuit shown in FIG. 5 will be explained. Components similar to those in the circuit shown in FIG. 4 are given the same reference numerals. In this adder circuit, a differential amplifier composed of transistors Q17 and Qlg is connected in parallel to a differential amplifier composed of transistors Q13 and Q14. The collector of the transistor Q17 is connected to the output terminal 41, and the collector of the transistor Q17 is connected to the output terminal 41.
The collector of 8 is connected to the output terminal 42. Common emitter of transistors Q13 and Q14 and transistor Q
The common emitters of transistors Q17 and Qlg are connected to the respective collectors of transistors Q19 and Q20, respectively, and the common emitters of transistors Q19 and Qlg are connected to the collectors of transistors Q19 and Q20, respectively.
Connected to the collector of 1B. And transistor Q
A switching signal that is inverted every IH in PAL mode is supplied between the bases of Q19 and Q20. Thereby, normal phase and negative phase (RY) modulated carriers are alternately derived from the output terminal 42 for each IH.

In the NTSC mode, since transistor Q1B is turned off, the functions of transistors Q19 and Q20 are stopped.

In the above-described embodiments, the emitters are directly connected as the configuration of the differential amplifier, but the dynamic range can be easily increased by inserting an emitter resistor. Further, although the third adding circuit has been described as a type in which one side of the outputs of the differential amplifiers are added together, it may be in a type in which the differential outputs are combined.

Further, in the above description, the burst signal generation circuit has been described as a video camera, but the present invention is not limited to this, and can be applied to all devices on the video transmission side.

[Effects of the Invention] As explained above, the present invention can be applied to both the NTSC system and the PAL system, and the amount and direction of variation of the burst signal phase are centered around the center phase for both systems. and the actual processing stage at the phase control center is one stage of differential amplifier,
Errors around the center phase can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a vector diagram shown to explain the invention in detail,
Figure 3 is a circuit diagram showing the blocks in Figure 1 in more detail;
Figure 4 is a diagram showing a specific example of the addition circuit in Figure 1;
6 is a circuit diagram showing another example of the adder circuit, FIG. 6 is a diagram showing a conventional burst signal generation circuit, FIG. 7 is a circuit diagram showing the circuit in FIG. 6 in more detail, and FIGS. FIG. 9 is a vector diagram shown to explain the operation of a conventional burst signal generation circuit. 23.24... 1st. 2nd adder circuit, 25...gain control circuit, 27... adder circuit. Applicant's representative Patent attorney Takehiko Suzue (G) (N) Figure (H) (L) Output diagram Figure

Claims (1)

[Scope of Claims] A first adding circuit that is supplied with two types of modulation carriers for orthogonally modulating a color difference signal and obtains a reference center phase burst signal using the carriers; and the two types of modulation. a second adder circuit to which a carrier is supplied and uses the carrier to obtain a correction signal having a phase different by approximately 90 degrees from the phase of the output burst signal of the first adder circuit; and an output of the second adder circuit. a gain control circuit to which a correction signal is supplied and whose amplitude is controlled in accordance with a burst phase control input to obtain an adjustment correction signal; and an adjustment correction signal from the gain control circuit and an output burst from the first addition circuit. 1. A burst signal generation circuit comprising: a third addition circuit for adding signals.