JPH02222391A - Still picture video telephone set - Google Patents

Abstract

PURPOSE:To suppress the influence of a noise by changing and controlling a synchronization possible range in a phase locked loop(PLL) by a prescribed sequence, in correspondence to the PLL sensitivity control signal of a desired pattern to be outputted from a CPU by the reception of a picture identification signal. CONSTITUTION:In the PLL, a carrier is recovered out of a received signal and picture data are reproduced from the received signal by utilizing the recovered carrier. In this case, a CPU 5 detects the picture element identification signal, which is sent before a picture element signal, and supplies the PLL sensitivity control signal to a modulation/demodulation part 4 in correspondence to a detected result. Then, the modulation/demodulation part 4 controls demodulation processing in correspondence to the supplied PLL sensitivity control signal. Namely, the synchronization possible range is enlarged usually and after the PLL sensitivity signal is received, the synchronization possible range is controlled according to the prescribed sequence of the PLL sensitivity control signal. Thus, the adverse effect due to the noise can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a still image videophone device that transmits and receives image data as an amplitude-phase modulated image signal, and particularly to a device that suppresses the adverse effects of noise contained in the received signal. Regarding.

[Conventional technology]

There is a demand for a videophone device that simultaneously transmits audio and images using a telephone communication line, but in reality, current telephone communication lines cannot continuously transmit and receive moving images, which requires a huge amount of data. However, still image videophone devices that transmit still images to the other party during a call are being put into practical use.

This still image videophone device is capable of temporarily interrupting a normal voice call and sending a desired still image, such as the speaker's face, a photo screen or a picture depending on the content of the call, or the like. is possible.

Therefore, with such a still image videophone device, it is possible to transmit and receive images over a telephone line, which was previously impossible. In addition, because - number of still images are transmitted and received each time the video telephone device is transmitted and received, the amount of data to be processed is small, and there is an advantage that the video telephone device can be put to practical use easily.

FIG. 5 is a block diagram illustrating a conventional video telephone device, which is shown in the September 1988 issue of Television Technology, which is capable of transmitting still images as described above.

In the figure, (1) is a connection input terminal for external equipment such as a line, (2) is an input terminal for inputting signals from each operation button, (3) is a network control unit, and (4) is for modulating data during transmission. and a modulation/demodulation unit that demodulates data upon reception, and (5) a central control unit that reads the operation signals of each operation button input to the input terminal (2) and controls the modulation/demodulation unit (4) and the image control unit (6). (hereinafter abbreviated as CPU), (7) is an image memory unit, (8) is an A/D converter, (9) is a television camera, (10) is a D/A converter, and (11) is a CRT. ,(
12) is a power source, and (13) is a connection terminal for the power source (12).

Next, the operation will be explained. First, when the caller presses the transmit operation button, the transmit signal is transmitted via the input terminal (2).
PU (5). The CPU (5) receiving the input of this transmission signal transmits the videophone identification signal (dual tone (A)) shown in FIG.
Image data consisting of each information of a control information signal (B) and an image signal (C) is sent out.

The modulation/demodulation section (4) modulates this image data information and sends it to the telephone line connected to the connection terminal (1) via the network control section (3).

Note that the image signal (C) is for reading data stored in the image memory section (7) into the central control section (5) via the image control section (6).

The videophone identification signal (A) is a signal that allows the receiving side to detect that the image signal (C) has arrived after the signal (A). In addition, the above control information signal (
B) includes information such as a frame synchronization signal to synchronize the timing of the received image, an amplitude calibration signal for gain control, and the mode of the image! The image signal (C) is a series of signals corresponding to the brightness of each pixel of the image.

Image data in this conventional example is modulated as follows. In other words, as shown in FIG. 7, the phase is si
There is a first phase of n-curve type and a second phase of -sin curve type which differs in phase by 180 degrees from this, and each phase is formed by signals of a plurality of amplitudes.

Each cycle of the signal having a specific phase and a specific amplitude is made to correspond to a specific brightness.

In this example, there are 8 amplitude values for each phase, totaling 1
There are 6 waveform patterns. The first phase maximum amplitude signal IV corresponds to black, and the second phase maximum amplitude signal #15' corresponds to white. Intermediate signals 11' to '14' correspond to gray of each brightness, respectively.

On the other hand, when receiving an image, a received signal input from the line via the connection terminal (1) is input to the modulation/demodulation section (4) via the network control section (3). The modulation/demodulation section (4) demodulates this signal and provides information to the central control section (5). This is sent as a received image to the image memory (7) via the image control unit (6).
) and is converted into an analog signal by a D/A converter (10) and displayed on a CRT (11).

FIG. 8 is a block diagram showing the demodulation section of the modulation/demodulation section (4), in which (14) is a zero cross detector;
(15) is a carrier recovery PLL (CPLL) for recovering the carrier wave from the received waveform, (16) is a chipper demodulator, (17) is a filter, (18) is a zero cross detector, and (19) is a transmitting side. Clock regeneration PLL (DPLL) for regenerating a clock synchronized with the modulation speed of (2
0) is an A/D converter.

Next, the demodulation operation will be explained with reference to the output waveform diagram of each part in FIG. 9. The received signal (Figure 9a) is detected by a zero-cross detector (
14) to the carrier recovery PLL (15) and directly to the chopper demodulator (16).

In the carrier regeneration PLL (15), the zero cross detector (
Based on the output of 14) (FIG. 9b), a clock (FIG. 8C) synchronized with the carrier wave of the received signal is output. The chopper demodulator (16) demodulates the received signal using the output of the carrier recovery PLL (15).

The demodulated signal (Fig. 8d) is filtered by the filter (17
) (Fig. 8e), the clock recovery PLL is passed through the zero cross detector (18).
(19) and the A/D converter (20)
is entered directly into

The clock regeneration PLL (19) regenerates the clock (Fig. 8 g) corresponding to the modulation rate on the transmitting side based on the output of the zero cross detector (18) (Fig. 8 f), and the A/D
Provides conversion timing to the converter (20). A
The output converted into digital data by the /D converter (20) is given to the CPU (5).

[Problem to be solved by the invention]

In such a conventional still image videophone device, when the demodulator of the modulation/demodulation section (4) demodulates the received signal, the carrier wave is regenerated from the zero-crossing point of the received signal (CP L
L).

Then, the received signal is synchronously detected based on the regenerated carrier wave,
The data clock is regenerated based on the zero cross points of the synchronously detected signal (DPLL).

Based on this regenerated data clock, the synchronously detected signal is sampled and the data is demodulated, and the performance of the demodulator largely depends on the performance of the two PLLs.

The PLL operates based on the zero-crossing points of the input signal, but as shown in Figure 9, when the amplitude of the input signal is small, the positions of the zero-crossing points are easily affected by noise, etc., and the PLL synchronization is likely to be disrupted. That is, when the amplitude of the input signal is small, a point where a zero cross occurs due to noise occurs, a shift occurs in the zero cross output, and synchronization is disturbed. When the synchronization of the PLL is disrupted in this way, carrier wave reproduction and signal sampling are not performed normally, resulting in a problem that reception performance deteriorates.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a still image videophone device that can improve reception performance by reducing disturbances in PLL synchronization caused by noise and the like. With the goal.

[Means to solve the problem]

The still picture video telephone device according to the present invention relates to a still picture video telephone device that transmits and receives image data as an amplitude-phase modulated image signal, and a demodulator that demodulates the image data from the received signal is a phase-locked loop. (P
LL), the carrier wave is recovered from the received signal, and the recovered carrier wave is used to reproduce image data from the received signal, but the range in which synchronization is possible in this PLL is limited to the image data that is transmitted prior to the image signal. CP that received the identification signal
It is characterized in that change control is performed in accordance with a predetermined sequence of PLL sensitivity control signals supplied from U.

[Effect]

In the videophone device according to the present invention, the received signal is input to the demodulator, where it is demodulated into image data.

This demodulator has a PLL, and this PLL
The carrier wave is recovered from the received signal by

The recovered carrier wave is then used to reproduce image data from the received signal.

Here, the synchronizable range in this PLL is changed according to a PLL sensitivity control signal of a desired pattern supplied from the CPU. That is, the synchronizable range is normally made large, and after receiving the PLL sensitivity control signal, the synchronizable range is controlled according to a predetermined sequence of the PLL sensitivity control signal.

Therefore, the tracking performance of the PLL is improved by increasing the sensitivity when a signal with a high signal level that is easy to achieve accurate synchronization is received, and lowering the sensitivity when receiving a signal with a low signal level that is easily affected by noise. It is possible to reduce the adverse effects of noise etc. without dropping the device.

〔Example〕

Next, a preferred embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the overall configuration of a video telephone device according to an embodiment of the present invention. Here, in the conventional example shown in FIG. 5, the same members are given the same reference numerals and repeated explanations will be omitted.

A characteristic feature of this invention is that the means (21) for supplying PLL sensitivity control signals from the CPU (5) to the modulation/demodulation section (4)
) is provided. This CPU (5) detects a pixel identification signal such as a videophone identification signal (A) or a control information signal (B) sent in advance of a pixel signal (C), and according to the detection result, performs a PLL of a desired pattern. The sensitivity control signal is supplied to the modulation/demodulation section (4).

The modulation/demodulation section (4) controls the demodulation process according to the PLL sensitivity control signal supplied from the CPU (5).

Next, the reception operation of the above embodiment will be explained with reference to FIG.

The amplitude pattern of the received signal is as shown in FIG. 2a. The amplitude pattern of the received signal is always the same except for the image signal. Therefore, CPU (5) is P
A signal as shown in FIG. 2 is output as the LL sensitivity control signal (100).

Therefore, the PLL sensitivity control signal (10
0) will be explained. In the reception standby state, the CPU
(5) sets the PLL sensitivity control signal (100) to H, and
Increase the sensitivity of LL (a).

Therefore, the frame synchronization signal (
During reception of B-1), the highly sensitive PLL quickly synchronizes (see). Note that, as described above, the CPU (5) knows the timing synchronization of the received signal using the frame synchronization signal (B-1), so it can know the timing of the following signals.

CP that recognized the demodulated frame synchronization signal (B-1)
U (5) is the PLL immediately before the amplitude calibration signal (B-2)
Set the sensitivity control signal (100) to L to lower the sensitivity of the PLL (c). While receiving the amplitude calibration signal (B-2),
A PLL with low sensitivity has little phase shift (disturbance of synchronization) due to noise, etc., and the modulation/demodulation section (4) exhibits good reception performance (d).

The CPU (5) returns to the PL immediately before the ID signal (B-3).
Set the L sensitivity control signal (100) to H to increase the sensitivity of the PLL (e). The PLL synchronizes again with high sensitivity and eliminates the phase shift.

The CPU (5) sets the PLL sensitivity control to L immediately before the image signal (C) to lower the PLL sensitivity (g).

A PLL with low sensitivity is less affected by noise and can receive image signals with small amplitude clearly (H). C.P.
U (5) raises the sensitivity of the PLL for the next reception after the reception is completed.

FIG. 3 is a schematic block diagram of a CPLL circuit which is a feature of the present invention, and FIG. 4 is a timing chart for explaining the operation of the CPLL circuit.

In FIG. 3, (22) is an edge detection circuit, and this edge detection circuit (22) detects a change point (edge) of an input signal and outputs a pulse.

(23) is a reference signal generation circuit, and this reference signal generation circuit (23) converts the pulse output from the edge detection circuit (22) into a signal having a constant pulse width, and is generally a one-shot multivibrator. A circuit is used. However, since an accurate pulse width is required here, it is constructed of a digital counter circuit that clears the count value and output with an input pulse, and when a certain count value is reached, sets the output to H and stops. This digital counter circuit outputs a signal with an accurate pulse width by always counting a reference clock signal having a constant period.

(24) is a phase difference detection circuit, and this phase difference detection circuit (24) calculates the phase difference between the output of the reference signal generation circuit (23) and the output of the variable frequency divider (27), which will be described later, using a two's complement number. Specifically, the reference clock signal is counted during the period when both inputs are L, and depending on the direction of the phase shift, the count value is converted to a two's complement number (that is, a negative value). Convert it to a value) and output it. In the case of the direction of phase shift shown in Fig. 4, the phase difference detection circuit (24)
The output of is a positive value.

(25) is a multiplication circuit, and this multiplication circuit (25) is
Output data of phase difference detection circuit (24) and CPU (5)
The multiplication result is multiplied by the data outputted by the multiplier and outputted, and the result of the multiplication becomes data indicating the amount of phase correction. This multiplication circuit (25) is newly provided in this invention in order to make the sensitivity of the PLL variable.

In addition, in the conventional PLL, there was a circuit that multiplied the output data of the phase difference detection circuit by a fixed constant, but since the fixed constant was set to, for example, 1/256, it was necessary to build a circuit equivalent to multiplication just by connecting the wiring. Since it was possible to do this, there were virtually no multiplication circuits.

(26) is a constant addition circuit, and this constant addition circuit (2
G) is a circuit that adds a fixed constant to the output data of the multiplication circuit (25). The fixed constant added here determines the basic frequency division of the next-stage variable frequency divider circuit (that is, the free-running frequency of the PLL).

(27) is a variable frequency divider circuit, and this variable frequency divider circuit (2
7), the frequency division number can be varied by input data. Specifically, it is a counter circuit that counts down based on a reference clock signal, and when the count value reaches zero, it loads input data and starts counting down again. The output of this variable frequency divider is a signal in which the logic of the most significant bit of the counter is inverted.

(28) is a frequency divider circuit, and this frequency divider circuit (28)
is for dividing the output of the variable frequency dividing circuit (27) into two, and C
Exists only in PLL. Note that the DPLL does not have a divide-by-2 circuit, and the output of the variable frequency divider becomes the output of the PLL as it is.

Next, the operation of the CPLL having the above configuration will be explained based on FIG. 4. Here, in order to make the description concrete, the frequency of the reference clock signal is assumed to be 3.58 MHz, and the free-running frequency of the PLL is assumed to be 1748 Hz.

First, assume that the input signal of the PLL (15) and the output of the variable frequency divider are as shown in the figure. The edge detection circuit (22) is
Detects the changing point of the input signal and outputs a pulse.

The reference signal generation circuit (23) outputs pulses corresponding to 512 cycles of the reference tarok signal based on the human pulse.

The phase difference detection circuit (24) is a reference signal generation circuit (22)
The phase difference between the reference signal, which is the output signal of the variable frequency divider, and the output signal of the variable frequency divider is output as a count using the reference clock signal. Since the pulse width of the 1i and 2vI signals is 512 cycles of the reference clock signal, the count value here is O to 512, and the output data after performing two's complement conversion depending on the direction of the phase shift is in the range of -512 to +512. . The sign of this Tagata data indicates the direction of the phase shift, and the absolute value indicates the magnitude of the phase shift.

Note that when the output pulse of the edge detection circuit (22) is not input in that cycle, the phase detection circuit (24) outputs O.

The multiplication circuit (25) multiplies the phase shift data output by the phase difference detection circuit (24) by a value that determines the sensitivity of the PLL in real time. The value that determines the sensitivity is a value in the range of 0 to 0. For example, when this value is 1/16,
Phase correction is performed by an amount equal to 1/16 of the detected phase shift. When this value is 0, the multiplication result is always 0 and no phase correction is performed.

The constant addition circuit (26) adds a constant that determines the free running frequency of the PLL to the output data of the multiplication circuit (25). In this case, the constant to add is 1o24.

The variable frequency dividing circuit (27) divides the frequency of the reference clock signal by the number of input data. The frequency division number when phase correction is not performed is 1024, which is added by the constant addition circuit (26) in the previous stage, and the free running frequency of the PLL is 3.58MHz/1024/
2-1748 Hz (/2 in the last term of this equation is due to the next-stage frequency divider circuit). The frequency division number when phase correction is performed is determined by the following formula.

(Frequency division number) - (Phase shift amount) It is output as a typical PLL output signal.

The PLL sensitivity is 1/16 to see how the PLL performs phase correction.
The case will be explained below.

Assume that the phase difference detection circuit (24) detects a phase shift of 300 cycles of the reference clock signal in a certain cycle. The phase difference detection circuit (24) outputs data +300, and the output of the multiplication circuit (25) is (+300)
(1/16) −(+19), and the constant addition circuit (2
The output of 6) is (+19) + (1024) - (+104
3). The next cycle of the variable frequency divider circuit (27) has a length of 1043 cycles of the reference clock signal, which means that phase correction for 19 cycles has been performed.

If the human input signal is 1748 Hz, a phase shift of (+300) - (+19) - (+281) cycles will be detected in the next cycle, and (+281) x (1/1 B) - (+
18) Phase correction for the period is performed, and the remaining phase shift is (
+281) −(+18)−(+263) cycles. In this way, the PLL gradually reduces the phase shift,
It's in sync.

In this way, in the PLL, synchronization can be achieved by detecting the phase of the input received signal.

In this embodiment, the value that determines the sensitivity in the multiplication circuit (25) is controlled by a sensitivity control signal (100) from the CPU (5).

Therefore, by grasping the timing of each signal in the received signal by the CPU (5) and adjusting the sensitivity accordingly, it is possible to perform optimal PLL control.

Note that the sensitivity of the PLL is set to 1/16, for example, as in this example.
The multiplication circuit (25) can have an extremely simple configuration if it is switched in two stages: and 0 (or 1/8). In addition, as shown by the broken line in FIG. 2, when a synchronization calibration signal with a high signal level is inserted into the image signal at a predetermined interval, the PLL sensitivity control signal (100 ) may be set to H.

〔Effect of the invention〕

As explained above, according to the videophone device according to the present invention, the synchronizable range in the phase-locked loop is adjusted according to the PLL sensitivity control signal of the desired pattern output from the CPU by receiving the image identification signal. Since the change can be controlled automatically according to a predetermined sequence, the influence of noise contained in the received signal can be suppressed to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a still image video telephone device according to the present invention, FIG. 2 is a received signal waveform diagram, and FIG. 3 is a block diagram showing the configuration of a phase-locked loop in the embodiment. FIG. 4 is an output waveform diagram of each part of the phase lock φ loop, FIG. 5 is a block diagram showing the overall configuration of a conventional still image video telephone device, FIG. 6 is an explanatory diagram showing the configuration of a received signal, and FIG. 7 is an explanatory diagram for explaining the modulation of image data, FIG. 8 is a block diagram showing the configuration of the demodulator, FIG. 9 is an output waveform diagram of each part of the demodulator, and FIG.
The figure is an explanatory diagram of PLL synchronization deviation. In the figure, (4) is a modulation/demodulation circuit, (21) is means for supplying a PLL sensitivity control signal (100), and (15) is a phase-locked loop. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent: Patent attorney Masuo Oiwa (2 others) Explanatory diagram of the structure of the received signal Luminance signal and carrier waveform diagram

Claims (1)

[Claims] A still image videophone device that transmits and receives amplitude-phase modulated image data through a telephone line, comprising: a modulation/demodulation section that modulates and demodulates the image data; and a central control section that controls the transmission and reception. The demodulator of the modulation/demodulation section includes: a phase-locked loop that extracts and recovers a carrier wave from a received signal; an image data reproduction means that reproduces image data from the received signal using the recovered carrier wave; Sensitivity change that changes the synchronizable range in the lock loop according to a predetermined sequence of PLL sensitivity control signals of a desired pattern supplied from the central control unit by receiving an image identification signal in a received signal. 1. A still image videophone device comprising: means for suppressing the influence of noise contained in the received signal by reducing the synchronizable range when receiving a low-level signal.