JPH03184447A - Modem - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a modem, in particular, an analog interface means for converting a human-generated analog signal into a digital signal, a digital signal outputted from the analog interface means, and a reception timing. The present invention relates to a modem comprising means for performing digital processing including extraction processing using a digital signal processor and demodulating the signal into a digital signal.

[Prior Art] Conventionally, when data communication or facsimile communication is carried out via an analog communication path such as a telephone line,
A modem (modulation/demodulation device) is used to perform mutual data conversion between an analog processing system and a digital processing system.

FIG. 2 shows the configuration of the main parts of a conventional modem.

In FIG. 2, reference numeral 203 denotes an analog interface circuit (203) that performs conversion between analog and digital signals.
The AIF (hereinafter referred to as AIF) inputs and outputs analog modulated signals to and from line interface circuits and the like. Al
The F203 only performs analog/digital signal conversion, and the actual demodulation is performed by a digital signal processor (
This is performed by a DSP 201 (hereinafter referred to as DSP).

DSP201 is a microprocessor dedicated to digital signal processing, and performs modulation and demodulation using digital signal processing.
DTE interface circuit (hereinafter referred to as DTEIF)
202, input/output of digital data is performed with the digital processing system. Here, DTE means a data terminal, and in a facsimile machine, the facsimile image processing system corresponds to this.

FIG. 3 shows the configuration of FIG. 2 in more detail, and here shows circuits related to reception from the line side, particularly reception timing extraction and control.

As shown, the AlF 203 includes an A/D converter 306 and a digital PLL circuit 305. DSP2
01 is a demodulation unit 307 and a timing/extraction control processing unit 3 that perform signal processing through software processing, respectively.
Consists of 01. The DTE interface 202 also includes a timing regeneration unit 302 that outputs a clock for synchronizing the reception timing, a clock generation unit 303 that generates a pit rate clock that synchronizes the data output to the digital system, and a clock generation unit 303 that generates a pit rate clock that synchronizes the data output to the digital system. It consists of a register 304.

The circuit shown in FIG. 3 will be explained below.

First, analog input is input to the AD converter 306, converted to digital data, and input to the DSP 201 manually.

In the DSP 201, a timing/extraction control process 301 extracts the timing component of the received data, and if it is detected that the extracted timing component is faster than the receiving operation timing of the local station, the timing reproducing unit 302 for timing reproduction On the other hand, if it is detected that the timing component extracted from the received signal is later than the receiving operation timing of the own station, processing is performed to increase the frequency division ratio of the timing regeneration unit 302. Let's do it.

Since the AlF 203 also operates in synchronization with the reception timing reproduced by the timing reproduction section 302, the output of the timing reproduction section 302 is output from the digital PLL of the AlF 203.
305 , and the A/D converter 306 performs a conversion operation in synchronization with the timing at which the digital PLL circuit 305 outputs the signal.

The basic configuration of the conventional digital PLL circuit 305 is shown in the fourth section.
As shown in the figure.

The human input signal to the digital PLL circuit 305 is sent to the phase comparator 4.
01, and its comparison output is manually input to the counter 402. The counter 402 advances in synchronization with a counting clock, and its count value is compared with a reference value corresponding to a preset phase error in a comparator 403, and the variable frequency divider divides the reference clock according to the result. Timing synchronization is performed by increasing or decreasing the frequency division ratio of frequency divider circuit 404. The output of the variable frequency divider circuit 404 is input to the phase comparator 401 via the frequency divider circuit 405. The outputs of the zero frequency divider circuits 404 and 405 can both be used as reception timing signals.

[Problem to be Solved by the Invention 1] However, in the modem using the AlF203 as described above, as shown in FIG. AI inside etc.
A timing reproducing unit 302 is always required outside of F.
There was a problem that the circuit was complicated.

An object of the present invention is to solve this problem and provide a modem that can be constructed easily and inexpensively.

[Means for Solving the Problems] In order to solve the above problems, the present invention includes an analog interface means for converting a manually generated analog signal into a digital signal, and an output digital signal of the analog interface means. In the modem, a predetermined reference clock is frequency-divided and the frequency-divided output is sent to the analog interface circuit. D
variable frequency dividing means for outputting as an operation reference clock for conversion; control means for determining a frequency division ratio of the variable frequency dividing means according to the output of the reception timing detection process of the digital signal processor; and an output of the variable frequency divider. We searched for a configuration with a means to output a clock synchronized with the .

[Function 1] According to the above configuration, the speed can be adjusted by controlling the operation reference clock of the A/D conversion of the analog interface circuit according to the output of the reception timing detection process of the digital signal processor, It is possible to obtain a clock that is synchronized with those subtle speed changes.

[Example] The present invention will be described in detail below based on an example shown in one drawing.

FIG. 1 is a block diagram illustrating the receiving portion of the AIF of a modem according to the present invention. Here, the AlF in Figs. 2 and 3 is used.
203 or a part of the DTE interface 202 is shown. As will be described later, by simply adding a DSP having the configuration shown in Figure 3 to the configuration shown in Figure 1,
It is possible to realize a configuration equivalent to that of the modem shown in FIG. 2 and the third unit.

In FIG. 1, reference numeral 101 denotes a frequency division ratio setting register for setting the frequency division ratio of the variable frequency divider 102 from a device external to the AIF (DSP 201 in FIGS. 2 and 3).
2 is a variable frequency divider for dividing the mask clock according to an arbitrary frequency division ratio set in the frequency division ratio setting register 101, and 103 is a frequency divider whose input is variable frequency divider 1.
02, and the output is connected to the A/D converter 104.
used as a conversion timing clock.

Further, the output of the variable frequency divider 102 is also connected to the input of the variable frequency divider 106, and the output of the variable frequency divider 106 is connected to the external device (
Register 30 of DTE interface 202 in FIG.
4 etc.).

The output of a frequency division ratio setting register 107 is connected to one input of the variable frequency divider 106, and the 1 frequency division ratio setting register 107 that determines the frequency division ratio is connected to a device external to the modem (such as a DTE).
The frequency division ratio can also be set by

The A/D converter 104 is a circuit similar to that of the conventional AlF203, and is connected to the DSP via an output buffer register 105.
The digitized data is output to 201.

Reception operation timing control using the frequency division ratio setting register 107 is performed by a DSP that demodulates the output of the circuit shown in FIG. Specifically, the DSP is configured in the same manner as shown in FIG.
As will be described later, the frequency division ratio of the variable frequency divider 102 is determined via the frequency division ratio setting register 101. Note that the variable frequency divider 10
The output of 6 is for later use as an output pit rate clocker for a DTE external to the modem, as will be described later.

The A/D converter 104 converts the analog input into digital data every time the clock output from the frequency divider 103 rises or falls, and outputs the output buffer register 105.
Output to. The output of the output buffer register 105 is connected to the input of a DSP (see Figure 2.3) that performs digital demodulation processing.

Note that when the AIF is configured as described above, the timing reproduction section 302 and pit rate clock generation section 303 of the DTE interface 202, which were conventionally necessary, become unnecessary (see FIG. 3).

Next, the operation of the above configuration will be explained.

In the above configuration, for example, the frequency of the mask clock is 7.3428 MHz, the sampling frequency of A/D conversion is 9600 Hz, and the division ratio of the 1 frequency divider 103 is "3".
shall be.

In this case, the frequency division ratio r256J is set in the frequency division ratio setting register 101 from the DSP side. When this value is set, the variable frequency divider 102 outputs 28.8kHz, the frequency divider 103 outputs 9600Hz, and the A/D converter 104 adjusts the level of the input analog signal according to the timing. is converted into digital data every 1/9600 seconds and stored in the output buffer register 105.

When data is stored from the A/D converter 104, the output buffer register 105 converts the data into, for example, serial data and outputs the data. This output is the DSP (3rd
(see figure) and digital signal processing is performed manually.

In the signal processing, timing extraction/control processing 301 is performed as shown in FIG. The setting value of the frequency division ratio setting register lot is rewritten to, for example, r255J. This makes it possible to speed up the reception operation (A/D conversion by the A/D converter 306) by about 0.4%.

Conversely, if the modulation timing of received data is slightly later than the reception operation timing.

For example, set the setting value of the frequency division ratio setting register 101 to "257".
”, the reception operation can be slightly slowed down.

As described above, according to the configuration shown in FIG. 1, the DSP serving as the digital demodulation means can directly synchronize the received data processing while finely adjusting the timing of the receiving operation.

Furthermore, the modem's parts other than the analog interface circuit must also operate in synchronization with the reception timing.

For example, if the pit rate clock of the received data needs to be synchronized with the rate of the received data, but the transmission bit rate is, for example, 7200 bps, the DTE external to the modem
Or “4” is sent from the DSP to the division ratio setting register 107.
By setting , it is possible to extract a clock synchronized with the modulation rate of the received data from the output of the variable frequency divider 106.

This clock can be used as a pit rate clock output by the pit rate clock generation section 303 of the conventional DTE interface 202 shown in FIG.

Similarly, the setting value of the frequency division ratio setting register 107 is set to "6".
, "12" etc., each will be 4800 bps.
, 2400 bps can be extracted to the outside. The output of the variable frequency divider 106 can also be output to an external device such as a DTE.

Therefore, the timing regeneration circuit 302 and bit rate generation circuit 303, which were conventionally necessary, are no longer required in the DTE interface section, and the entire modem can be configured easily and inexpensively.

Note that the frequency division ratio setting register 107 and the variable frequency divider 106 may be deleted from the configuration shown in FIG. 1, and the output of the variable frequency divider 102 may be directly output to a DTE interface, etc. If the lock speed is appropriate.

With such a configuration, it is possible to simplify the entire -layer modem and reduce costs.

The above configuration can be implemented in modems used with various communication devices, such as facsimile machines and data terminals.

[Advantageous Effects of the Invention 1] As is clear from the above, according to the present invention, there is provided an analog interface means for converting an input analog signal into a digital signal, and an output digital signal of the analog interface means is input and a reception timing extraction process is performed. In the modem, a predetermined reference clock is frequency-divided and the frequency-divided output is used as an operating standard for A/D conversion of the analog interface circuit. variable frequency dividing means for outputting as a clock; control means for determining a frequency division ratio of the variable frequency dividing means according to the output of the reception timing detection process of the digital signal processor; and a clock synchronized with the output of the variable frequency divider. Therefore, the speed can be adjusted by controlling the operating reference clock of the A/D conversion of the analog interface means in accordance with the output of the reception timing detection process of the digital signal processor. This has an excellent effect in that a timing reproducing unit and the like conventionally required outside the analog interface means can be omitted, and the configuration of the modem can be made simple and inexpensive.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the configuration of an analog interface section of a modem incorporating the present invention, Figure 2 is a block diagram showing the configuration of a conventional modem, and Figure 3 is a block diagram showing the configuration of a conventional modem for controlling reception operation timing. A block diagram showing the configuration of
FIG. 4 is a block diagram of the digital PLL circuit of FIG. 3. 101.107...Division ratio setting register 102.10
6...-Variable frequency divider 103--Frequency divider 104-=A/D converter 105--Output buffer register ■...DSP 02--DTE interface 203...A ■

Claims (1)

[Claims] 1) An analog interface means for converting an input analog signal into a digital signal, and an output digital signal of the analog interface means is input, and digital processing including reception timing extraction processing is performed by a digital signal processor. means for demodulating into a digital signal; variable frequency dividing means for dividing a predetermined reference clock and outputting the divided output as an operation reference clock for A/D conversion of the analog interface circuit; It is characterized by comprising a control means for determining the frequency division ratio of the variable frequency dividing means in accordance with the output of the reception timing detection process of the digital signal processor, and a means for outputting a clock synchronized with the output of the variable frequency divider. modem. 2) dividing the output of the variable frequency dividing means by a predetermined frequency dividing ratio;
2. The modem according to claim 1, further comprising means for supplying an operation reference clock to necessary circuits inside the modem or to devices outside the modem.