JPH02223221A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a propagation delay time and its output capacitor dependency by comprising an output transistor to execute the charge and discharge of the output capacitor of an input/output level converter of a bipolar transistor. CONSTITUTION:The title device is equipped with an internal logic block 11 including a CMOS circuit and an input circuit 10 including the bipolar transistor to drive the input of the block. And a storage means is provided in the internal logic block 11. In the level converters of input and output buffers 10 and 12 for TTL-CMOS level conversion for the internal logic block 11 operated by a CMOS level, the output transistor which executes the charge or discharge of the level converter is comprised of the bipolar transistor. Thereby, the propagation delay time and the capacitor dependency of the input and output buffers 10 and 12 can be reduced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when used in semiconductor integrated circuit devices, for example, logic semiconductor integrated circuit devices whose input/output levels are TTL level, SMM level, and CMOS level. be.

[Background technology]

In FIG. 1, the input/output level studied by the inventor of the present invention prior to the present invention is the TTL level.

A block diagram of a logic semiconductor integrated circuit device IC whose internal logic level is 0MO8 level is shown.

Such a circuit device IC receives TTL level input signals IN, .
IN, Input pad 7710.0 for converting the level of the river INn into a CMOSL/Bell signal 7710.0 Internal logic block 11.0 for performing a logic operation at the MO8 level. The output signal of the CMOS level of this part logic block 11 is T
It includes an output buffer 12 for level conversion to a TL level output signal, and each circuit 10, 11, 12 is supplied with a 5 volt power supply voltage Vcc and is properly grounded.

Input terminals IN, IN, ... IN of the input buffer 10
The high level input voltage VIHIG supplied to n is 2.0
volt or more and this low level input voltage VILIG is 0
．． Set to 3 volts or less. Therefore, the input threshold voltage Vith1o for the input buffer output terminals IN, IN, .

On the other hand, the high level output voltage VOHIO obtained from the output of the input buffer 10 is set equal to the high level input voltage Vinxt of the internal logic block 11, and the low level input voltage VOLIO obtained from the output of the input buffer 10 is set equal to the high level input voltage Vinxt of the internal logic block 11.
is the low level input voltage VfLt of the internal logic block 11
is set equal to t. Therefore, internal logic block 11
P-channel MO8 that constitutes the CMOS i/verter in
If the FET threshold and hold voltage are VTP, and the N-channel MO8FET threshold voltage VTN*power supply voltage Vce, the above voltage VOHIOi VjH
ll #VOLIO* V 1L11 are respectively set as follows.

N'auxo=V1 old construction>VcC-1vrpl 0”
(1) VOLIO-ViLtt <VTN
9th 2) Vcc to 5yk' l IVTP l
If you set 0.6 Mk + VTN to 0.6 volts,
VOHIO and V, IHII are 4.4 volts or less, V
OLIO and ViLxt are set to 0.6 volts or higher.

Therefore, the input logic threshold voltage Vithxx of the CMOS i/verter in internal logic block 11
is set at approximately 245 volts between 0.6 volts and 4.4 volts.

Similarly, the high level output voltage V of the internal logic block 11
OH1,l and the low-level input voltage ViH1x of the output buffer 12 are set to 4.4 volts or more, and the low-level output voltage VOLII of the internal logic block 11 and the low-level input voltage Vitxz of the output buffer 12 are set to 4.4 volts or more. is 0.6
The output buffer 120 input logic threshold Vithtz is set below 0.6 BoA, -
) and 4.4 volts, approximately 2.5 volts.

The high level output voltage VOH of the output buffer 12 is set so that the output buffer 12 generates a TTL level output signal.
I! is more than 2.7 volts, its low level output voltage v
oLtz is set to 0.5 volts or less.

FIG. 2 is a circuit diagram showing one of the input roses 7710 studied by the inventor of the present invention prior to the present invention, and includes P-channel M08 FET MpI, Mpt.

It is composed of Nf Yarnel MO8FETMn, , Mn, , Mnm + resistor Rp. The gate, source, and drain of each M0.9 FET are designated by the symbol gr S.
Indicated by +d.

The first stage CMOS inverter made up of MpI and Mn and the second stage CMOS inverter made up of M pz and Mn2 are connected in cascade, and R
p and M n constitute a gate protection circuit for protecting the gate insulating films of M pr and Mn1. 2
The output capacitance Cs connected to the drains of Mpt and Mn1 of the stage CMOS inverter is actually Mpt and Mn,
Its value is determined by the drain capacitance of , the wiring stray capacitance between the output of the input buffer 10 and the input of the internal logic block 11 , and the input capacitance of the internal logic block 110 .

Each M OS F E TMp+ l M p! #M
The ratio W/L of channel @W and channel length of n+ + Mnt +Mns is 27/3.5 and 42, respectively.
/3, 126/3.5, 42/3, and 15/3, and the resistance Rp is set to a value of 2 kilohms.

Figure 3 shows the propagation delay time IP of the input buffer 10 in Figure 2.
The dependence of HL + 'PLH on the output capacitance Os is shown, the vertical axis shows the propagation delay time, and the horizontal axis shows the output capacitance C11.

As shown in FIG. 35, the first propagation delay time t PH
L is defined as the time from when the input INPUT changes with the 50% value as the border until the output 0UTPUT changes from the high level to the low level with the 50% value as the border, and is the second propagation delay time t. PLH is input I
Output becomes 0UT after NPUT changes around 50% value.
Part 5 when PUT changes from low level to high level
It is defined as the time until it changes from the 0% value.

In FIG. 35, tf is defined as falling time and tr is defined as rising time.

Thus, as can be understood from FIG. 3, the output capacitance dependence KHL (=ΔtpHL/ΔCs) of the first propagation delay time t PHL of the input buffer 10 in FIG. 2 is approximately 0.8 n
sec/pF, second propagation delay time t PLH output capacitance dependence KLH (=△t PLH/ΔCs) is approximately 1.4n
sec/pF are both large.

In the input buffer IO of Fig. 2, in order to set the manual threshold voltage Vithxo to approximately 1.3 to 1.5 volts, the MI of the first stage CMOS inverter)
Ratio W of channel width and channel length of I and Mn
/L are greatly different, and the propagation delay time tPHL
* In order to reduce the output capacitance dependence KHL*KLH of jl'LH, the ratio W/L of the second stage CMOS inverter l(7) Mp and Mrl is set to a large value of 42/3, and M pt and MU, The channel conductance of the channel is increased.

In order to reduce the dependence of both output capacitances KHL + KLH, K should be increased by increasing the ratio W/L of Mp and Mn= of the second stage CMOS i/parter, but this is because the integrated circuit chip This results in a significant increase in the area occupied by the input buffer 10 on the surface, which hinders improvement in integration density.

In other words, although miniaturization is currently being vigorously promoted in the manufacturing technology of integrated circuits, the lower limit of the channel length of MOS FET in current photolithography using ultraviolet exposure is 3 μm, and the ratio W/L of MOS PET is
In order to make the channel width W a very large value, the channel width W must be made a very large value, and ultimately the M
This is because the area of the element region of the OS FET is significantly increased.

On the other hand, FIG. 4 is a circuit diagram showing one of the output buffers 12 studied by the inventor of the present invention prior to the present invention.
08 F E T M n . The gate, source, and drain of each MO8FET are designated by the symbol ge''xdK, respectively.

CMOS of internal logic block 11 in integrated circuit device IC
The level output signals are M p4 and M of the output buffer 12.
A power supply voltage Vcc of 5 volts is supplied to the 30th terminal, which is applied to the gate of rl4. Therefore, to set the output buffer 120 input p thick threshold voltage Vithl* to approximately 2.5 volts, M
The ratio W/L of p4 and Mn4 is set to be equal to each other.

Similarly, a TTL circuit 14 is shown in FIG. 4, and a power supply voltage Vcc of 5 volts is supplied to this circuit 14 through a terminal No. 35. The output signal of the TTL level output buffer 7 is obtained from the 20th terminal, and the multi-emitter transistor Q of the TTL circuit 14 is obtained through the 32nd terminal.
, which is fed to two emitters.

On the other hand, as a TTL circuit, it is a standard type TTL circuit.

Shigattoki TTL circuit, low power Shigatki TT
L circuit, advanced low power simulation TT
L circuits have been announced, and their characteristics are naturally somewhat different from each other.

Further, the output of the output buffer 12 is transmitted to a large number of TTL circuits 14.
It is necessary to drive the 0 inputs simultaneously and in parallel. One measure of this driving ability is the low power seal,
) 20 inputs of the T'I'L circuit can be driven in parallel.

When the output of the output buffer 12 is low level, the low level
0.0 from one input of the power switch TTL circuit.
The low level input current IIL of 4mA is output from the output buffer 7.
It flows into the drain-source path of ON channel MO8FETMn. Follow [1. In order for the output buffer 12 to drive <20 inputs to low level as described above, M
n, it is necessary to flow a total of 8 mA.

On the other hand, the low level output voltage VOLI of the output buffer 12
As explained above, J must be less than 0.5 volts, so the output buffer 12ON channel MOS
The on-resistance ROM of F E T M n 4 is 0.
It must be set to a small value, such as 5 volts/8 milliamps - 62.5 ohms.

Furthermore, in order to make the on-resistance ROM of K and Mna small, the ratio W/L of Mn must be set to an extremely large value of 700/3 to 1000/3. On the other hand, in order to set the input logic threshold island hold voltage Vth hxz of the output buffer 12 to approximately 2.5 volts as described in 5 above, the ratio W/L of Mpa and Mn4 must both be equal values. Therefore, the ratio W/L of the P-channel MQ8 FET Mp4 of the output buffer 12 must also be set to an extremely large value of 700/3 to 1000/3.

This also results in a significant increase in the area occupied by the output buffer 12 on the surface of the integrated circuit chip, which not only hinders the improvement of integration density but also increases the switching speed of the internal logic block 11 for the following reasons. causes a significant decrease in

That is, both MO8FETMp of the output buffer 12,
When the ratio W/L of both Mn and Mn is set to a large value, both MO8
The gate capacitances of the FETs Mpa and Mni also become proportionally large cages. These Mpa.

Since the gate capacitance of Mn4 becomes the output load capacitance of the internal logic block 11, the output resistance of the internal logic block 11 and these gate capacitances cause a reduction in the switching speed of the internal logic block 11.

On the other hand, the output of the output buffer 12 is not only led out as an external output terminal (terminal 20) of the integrated circuit device IC, but also connected to the input terminals of a large number of TTL circuits 14 via external wiring. A12 output load capacity Ox
is often an extremely large value.

Figure 5 shows the output load capacitance Ox of the output buffer 12 in Figure 4.
The graph shows the dependence of the propagation delay time L PHL r 'PI-H on the graph, the vertical axis shows the propagation delay time, and the horizontal axis shows the output load capacitance.

As can be understood from FIG. 5, the capacitance dependence KHL (=Δtpsu, /ΔCx) of the first propagation delay time tPHL of the output buffer 12 in FIG. 4 is approximately 0.3n.
aec/pF, second propagation delay time t PLH capacitance dependence KLH (=ΔtphH/ΔCx) is approximately 0. l 7
Both n5ec/pF are large.

Therefore, the input bug 7 in FIG. 2, which is the background art of the present invention,
The problems of A10 can be summarized as follows.

(In order to reduce the dependence of the propagation delay time of the input buffer 100 on the output capacitance of the input buffer 100, the second stage C
Both MO8FB'rMpt + Mn of MOS inverter
, the ratio W/L must be increased, which hinders the improvement of the integration density. In particular, when the integrated circuit device IC is of the master slice type or semi-custom gate array type, there is a possibility that a very large number of gate input terminals in the internal logic block 11 are connected to the output of the input buffer 10. When the output capacitance Cs of the input cover 7a 10 becomes extremely large, the above problem becomes extremely serious.

(2) Furthermore, since the first stage of the input buffer 100 is composed of a CMOS inverter M1' tr Mn1, even if a gate protection circuit composed of Rp and Mn3 is connected, the voltage applied to the input terminal IN is The breakdown strength of the gate insulating films of both MO8PETs against the applied surge voltage is not sufficient.

Further, the problems of the output buffer 12 shown in FIG. 4, which are the background art of the present invention, can be summarized as follows.

(3) In order to set the hold voltage V1tbs* for the input logic threshold of the output buffer 7a 12 to approximately 2.5 volts and to increase the current sinking ability of the output buffer 7a 12 during low level output, both MO8FETs must be Mp,,M
The ratio W/L of n4 must be both equal to each other and have large values, which hinders the improvement of the integration density.

(4) Increase the ratio W/I of both MO8PET Mp4°Mn of the output buffer 12 (then both Mp4.

The gate capacitance of Mn4 also increases. Therefore, the output resistance of the internal logic block and these gate capacitances result in a reduction in the switching speed of the internal logic block 11. especially,
The output stage of the internal logic block 11 is an MO with a large output resistance.
In the case of an S FET□, this reduction in switching speed becomes a significant problem.

(5) Output buffer 12 is M O8F E T M
I) Since it is composed of 4-Mr14, the propagation delay time has a large dependence on the output load capacitance CXVC.

In particular, a large number of TTL circuits 14 are provided at the output of the output buffer 12.
This problem becomes important when connected to the input terminal of

[Purpose of the invention]

The object of the present invention is to provide an internal logic block that generates an output signal of 0M08 level by applying an input signal of 0M08 level, and a level converter such as TTL-0MO8 level conversion for this internal logic block p2. In a semiconductor integrated circuit device having a converter cover 7a and/or a level converter cover sofa such as 0MO8-TTL level converter, the integration density can be improved, and the input buffer 7a and/or the output buffer The object of the present invention is to reduce the dependence of the operating speed on the output capacitance and to improve the operating speed.

The above and other objects and novel features of the present invention include:
It will become clear from the description of the invention and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, in Kapuffer's level converter for TTL-CMOT level conversion for internal logic blocks operating at the CMOS level, the output transistor that performs charging or discharging of the output capacitance of the level converter is constituted by a bipolar transistor. By this, M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence You can achieve your goal by making it smaller.

In addition, in an output converter for MO8-TTL level conversion for an internal logic block that operates at a CMOS level, the output transistor that charges or discharges the output load capacitance of the level converter is a bipolar transistor. By configuring M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even though the element size is small, and a large charging current or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence The purpose of reducing gender can be achieved.

〔Example〕 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device IC according to an embodiment of the present invention, in which the input buffer 10 of FIG.
TTL-CM08 level conversion capacitor 7a 20° which performs the same operation as the internal logic block 1 in FIG.
An internal logic block 21.1 which operates at the CMOS level as in 21.1. It includes an output buffer 22 for 0MO8-TTL level conversion that performs an operation similar to that of the output buffer 7 in FIG.
It is supplied with a power supply voltage Vcc of volts and is properly grounded via terminal No. 31.

The input buffer 20 has a plurality of TTL-CMOS level converters 201, 202...2On, each input is connected to the 1st terminal, 2nd terminal...19th terminal, and each output is connected to an internal logic block. 21 through an aluminum wiring layer inside the circuit device IC.

Internal logic block 21 is 0MO8, NAND gate 21
1,212,213,214 further 0MO8-NOR gate 21i-1), 2xl further 0MO as necessary
8. Exclusal tin OR gate, 0MO8. Transmission gate.

Includes 0MO8 inverter, etc.

For example, as shown in FIG.
Channel M08 FET Ms.

It is composed of 100 MO8 circuits including M4.

Further, as other examples of the 0MO8-NAND gate 211, as shown in FIG.
, resistance 5. It can also be configured by a quasi-CMOS circuit that further includes R1, and since the output stage of such a quasi-CM08 circuit is composed of bipolar transistors Q, ,Q, the output drive capability is improved and the propagation delay time is reduced. Output load capacitance dependence can be reduced.

Further, the 0MO8/NOR gate 211 is, for example, a P-channel M08 FETM, , M, and an N-channel MO8PET M, as shown in FIG.

It is configured by a #gcMos circuit including M4.

Further, as other examples of the 0MO8-NOR gate 211, as shown in FIG.
It can also be constituted by a quasi-CM08 circuit further including resistors R, , R, whose output stage is a Bibo2 transistor Q4 . Since it is configured with Q*, the output driving ability is improved and the dependence of the propagation delay time on the output load capacitance can be reduced.

In the internal logic block 21, these 0MO8-N
The AND gate and 0MO8-NOR gate are connected in various configurations according to the master slice method or semi-custom gate array method.

For example, as shown in Figure 11, two CMOS/NAN
By combining D gates or by combining two 0MO8-NOR gates as shown in FIG. Gated R-8 controlled by clock signal CK by combining
It consists of 7 lips and 70 tubes.

In this way, in the master slice type or gate array type logic semiconductor integrated circuit device IC that meets customer needs, the level converter 201.2 of the input buffer 70 can be changed by changing only the wiring pattern.
The outputs of 02...20n and the inputs of various gates or inverters of the internal logic block 21 are connected in various ways, and similarly the outputs of the various gates or inverters of the internal logic block 210 and the output buffer 220 level conversion. The inputs of the devices 221, 222, . . . , 22m are connected in various ways.

The output buffer 22 has a plurality of 0MO8-TTI level converters 221, 222, . . . , 22m, and each output is connected to a 20th terminal, a 21st terminal, .

Input buffer 200 level converter 201, 202...
The essential features of 20n are as follows.

(1) The input threshold and hold voltage vtth of each level converter 201, 202, and 20n is TTL low level input voltage 0.8 volts and TTL high level input voltage 2.0 volts.
It is set between the bolt.

(2) The output capacitance C of each level converter 201, 202...20n in response to the input signal supplied to its input terminal
The output transistor p that performs charging or discharging of s is constituted by a Bibo2 transistor.

Furthermore, the level converter 201゜20 of the input buffer 20
Preferred features of the preferred embodiment of 2...20fl are as follows.

(3) A Schott barrier diode is connected between the base and collector of the two-output transistor Q, which discharges the output capacitance Cs in (2) above.

(4) The base and collector of the drive transistor Q for driving the base of the bipolar output transistor Q by its output in response to the input signal supplied to the input terminal of each level converter 201, 202...10n. A second synchronized barrier diode is connected between the two.

(5) The output transistor for charging the output capacitor C3 of each level converter 201, 202-200 is also constituted by a bipolar transistor Q.

(6) Drive transistor Q! via MO8 buffer with high input impedance and amplification effect! The base or collector signal of Q is transferred to the charging bipolar output transistor Q.

A barrier diode D for level shifting is connected between the input terminal of each level converter 201, 202, . . . 20n and the base of the drive transistor Q.

(8) Between the input terminal of each level converter 201, 202-2Qn and the base of the drive transistor Q, there is a PNP emitter/7-lower transistor Q4 and a PN junction diode D! for level shifting. are connected.

14 to 31 show various circuit diagrams of an input buffer 200 and a level converter 2010 according to embodiments of the present invention, all of which are described in (1) and (2) above.
It has the essential characteristics of Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

In the level converter 201 of FIG. 14, the input terminal I
Nr is connected to the cathode of a level-shifting Shittatchi barrier diode D, whose anode is connected to the base of the drive transistor Q. The forward voltage V of this diode D1 is between 0.635 volts and 0.635 volts.
The type of barrier metal and barrier area are determined so that the voltage is set at 41 volts. The forward voltage V of the Schottky barrier diode D of the level converter shown in FIGS. 15 to 31 is similarly set to 0.35 volt to 0.41 volt.

Furthermore, in FIG. 14, as shown by the key-shaped base electrode signals of the drive transistor Q and the discharge output transistor Q1, there is a parallel barrier diode D between the base and collector. It is connected. Clamped transistors with Schottky barrier diodes thus have a very short integration time, as is well known. In the examples below,
A transistor with a hook-shaped pace electrode signal is indicative of such a clamped transistor.

In addition, the base of the discharge transistor zQ+ has a 5 kilohm resistance hole for discharging the base charge. is connected to the ground potential point via.

Further, in FIG. 14, an 18 kilohm resistor R11 and a 2 kilohm resistor are connected in series between the power supply voltage Vcc and the anode of the Schittke barrier diode D1. The common connection point of both resistors R, □, R, is a P-channel MO8FET as a phase inverter.
M+), o is connected to the gate thereof, and its drain is connected to the base of the charging output transistor Q.

Further, a diode D is connected to ensure that the transistor Q8 is turned off when the level converter 201 generates a low level output.

The output of the level converter 201 at the emitter of the charging output transistor Q is connected to the output capacitor Cs, and the output of the internal logic block 21 is 0MO8・NA, ND.
Connected to gate 2110 input.

Also, bipolar transistors Q,,Q.

The area of each emitter Q is set to 100μ to 144μ, and it is also possible to set the area smaller than this. Indeed, the ratio W/L of %MO8FET is set to a value of 32/3 to 64/3.

The inventor has confirmed that the embodiment shown in FIG. 14 having the above configuration has the following propagation delay time and its output capacitance dependence.

t PHL (when C5=OpF) = 1.6
n5ectpLn (when C5=OpF)...
5.7nsecKHL...
0.4 n5ec/pFKLH=-0.4nsec/p
F It can be seen that the propagation delay time i PHL + t PLH and the output capacitance dependencies KHL and KLH described above are excellent when compared with the characteristics of the input buffer 10 shown in FIG.

Furthermore, the level converter 201 in FIG. 14 can obtain desired characteristics for the following reasons.

(1) The Schottky barrier diode D10 term direction voltage vF is set to 0.35 to 0.41 volts Ic, and the base-emitter voltage vi of the transistors Q, , Q,
+gt l VBE2 is approximately 0.75 volts,
Level converter 2010 input threshold hold voltage Vf
th is set as follows.

VIth=-VF+VBR1+VBE2=1.09 to 1.15 volts (2) Output transistors Q, , Q for discharging or charging the output capacitance Cs of the level converter 201.

Since it is constituted by a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistors Q, ,Q driven into the saturation region.

Is there a shot between each base and each collector?
- Since the barrier diode is connected, the storage time when both transistors Q, Q, switch from on to off can be reduced.

(4) When the potential at the common connection point of the resistors R, , R1 increases and the phase inverting MO8FET MpIo-charging output transistor Q turns off, the MO8FET
Since the input impedance of the gates of M1), , is very high, from the above common connection point Mp+. The current flowing into the gate of is very small. Therefore, M.O.S.
FBT M9+. Compared to the case where the phase inverter is configured by a Bibo2 transistor instead, the operating speed for switching the charging output transistor Q from off to on is improved.

The level converter 201 in FIG. 15 differs from the one in FIG. 14 only in that another PN junction diode D is added, and the addition of this D4 further reduces the low level output voltage of the level converter. be able to.

Regarding the level converter 201 shown in FIG. 15, the propagation delay time and its output capacitance dependence were confirmed by the inventor as follows.

t PHL (when C5=QpF) ”・1.8
9 n5ectpLH (when C5=OpF)...
・6.37nsecKHL
-0,4n5ec /pFKLH1'00.4nsec
/pF Further, the level converter 201 shown in FIG. 15 can also obtain desired characteristics for the same reason as the case shown in FIG. 14.

The level converter 201 in FIG. 16 includes a drive transistor Q,
Only the collector connection method in FIG. 14 is different from that in FIG. 14, and the propagation delay time of the level converter in FIG. 16 and its output capacitance dependence were confirmed as follows.

t PHL (However, when Cs-0pF, freezing-1, f3
l n5ectpLu (when C5=OpF) ・
-5,08nsecKH! ,
...0.4 n5ec/pFKLH=0.4 n5ec
/pF Also, in the level converter 201 of FIG.
Desired characteristics can be obtained for the same reason as in the case of Figure 4.

Each level converter 201 in FIG. 17 is a MO8F for phase inversion.
The only difference from the one in FIG. 15 is that another NPN transistor Qll is connected between the drain of ET MpIo and the base of the charging output transistor Q, and the propagation delay of the level converter in FIG. Time and its output capacity dependence were confirmed as follows.

t PHL (However, when C5=OpF)...2.
01 n5ectpLu (when C5=OpF)
”4.30 n5ecKHL
--・0.4naec/pFKLH...0.4ns
ec/pF In the level converter 201 of FIG. 18, the transistors Q, , Q, are clamped transistors with a shunt barrier diode, and the base of the discharge output transistor Q, is used for base charge discharge. 5k ohm resistance horse. is connected to the ground potential point via. Also,
Transistor Q! The collector of 8. has a 20 kilohm resistor hole for collector current limiting. is connected.

Power supply voltage Vcc and barrier diode D1
There are 18 kilohm resistors R11 and 2 between the anodes of
Kilohm resistance R1! are connected in series. The common connection point of both resistors 几, , R, , is O8PET 'M9 between P channels as a charging output transistor.
Connected to the gate of Il.

Further, the ratio W/L of Mp+t is 64/3.

The propagation delay time of the level converter 201 shown in FIG. 18 and its output capacitance dependence were confirmed as follows.

tpHL (when C5=OpF) -・-1,9n
5ectpLH (however, when C5=OpF)・-・2,
9nsecKHL…0
．． 4nsec/pFKLH-1.3nsec/pF Furthermore, the level converter 201 in FIG. 18 can obtain desired characteristics for the following reason.

(1) As in the case of Fig. 14, the level converter 20
The 10-input threshold voltage Vith can be set to 1.09 to 1.15 volts.

(2) Since the output transistor Q that discharges the output capacitance C3 of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of FIG. 14, transistors QzQ,
The accumulation time can be reduced.

In the level converter 201 of FIG. 19, the transistors Q, Q, are clamped transistors with Schottky barrier diodes, and the base of the discharging output transistor Q1 is a 5 kilohm resistor for base charge discharging. 0 to the ground potential point. A load resistance R of 8 kilohms is placed on the collector of the transistor Q.
1, and a 20 kilohm resistor R14 is connected between the power supply voltage Vcc and the anode of the Schottky barrier diode D. drive transistor Q,
The collector signal of Nf as a charging output transistor
a, Channel M08 Connected to the gate of FET Mnu. Moreover, the ratio W/L of this Mn1t is 64/3
is set to .

The propagation delay time of the level converter 201 shown in FIG. 19 and its output capacitance dependence were confirmed as follows.

LpuL (when C5=OpF0) -1, l n5e
ctpr, H (when C5=OpFO)・8.5 n
5ecKHI, ...0.3n
sec/pFKLH-2,0nsec/pF Furthermore, the level converter 201 in FIG. 19 can obtain desired characteristics for the same reason as in the case of FIG. 18.

The key to the level converter 201 in FIG. 20 is that the transistors Q, Q, are similarly clamped transistors, and the base of the discharging output transistor Q1 has a 5 kilohm resistor for discharging the base charge. is connected to the ground potential point via. 10 at the collector of transistor Q2
A kilo-ohm load resistor 6 is connected, and the power supply voltage Vc
A 20 kilohm resistor R14 is connected between C and the anode of the Schottky barrier diode D. The collector signal of the drive transistor Q is an N-channel MO8FET Mpts as an amplification transistor.
is applied to the gate of , and the ratio W/L of M n + s is 32
/3, and a load resistance of 20 kilohms is placed on the drain of M n t s. is connected. Mn+a
The drain signal of Mpts is applied to the gate of P-channel MO8FET Mpts as an amplification transistor.
The ratio W/L of pts is set to 64/3, and R□, which serves as a load resistance of 10 kilohms and a resistance for discharging the base charge of the bipolar output transistor Q for charging, is connected to the drain of Mpts.

The propagation delay time of the level converter 201 shown in FIG. 20 and its output capacitance dependence were confirmed as follows.

tPHL (when C5=OpF) -2.2nsec
tpLH (when C5=OpF) "4.5 n5
ecKHx, ・;・0.4
n5ec/pFKL)I
-0.4n5ec/pF Furthermore, the level converter 201 in FIG. 20 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the level converter 2010
Set the input threshold voltage v+th to 1.09 to 1.
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitance Cs and its dependence on the output capacitance can be reduced.

(3) As in the case of Fig. 14, transistor Qi+Q
8 can be reduced.

(4) When the collector potential of the drive transistor Q rises and the charging output transistor Q switches from off to on, the amplification MO8FET M n I
s and Mp, , not only amplify the collector potential change of Q2 and transmit it to the base of Q, but also
F E T M n + s (') The extremely large gate input impedance prohibits the direct flow of large base current from the collector of Q to the base of Q, thereby improving the switching speed of the output transistor Q3. Can be done.

In the level converter 201 of FIG. 21, Q+rQ,
is a clamped transistor, D is a shift barrier diode for level shifting, and resistor R3゜,
R, 4, R, are set to 5 kilo ohms, 20 kilo ohms, and 8 kilo ohms, respectively. The collector signal of the drive transistor Q is applied to both gates of a P-channel MO8FET M14 and an N-channel hMO8FET Mnn, which constitute a CMOS inverter as a voltage amplifier, and both M08FETs MpI<, Ml
The + drain signal is used as a charging output transistor, and the
Applied to the gate of channel MO8FET MpIt. M p+a I M flea + M! '
++ local W/L is 24/3.22/3.64 respectively
/3.

Such a level converter 201 of FIG. The propagation delay time and its output capacitance dependence were confirmed as follows.

tpuL (when C5=OpF) --- 2.02n
sectptu (when Cs = Op F)
・4.27 n5ecKHL
・-0,42n5ec/pFKLH・・4.32nse
c/pF Furthermore, each level converter 201 in FIG. 21 can obtain desired characteristics for the following reason.

(1) As in the case of Fig. 14, the level converter 20
The input threshold voltage of 1 can be set between 1.09 and 1.15 volts.

(2) Since the output transistor Q that discharges the output capacitance C3 of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of Fig. 14, transistor Q++Q
, the accumulation time can be reduced.

In the level converter 201 of FIG. 22, l1 and Q.

is a clamped transistor as an output transistor for discharging, and a level shift barrier diode D10 is connected to the input terminal IN. Anode of D and Q.

A PN junction diode D for level shifting is connected between the base of the power supply voltage Vcc and DI.

A resistor R2°, R,o having a resistance value equal to 10 kilohms is connected in series between both anodes of D, and a base charge discharge is connected between the input terminal IN and the base of Q. A switch barrier diode D is connected to the switch.

A common connection point of the resistors R+I e RIO is connected to the gate of the P-channel MO8FETM Mp as a charging output transistor, and the ratio W/L of M p, , is set to 64/3.

The propagation delay time of the level converter shown in FIG. 22 and its output capacitance dependence were confirmed as follows.

t PHL (when C5=QpF) -2,44n
sectpt, H (when C5=OpF)...
5.41 n5ecKHL
...1.0 nsec/pFKLH-5,3n5ec/pF Furthermore, the level converter 201 in FIG. 22 can obtain desired characteristics for the following reason.

(1) The forward voltage V of the switch barrier diode D is set to 0.35 to 0.41 volts, and the PN
The forward voltage V of the junction diode Ds is 0.75 volts, and the base-emitter voltage VBg of the transistor Q is
Since l is 0.75 volts, the input voltage and hold voltage Vith of the level converter 2010 for turning on the transistor Q is set as follows.

Vith=-VFI +VF5 +Vagx=1.09
to 1.15 volts (2) Since the output transistor Q, which discharges the output capacitance Cs, is composed of a bipolar 2 transistor with small output resistance, the switching time or propagation delay time and its dependence on the output capacitance can be reduced. can do.

(3) Since transistor Q is a clamped transistor, its storage time can be reduced.

In the level converter 201 of FIG. 23, Q++Q,
The clamped transistor rDl is a shuttling barrier diode for level shifting, and the resistor R8゜+
RI4*RlB are set to 5 kilohms, 20 kilohms, and 8 kilohms, respectively. The collector signal of the drive transistor Q is the CMO as a voltage intensifier.
P-channel MO8FET that constitutes the S inverter
The drain output of both MO8PETs is applied to the gate of the P-channel MO8FET Mpto for switching. MpI4, Mnraz
The 6 ratio W/L of M pIN is 24/3.32/ respectively.
It is set to 3.64/3.

The drain output of MOS PET Mpto is applied to the base of a bi-polar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter shown in FIG. 23 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=-QpF)...5
．． 07 n5ect PLH (when C5=OpFO) -5, Q 9 n5ecKHL
...0.4 n5ec/pFKLH=0.4
n5ec/pF Furthermore, the level converter 201 in FIG. 23 can obtain desired characteristics for the following reason.

(11 As in the case of Fig. 14, the level converter 2010
Input frequency hold voltage Vith from 1.09 to 1
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time in charging and discharging the output capacitor iCs and its dependence on the output capacitance can be reduced.

(3) As in the case of Fig. 14, transistor Q+
+Q, the accumulation time can be reduced.

(4) When the collector potential of the drive transistor Q rises and the charging output transistor Q switches from off to on, the CMOS converter M pear
M1114 amplifies the collector potential change of Q2 and
In addition to transmitting data to the base of the MOS FET
The extremely large gate input impedance of Mp14 and Mnn prevents a large base current from flowing directly from the collector of Q to the base of Q, thereby improving the switching speed of the output transistor Qa.

The level converter 201 in FIG. 24 is a 10 kilohm resistor RI for discharging the base charge of the charging output transistor Q1.
The only difference from the level converter 201 in FIG. 23 is that s is connected between the base and emitter of Q, and the propagation delay time and output capacitance dependence of the level converter 201 in FIG. 24 are as follows. It was confirmed as follows.

tpHL (however, C5 = QpF' Tokito 6.2nse
ctphn (however, C5=OpF time block "4.9nse"
cK)IL”・0.4
nsec/pFKLH-=0.4 nsec/pF Furthermore, the level converter 201 in FIG. 24 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 shown in FIG. 25, the resistance R1° of the base charge discharging circuit of the discharging output transistor Q1 is 1.5°.
Kilohm resistance R1゜, 3kohm resistance R,...
The base of the capacitor Q s and the base of the capacitor Q s are replaced by an active pull-down circuit configured by a clamped transistor Q6 and a Schottky barrier diode for discharging the base charge of the charging output transistor Q3. The only difference from the one in FIG. 24 is that it is connected to the collector, and the propagation delay time and its output capacitance dependence in FIG. 25 were confirmed as follows.

LpiiL (however, when C5=OpF)・-・5,6n
sectrLu (when C5=OpF) -1・5
．． 3 nsecKHL
IT-0,4nsec/pFKLH…0.4nsec
/pF Furthermore, the level converter 201 in FIG. 25 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter 201 in FIG. 26 is the same as the active pull-down circuit R,,,l(,,.sQa) in FIG. Unlike the one shown in the figure, the propagation delay time and its dependence on the output capacitance were confirmed as follows in FIG. 26 as well.

t PHL (However, when C5=OpF) --- 8.6
2nsectpLH (when C5=OpF)...
4.7nsecKHL...
・0.4 n5ec/in pFKLH
pF Further, the level converter 201 in FIG. 26 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG. 27, bipolar transistors Qt, Q-, and Qs are discharge output transistors and drive transistors, respectively.

It is an output transistor for charging, and D, , and D are respectively switch barrier diodes for level shifting, and P.
It is an N-junction diode, R,,,R,,.

R2, and R□ are resistances of 20 kilohms, 8 kilohms, 10 kilohms, and 10 kilohms, respectively, and M
p, 6, M n+6 are each P channel MO8
FET, N channel MO8FE'r, both MDI
The ratio W/L of 6 +Mis is both set to a value equal to 32/3.

In particular, M I) Ill r M ml$ l Qt +
Qa is characterized in that it is a quasi-CMOS inverter type amplifier with low output resistance.

The propagation delay time of the level converter 201 shown in FIG. 27 and its output capacitance dependence were confirmed as follows.

tpuL (when C5=OpF)...5.48n
secLpLa (when C5=OpF)"5.23
nsecKHL...0.3
7 nsec/pFKLH...0.38 nsec/pF Furthermore, the level converter 201 in FIG. 27 can obtain desired characteristics for the following reason.

(1) The unidirectional voltage V of the barrier diode D is 0.35 to 0.41 volts, the base-emitter voltage VBE2 of the transistor Q is 0.75 volts, the PN junction diode D, The forward voltage VF8 is 0.
Since it is set to 75 volts, the input threshold-hold voltage Vj th of the level converter 201 regarding the on/off operation of the transistor Q is set as follows.

VIth = -VF1 + VBE2 + VF8 = 1.09 to 1.15 volts (2) The output transistors Q, , Q, which discharge or charge the output capacitance Cs are composed of bipolar transistors with small output resistance, so switching operation is possible. The speed or propagation delay time and its dependence on output capacity can be reduced.

(3) Since Qt and Qt are clamped transistors, their storage time can be reduced.

(4) The collector potential change of the drive transistor Q is quasi-C
MOS(yverter Mp+a l MnIe l Qs
+ Since it is amplified by Qt and transmitted to the output,
The output waveform change speed can be improved.

In the level converter 201 of FIG. 28, the collector load of the transistor Q is also a resistor. rather than a PN junction diode D,, D,. It differs from the one in FIG. 27 only in that it is composed of a resistor R0 of 5 kilohms,
The propagation delay time of the level converter shown in Figure 8 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpFO) -・5,65
nsectpLH (when C5=OpF)・-・4
．． 16nsecKHL ・0.
42nSeC/pFKLH...0.37nsec/p
F Furthermore, the level converter 201 shown in FIG. 6 can obtain desired characteristics for the same reason as the case shown in FIG. 27.

The level converter 201 in FIG. 29 is connected to a PN junction diode D to ensure that the transistor QA is turned off, and a shield barrier diode D to discharge the pace charge of the transistor Q. The only difference from the level converter 201 shown in FIG. 23 is that the level converter 201 shown in FIG.

tpHL (when C5=OpFO)"1.72nse
ctpLH (when C5=OpF) - 5.44n
secKHLl-10,32nsec/pF K LH= 0.29 n5ec/pF Furthermore, the second
The level converter 201 in FIG. 9 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter of FIG. 30 has a resistor RI in FIG.
4 is replaced by a resistor R14 of 25 kilohms and a resistor R□ of 5 kilohms, and the resistor R1 has a ratio W/L of 24
P-channel MO8FET ME set to /3)
I? It differs from the one in FIG. 29 only in that it is replaced by . Since Mp, , operates as an active load element of Q, the voltage gain of the amplifier Q@#Mp+y becomes an extremely large value.

Regarding FIG. 30 as well, the propagation delay time and its dependence on output capacitance were confirmed as follows.

t PHL (However, when C5=OpF) -・2.2n
sectpLu (when C5=OpF) -5,2n
secKHL...0.4
n5ec/pFKLH...0.3 n5ec/pF Furthermore, the level converter 201 in FIG. 30 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 in FIG. 31, transistors Q, , Q, beam 2/button transistor +Qs are charging output 2/transistor 1Q4 is a PNP emitter 7 lower transistor, and DI is a level shift transistor. Toki・
barrier diode.

D is a PN junction diode for level shifting.

is a PN junction diode to ensure that the transistor Q is turned off, and D6 is a Schottky barrier diode to clamp negative noise at the input terminal. Resistance too. , R, , R, and 6 are set to 5 kilo ohms, 8 kilo ohms, and 20 kilo ohms, respectively. The collector signal of the drive transistor Q is CM as a voltage amplifier.
P-channel MO8PET that constitutes the OS inverter
Mp+a and N channel, tbMO8FET Mn,
The drain output of both M08 FE'I' is applied to both gates of MO8FET for switching.
Mp.

is applied to the gate of M p14 r M nu +
The six ratios W/L of M p+s are 24/3 and 32/, respectively.
It is set to 3,64/3. MOS FB'r
The drain output of Mp+s is applied to the pace of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter 201 shown in FIG. 31 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpF)...1.
94-3.84 n5ectpx, ii (however, C5=
OpF)...4.64~5.44 n5ecK
HL, ...0.38 n5
ec/pFKLH...0.30 nsec/pF Furthermore, the level converter 201 in FIG. 31 can obtain desired characteristics for the following reason.

(1) Forward voltage VFt of switching barrier diode D, 0.35 to 0.41 volts, forward voltage VF2 of PN junction diode D, approximately 0.75 volts, transistors Q, , Q, , Q The pressure between the pace and emitter of Vngx * Vngz * VBK4 is approximately 0.75
Since it is volt, the input sledge 1 hold voltage vtth at which transistors Q, , Q, are turned on is as follows.

Vjth=-VBx4+Vr*+Vag2+Vagt=
1.5 volts (2) The output transistors Q, , Q, which discharge or charge the output capacitance Cs, are composed of bipolar transistors with small output resistance, so the switching operation speed or propagation delay time and its output capacitance Dependency can be reduced.

(3) Since Q+ and Qt are double-amped transistors, their storage time can be reduced.

(4) When the collector potential of the driving transistor Q rises and the charging bipolar output transistor Q switches from off to on, the CMOS inverter Mp1
4. MnI4 just amplifies the change in the collector potential of Q and transmits it to the base of Q.
The extremely large gate input impedance of T Mp142Mn++ prohibits the direct flow of a large kina base current from the collector of Q to the base of Q, and the base current flows to the base of Q through the small on-resistance of Ml)ts. is supplied, so the output transistor Q,
switching speed can be improved. In FIG. 3, the dependence of the propagation delay time on the output capacitance of the level converters shown in FIGS. 14, 19, 22, and 33 is shown by a dashed line, and It can be seen that the dependence of either one of the propagation delay times on the output capacitance has been improved.

Next, a plurality of 0MO8-Ts of the output buffer 22 in FIG.
The TLv Pel converters 221, 222-22m will be explained. These level converters 221° 222...22
The essential characteristics of m are as follows.

Margin below (1) Each level converter 221.222...22
The input threshold voltage Vith of m is the high level output voltage 4 of the CMOS low level output voltage 0.6 volts.
．． It is set between 4 volts.

(2) An output transistor Hapai Bora transistor which discharges the output load capacitance CX of each level converter 221, 222...22m in response to the input signal supplied to its input terminal. It is structured differently.

Furthermore, the level conversion 6221.22 of the output buffer 22
The preferred features of the preferred embodiment of 2...22m are as follows.

(3) A high input impedance circuit is connected between the base of the drive transistor Qi1 that drives the base of the discharge output transistor Q+o and the output of the internal logic block 21.

(4) The high input impedance circuit in (3) above has a function of logically processing a plurality of output signals of the internal logic block 21.

(5) Discharge output transistor Q. and the drive transistor Qtt are constituted by a clamped transistor with a thick barrier diode.

(6) Output transistor Q that charges the output load capacitance Cx
Reference numeral 11 is composed of a bipolar transistor.

(output transistor Q for discharging in response to a control signal,
. and charging output transistor QI! By turning off the output terminal OUT at the same time, the output terminal OUT becomes a floating state.
It has the function of controlling.

(8) Level converters 221, 222-...22
m has an open collector output format.

32 to 34 and 36 show various circuit examples of the level converter 2210 of the output buffer 20 according to the embodiment of the present invention, and all of these level converters are shown in (1) above.
) and (2). Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

In the level converter 221 of FIG. 32, QI0 is the output transistor + for discharging the output load capacitance it Cx.
Q++ is Q. Drive transistor +Q to drive
u is a precautionary output transistor pQts that charges the output load capacitance Cx. QI! Current amplifying transistor s Rso for transmitting the pace of
tRs+tQl4 is an active pull-down circuit for discharging the base charge of QCs.

Q, *'ri multi-emi, ri-transistor, R
o is the collector resistance of Qll, Rlj is Ql! A resistor for discharging the pace charge, DI. is a Schittky barrier diode for discharging the pace charge of Ql, Rs4 is a resistor for limiting the collector current of Qtt + Qts, and R8 is a pace resistor of Qss.

Furthermore, P channel MO8F of internal logic block 21
ET M,,M, and N-channel MO8FETM,,M
, 0MO8-NAND gate 21 made by Ml
The output of 1 is applied to the first emitter of multi-emitter transistor Qrs, and the output of 0MO8-NAND gate 21
The output of 0 MO8 is applied to the second emitter of the QCs.
The output of the -NAND gate) 213 is applied to the third emitter of Qss. Therefore 1. The level converter 221 not only has a level conversion function but also a logic processing function as a three-man NAND gate.

Furthermore, the level converter 221 of FIG. 32 can obtain desired characteristics for the following reasons.

(1)) The pace-emitter voltage VBE15 of transistor Qts is approximately 0.75 volts, and the pace-emitter voltage VBE15 of transistor Q
The voltage across the collector, VBC, is approximately 0.55 volts, transistor Q. eQu pace-emitter voltage V B z
tZ.

Since VBE, 11 are about 0.75 volts each,
Input threshold voltage vt of level converter 221
th is set as follows.

Vi th =-Vents +VBC111+VBE
11 +Vngt.

=-0,75+O15!5+0.75+0.75=1.
Output transistor Qto+Q1f that discharges or charges the output load capacitance Cx of the 3 volt (2) level converter 221
Since fi is constituted by a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistor Q+or Qtt + QCs
+Ql4* Since QCs is a clamped transistor, its storage time can be reduced.

(4) Since the multi-emitter transistor QCs has a logic processing function, the degree of freedom in designing a master slice type or gate array type logic semiconductor integrated circuit device IC is improved.

However, when the output of the 0MO8-NAND gate 211 is at the low level, the level converter 221 of FIG.
Since a large current of 0.4 milliamps always flows into the output of the NAND gate 211, 0MO8-NAND
The on-resistance ROM is set by setting the ratio W/L of N-channel MO8FETM, M4 of the gate 211 to a large value of 100/3.
must be a small value. This not only leads to a decrease in the integration density of the integrated circuit device IC, but also
8FETM, 0M because the gate capacitance of M4 also increases.
The inventor's study revealed that the switching speed of the O8-NAND gate 211 decreases.

FIG. 33 shows a circuit diagram of a level converter 221 developed to solve the above problem.
Emitter transistor QI6 has been replaced by a high input impedance circuit described below.

In other words, such a high input impedance circuit in FIG. 33 consists of a PNP input transistor U4. ,,NPN
Emitter follower transistor Q+a+Silicon barrier diode DIt e DIt.

It is composed of resistors R, , R□, and R1-.

Further, the level converter 221 includes a PNP) transistor Q,
,,NPN) transistor Qto-PN junction diode D
, , 'Resistors R, , and includes a ninth control circuit for controlling the output terminal 0UT1 to the 70-Ting state.

PNP) transistor Q of this control circuit. The base of
P channel M'08FE in internal logic block 21
TM, and N-channel MO8F'ETM.

0MO8-NAND gate 21 constructed by special arrangement!
It is driven by the enable signal EN of.

Note that an inverted enable signal EN is applied to the input button of the 0MO8-NAND gate 211.

Furthermore, since this control circuit is added to the level converter 221, the rc
PNP input transistor input transistor barrier
A diode I)+s is added.

Therefore, when the enable signal EN becomes low level, the transistor Q1゜#QllllQB of the level converter 221
Since p Qts is turned off at the same time, its output terminal OU
'l' is in a floating state.

On the other hand, when the enable signal EN becomes high level, the level converter 221 also has a logic processing function as a two-man NAND gate, so the degree of freedom in designing the integrated circuit device IC is improved.

Furthermore, one block barrier diode D111D,
, , D, , +7) 791 direction no' is pressure Vro, v
F121 VF13 0.35 to 0.41 volts, PNP input input Ql? + QCs t
Qt. Base-emitter voltage VBIC17 reference VBi
18 m VBKI9 is approximately 0.75 volts (NPN)?
Njista Q. + Qls + Base-emitter voltage of QCs VBEIOe VlgZl 1 VaguF
i about 0. ．． Since it is 75 volts, for example, a PNP transistor Ql? The CMOI applied to the base of 9, N
Regarding the output voltage of AND gate 211, transistor Q
1°, Q,.

The input threshold voltage Vi th at which V is turned on is as follows.

Vi th = −VBK17 +Vagta +Va
g11 +Vagt.

= 1.5 volts. Additionally, an output transistor Q, which performs discharging or charging of the output load capacitance Cx. *Qtt is composed of a bipolar transistor with small output resistance, so
Switching speed or propagation delay time and its dependence on output capacitance can be reduced. Also, transistor Q. ＃Qll ＃Qll e Ql4 s Q
l. Since it is a clamped transistor, its delay time can be reduced.

However, in the level converter 221 of FIG. 33 as well, when the output of the 0MO8 NAND gate 211 is at a low level, a negligible current flows from the base of the PNP input input transistor Q0 to the output of this gate 211. Therefore, the inventor's studies have revealed that the above-mentioned problem cannot be completely solved.

FIG. 34 shows a level converter 211t, fJ, 3, which is finally solved to almost completely solve this problem.
The multi-emitter transistor Ql in Figure 2 has been replaced by a high input impedance circuit constructed from MO8FETKs as explained below.

That is, in FIG. 34, such a high input impedance circuit FiN channel MO8FETM11Ms* −
It is composed of a Mxs-P Ni1 combination diode D0. M, 1. The drain-source paths of Ml, , Ml are connected in parallel, and each gate is connected to the internal logic processor 0M08-NAND gate 211, 212゜213, respectively, and a PN junction diode is connected to these drain-source paths. D9 are connected in series.

Maji, resistance R3o, R,,, 几m! ＋ Rml ＋
R! 4 *几, , are set to 2 kilo ohms, 4 kilo ohms, 10 kilo ohms, 4 kilo ohms, 50 to 75 ohms, and 16 kilo ohms, respectively. transistor Q
1°.

The area of each emitter of QII + Qts r Ql4 is
672pn, 132pmI, 363μrn” respectively.
, 187 μm”.

242μrrr&c is set.

Furthermore, in order to further improve the logic processing function of the level converter 221, the drive transistor Q1
a second drive transistor Q having the same emitter area as 1;
,. are connected in parallel with the QII, and like the high input impedance circuit above, an N-channel MO8FETM, 4. M
, ,M, , PN junction diode D1. , resistance 31
A second high input impedance circuit is constructed, and this level converter 221 is connected to a six-person complex.
It has a logic processing function as a gate circuit.

Furthermore, when the level converter 221 is supplied with a low-level enable signal EN from the internal logic block 21, its output terminal OUT.

A control circuit for controlling the floating state is also added. This control circuit is an N-channel MO
8PETM,, Transistor Q□.

Qtte Q! s e resistance R4゜, R,,,R,,
, R, , Shitatki Barrier Diode DIll
+ DI4 + DIS rDl.

Furthermore, in the level converter 221 of FIG.
The input threshold voltage at each gate of the MO8FETM, old... MH6, is set to an intermediate value of 2.5 volts between the icMOS low level output voltage of 0.6 volts and the CMOS high level output voltage of 4.4 volts. The ratio W/L of the ninth setting, M□...M16, is set as follows. Furthermore, at this time, M......M
,. The threshold voltage VTH of the PN junction diode DI4 is set to approximately 0.75 volts, the forward voltage VF14 of the PN junction diode DI4 is set to 0.75 pol)K, and the
60 channel conductance β. is 60X10-'
[1/It is set to Ohmco.

Consider the case where only MO8FETM,1 is on, and calculate the drain voltage Vy, etc. from its gate voltage VX, gate-to-source voltage VG8+drain current.

It is assumed that M is biased in the saturated region at this time.

Vx = V as + VFI a
``・(1)VY''''VCCass' ID From formulas (1) and (2), ...(3) By the way, as Vx increases, Vy decreases and transistor Q+o*Qs+ turns off. VX corresponding to is considered as the input threshold voltage.

Transistor Q. The drain voltage VyFi at which +QIl is turned off is determined as follows.

V y ”” V B E 11 + V B g 1
0 From equations (3) and (5), ... (5) From equations (4) and (6), L R,, βo (VX VFI4-V
TH)”...(Force Vcc2>f 5 Holt* VBEII (!: V
BEIO voltage 0.75 volts, R8, 16 kilo ohms, I0 60 x 10-' [1/ohmco, Vx 2
．． 5 volts VFI4 is 0175 volts * VTH is 0
If we put the condition of 75 volts into the above (method), W 5-0.75-0.75 2X10'
IL 16X10” 60 (2,
5-0,75-0,75)”960
1"=-xio" =7.29-- Thus, M,...M8. The ratio W/L is 22
By setting /3Ilc, the input threshold voltage of the level converter 221 can be set to 2.5 volts.

The inventor has confirmed that the embodiment shown in FIG. 34 having the above configuration has the following propagation delay time and its output capacitance dependence.

tpHL (when C5=OpF) --8,8n5
ectpLH (when C5=OpF') = -7
,8n5ecKHL=O:H
n5ec/pFKLH=0;01 n5ec/
pF In FIG. 5, the output load capacitance dependence of the propagation delay time of the level converter of the embodiment of FIG. 34 is shown by a dashed line, and the first and second propagation delay times tPHL,
(Each output capacitance dependence KHL of PLH.

It can be seen that KLH has been improved.

Further, the level converter 221 shown in FIG. 34 can obtain desired characteristics for the following reason.

(1) As described above, transistor Q1o+Q+t
Base-emitter voltage of B E 10 r VB
E 11 K 1 power supply voltage Vcc + resistance ⇠, MO
8FETM, -M,.

channel conductance β. By setting the ratio W/L of MO8FETM, . 2 between 6 volts and 4.4 volts
．． It can be set to 5 volts.

(2) An output transistor Q, which discharges and charges the output load capacitance Cx. , Q,1 are constructed of bipolar transistors with small output resistance, so that the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Since a high input impedance circuit configured with MO113FETM,1 is connected between the base of the drive transistor Q1m and the output of the internal logic block 21, The current flowing into the output of the 0MO8-NAND gate 211 from the gate of the 0MO8-NAND gate 211 to the internal logic block 21 can be reduced to a negligible level.
A significant increase in the ratio W/L of the N-channel MO8FET can be prevented.

(4) MO8FETM high input impedance circuit,
.

Since Ml, , M, and s perform three-man OR logic, the logic processing function of the level converter 221 is improved.

(5) Two drive transistors'; L+ e Qt. If the level converter 221 also performs AND logic, the logic processing capability of the level converter 221 is further improved.

(6) Transistor QIa r Qu t Qu p
Qt4 + Qt.

Since it is a clamped transistor, its storage time can be reduced.

(7) By setting the enable signal ENi to low level, the output transistor Q+o+QI of the level converter 221
t is turned off at the same time, the output terminal 0TJT becomes a floating state, and this output terminal OUT.

During parallel operation in which the output terminal and the output terminal of another logic circuit (not shown) are connected, a signal can be output from this output terminal OUT.

FIG. 36 shows a level converter 22 according to another embodiment of the invention.
An example of circuit No. 1 is shown below, and its output terminal 0LJT.

is commonly connected to other open collector output type semiconductor integrated circuit device IC power terminals for TTL level logic,
This common connection point is a 2 kilohm load resistor R1,oo
It is connected to a 5 volt power supply voltage Vcc via a power supply voltage Vcc of 5 volts.

The open collector output type T'1' L level circuit device IC' includes, but is not particularly limited to, Schottky barrier diodes D, D, D, multi-emitter
Transistor Qao + Cranked transistor Qas
to Q, 4. It is composed of resistors R4° to R44 and a PN junction diode D4. However, output transistor Q4. Collector n, f −7' y is connected to terminal 43 as output terminal as collector output.
On the other hand, inside the circuit device IC/, no circuit element is connected between the power supply voltage Vcc and the collector of the output transistor Qns.

In the level converter 221 of FIG. 36, the circuit device I
Any circuit elements inside C include the power supply voltage Vcc and the output transistor Q. The level converter 221 is formed exactly the same as the level converter 221 shown in FIG. 34, except that it is not connected to the collector of the level converter 221 of FIG.

Thus, the output terminal of the circuit device IC and the output terminal of the circuit device IC' are connected in the form of a so-called wired OR circuit. Further, by setting the enable signal EN to a low level, the output transistor Q+o of the level converter 221 is forcibly turned off, and the level of the output terminal OUT can be made independent of the output of the internal logic block 21.

FIG. 37 shows the layout of each circuit block on the surface of the semiconductor chip of the logic semiconductor integrated circuit device IC according to the embodiment of the present invention.

The central part (area surrounded by broken lines!) of the semiconductor chip 300 K is a 0M08 circuit (pure CMOS circuit or quasi-CMOS circuit).
An internal logic block 21 configured by a circuit) is wired, and an input level converter (inside a triangle with diagonal lines) shown in FIG. (shown) is 9th 34th
A plurality of output level converters shown in the figure (indicated by white triangles) are arranged alternately, and the semiconductor chip 30 is similarly arranged.
The input level converter shown in FIG. 31 is located on the right side of 0 (the area surrounded by the broken line lt), the bottom side (the area surrounded by the broken His), and the left side (the area surrounded by the broken i/4). Further, a plurality of output level converters shown in FIG. 934 are arranged alternately.

Upper part! , the number of input bonding pads corresponding to the number of level converters (indicated by solid line rectangles) and the number of output bonding pads corresponding to the number of output level converters (indicated by solid line rectangles). (represented by a square)
are arranged, the input part of each input level converter faces each input bonding pad, the output part of each input level converter faces the internal logic block 21, and the input part of each output level converter faces each input bonding pad. Facing the internal logic block 21, the output section of each output level converter faces each output bonding butt.

A plurality of input bonding pads and a plurality of output bonding pads on the right side of the right side Mlt, a plurality of input bonding pads and a plurality of output bonding pads under the lower side l, the left side! , the multiple input pads and multiple output pads on the left are on the top!
, are arranged in the same way as in .

Right side part 1tp Lower side part 13r The direction of the input/output part of the input level converter in the left side part 14 and the input/output part of the output level converter
The direction of the output part is the upper part! .

The same is true for .

[30 power bonding pads for supplying the source voltage Vcc; 30 grounding bonding pads 31 disposed on at least one of the four edges of the semiconductor chip 300 and connecting to the first grounding point; At least one of the above four etched parts is formed.

The semiconductor chip 30 having the T layout shown in FIG.
0 is physically attached to the surface of the tab lead LT of the metal lead frame L shown in FIG. 38')'1! connected in close contact with each other.

In the lead frame L in FIG. 38, this lead frame LP has lead portions L1, L, 6. The opening part. .

It has a dam portion LD with diagonal lines. However, in reality, the same applies to the parts corresponding to the lower right, lower left, and upper left of the semiconductor chip, so the lead frame L
, is the part Lo + defined by the shaded dam part
')-do part, ~L64. This is a metal D-processed thin plate for packaging in which tab leads LT are connected to each other.

After the back surface of the semiconductor chip 300 is connected to the front surface of the tab lead LT, wiring of bonding wires (eg, gold wire, aluminum wire, etc.) described below is performed.

By using a commercially available wire bonding device i1'e, wire 1. The power supply bonding pad 30 and the lead portion LS4 are electrically connected by the VCM, and then the input pad and the lead portion are connected by the wire J, and the wire L? The output pad' and the lead part are connected by the wire L, and the output pad and the lead part are connected by the wire L*vc.
s and wire l.

Depending on the input pad and lead part, wire 1I
Grounding pad and tab lead LT from IVC
are electrically connected to each other.

・Lead frame L after the wire wiring described above is completed.
T and the semiconductor chip 300 are delivered to a mold for resin sealing, and liquid resin is injected into the inside of the time portion LD of the lead frame L. This dam portion LD prevents the resin from flowing out.

After the resin has solidified, the lead frame LP, the semiconductor tip 300, and the resin, which have become an integrated structure, are taken out of the mold, and each lead portion is removed by removing the dam portion LD using a 7-less machine or the like. , %L, 4 can be electrically isolated.

The leads L, -L64 protruding outside the solidified resin are bent downward as necessary, and as shown in the completed diagram of FIG. 39, the logic semiconductor integrated circuit device IC sealed with the resin 301 is completed. Complete. As shown in the figure, no special heat dissipation fins are provided to actively dissipate the heat generated by the circuit device ICFi semiconductor chip 300 to the outside of the sealing structure.

If such heat dissipation fins are installed, the circuit device IC
costs increase undesirably.

In addition to the above-mentioned resin encapsulation method, there are also ceramic encapsulation methods and methods using a metal case as a method for encapsulating semiconductor chips, but from the viewpoint of the cost of the circuit device IC, the above resin encapsulation method The sealing method is the most advantageous.

In the logic semiconductor integrated circuit device IC according to the embodiment using the drawings of FIGS. 37 to 39, the input buffer 2
Input level converter 201゜202 as 0...
・Total number of 20n is 18 to 50 + CMOS gate 211゜212...21 as internal logic block 21
The total number of J is 200 to 1530, the output level converter 221゜222...22 as the output buffer 30
Despite the fact that the total number of m is 18 to 50 and the semiconductor chip 300 is a large-scale semiconductor integrated circuit device, the circuit device IC can have a structure without heat dissipation fins for the following reasons.

That is, each CMOS gate 211, 212...211! as the internal logic block 21! The power consumption per gate is extremely low at 0.039 milliwatts, and the power consumption of the entire internal logic block 21 having 200 to 1530 gates is extremely low at 7.8 to 59.67 milliwatts. Input pad 772 according to the embodiment of FIG.
Each input level converter 201, 202 as 0...
...20n contains many bipolar transistors, so the power consumption per converter is 2.6 μI
The total power consumption of the input buffer 20 with 18 to 50 converters is as large as 46.8 to 130 milliwatts. Each output level converter 221, 222 as the output rose 2a 20 according to the embodiment of FIG.
Since 22m contains many bipolar transistors, the power consumption per converter is as large as 3.8 milliwatts, which is the power consumption of the entire output buffer 22 with 18 to 50 converters! It is large at r168.4 to 190 milliwatts.

From the above data, the input buffer 20. of converters is 18.
21° internal logic block with 200 gates and 18 converters
In the output buffer 220 circuit device IC, the 37th
The center of the semiconductor chip surface in the figure! . In contrast, 6.4% of the heat is generated in the comparative part 1+, l*
-1s, J4 total heat of 93.6/<-cents is generated.

In addition, the converter 500 Å capacufa 20. Number of gates: 153
0 internal logic block 21. 7 output batteries with 50 converters
In the circuit device IC of A 22, 15.8% of the total heat is generated at the central portion 10 of the semiconductor chip surface shown in FIG. ! 1,14 total 8
4.2 percent heat is generated.

By the way, as shown in FIG. 37, the internal logic block 21 that generates a small amount of heat is arranged in the central part 70 of the chip, and the input buffer 20 and output buffer 21 that generate a large amount of heat are located in the central part 70 of the chip.
2 means each side l of the depth.

It −Is, 14 Then, from FIG. 38, each side It, l! , In, 14, a large amount of heat is transferred to the outside of the circuit device IC (% to the printed circuit board K) via the tab lead LT and the lead part as a grounding lead.
If an IC is mounted, the ground line of the printed circuit board)
Instead of just taking out K, it is connected to the outside of the circuit device IC (particularly when the IC is mounted on a printed circuit board, the signal line of the printed circuit board and power line).

In contrast to the above embodiment, the input buffer 20 and output buffer 22, which generate a large amount of heat in the central part 10 of the chip, are rearranged, and the central part 10 is re-arranged. . It has been confirmed through calculations by the inventor that if the internal logic block 21 is arranged around the central part 10, a large amount of heat in the central part 10 is not easily extracted to the outside of the circuit device IC.

For the above reasons, the circuit device IC of the above embodiment can have a structure without heat dissipation fins. Furthermore, since the circuit device IC has a resin-sealed structure, it has become possible to significantly reduce the cost of the IC.

FIG. 40 shows the logic semiconductor integrated circuit device IC according to the embodiment using the drawings in FIGS.
L-level logic semiconductor integrated circuit/device 401.402
"=4On, 501 to 505°600 are mounted on a printed circuit board to form a block diagram of an electronic system.

In the figure, a device 4 having an output at the T'I'L level
Each output of 01, 402...40n is connected to circuit device I.
The outputs of the circuit device IC are supplied to the inputs of the TTL input level circuits 501 . . . 505, respectively.

Furthermore, by commonly connecting the output OUT of the circuit device IC and the output of the device 600, the output of the circuit device IC, 600
is the input buffer 2 of the circuit device IC that executes parallel operation.
A large amount of heat generated in the output buffer 22 and the output buffer 22 can be dissipated to the ground line of the printed circuit board, the power line, the input signal line, and the output signal line.

Also, an enable signal E provided to output back 722
When set to Nt-low level, its output 0UT1. OU
T, . . . OUTmit is in the floating ink state, and the input levels of the devices 501, 502, and 503 are set by the output level of the device 600.

In addition, the input buffer 20 and the devices 401, 402...
...40n, high speed is obtained at the interface between the internal logic block 21 and input buffer 20, and twinter 7 ace is obtained between the internal logic block 21 of the output buffer 22. High speeds are obtained, and also at the interface between the devices 1501...505 and the output buffer 20.

[Effects] According to the above embodiments, favorable effects can be obtained for the following reasons.

(1) By configuring the output transistor that charges or discharges the output capacitor Cs of the input level converter 201 with a bipolar transistor, the
Compared to a FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of an input level converter and its output capacitance. Dependency can be reduced.

(2) In the input level converter 201, a barrier diode that performs majority carrier operation is connected between the base and collector of the bipolar transistor driven into the saturation region. Since the injection of minority carriers from the collector layer into the base layer can be reduced, the accumulation time can be reduced.

(3) Input level converter 20 according to a preferred embodiment
1, the drive transistor Q is connected via a MOB buffer with high input impedance and voltage amplification function.
By transmitting the pace signal or collector signal of , to the pace of the charging bipolar output transistor Q, the operating speed of the output transistor Q is improved due to the high input impedance and voltage amplification function of this MO8 buffer.

(4) In the input level converter 201 according to the preferred embodiment, the input terminal IN and the drive transistor Qt
By connecting the 5cit PNP emitter/7lower transistor Qs and the PN junction diode D, not only can the input level converter 201 input threshold and hold voltage be set appropriately, but also the PNP transistor Q can be set properly. Since the current amplification effect improves the input impedance at that pace, it is possible to reduce the influence of the output impedance of the TTL level signal source connected to the input terminal IN.

(5) By configuring the output transistor that charges or discharges the output load capacitance Cx of the output level converter 221 with a bipolar transistor
Compared to a FET, the Bibo2 transistor has a small output resistance and a large current amplification factor even though its element size is small, and a large buying/selling current or discharge current can be obtained, which reduces the propagation delay time of the output level converter and its Output capacitance dependence can be reduced.

(6) In the output level converter 221, there is a barrier between the bipolar transistor C driven in the 1!2 range and the collector that operates as a majority carrier.
Since the diode is connected, injection of carriers from the collector layer into the space layer can be reduced, so that the accumulation time can be reduced.

(7) In the output level converter 221 according to the preferred embodiment, there is a high input impedance M between the output of the internal logic block 21 and the pace of the drive transistor Qll.
By connecting the O8 circuit, the MO of this MO8 circuit
Since the current flowing from the gate of the SFET to the output of the internal logic block 21 can be reduced to a negligible level, it is possible to prevent a reduction in the integration density and switching speed of the output circuit of the internal logic block 21.

(8) In the output level converter 221 according to the preferred embodiment, the multiple output signals of the internal logic block 21 are processed by a logic processor in the high input impedance MO8 circuit, thereby improving the degree of freedom in assembling logic semiconductors using the master slurry method. 7, in the output level converter 221 according to the preferred embodiment, the enable signal EN causes the output terminal 0UT1 to
Since a control circuit is arranged to control the output terminal to a 70-setting state, when this output terminal OUT and the output terminal of another logic circuit are commonly connected, the level of this common output terminal is set to 70-. It can be set by the output of the logic circuit.

α0 According to a preferred embodiment, the internal logic block 21 is arranged in the center of the semiconductor chip surface, and includes a plurality of bipolar transistors, and its power consumption is reduced by constructing it with a pure CMOS circuit or a quasi-CMOS circuit. Input level converter 201 with large power consumption...
... and the output level converter 221 on the periphery of the semiconductor chip surface, heat dissipation is facilitated. It is possible to reduce the cost as a structure.

αυ According to the preferred embodiment, the logic semiconductor integrated circuit device IC has a resin-sealed structure, which makes it possible to reduce its cost.

α On the other hand, the input terminal IN of the input level converter 201,
Since the voltage is not applied to the gate of the ViM08FET, but to the cand of the switch barrier diode D, or the pace of the PNP transistor Q, the breakdown strength against the surge voltage applied to the input terminal IN is reduced. Just in case you can improve.

Although the specific invention made by the present inventor has been specifically explained based on Examples, the present invention is not limited to the above-mentioned Examples, and various modifications can be made without departing from the gist thereof. Needless to say.

For example, in FIG. 6, the level converters 201, 202...20n of the input buffer 20 are ECL-0
MO8 level conversion is executed, and the level converters 221, 222...22m of the output buffer 22 are 0MO8-
It may also be configured to perform ECL level translation. For this purpose, an input buffer 20. Internal logic block 21. It goes without saying that it is sufficient to operate the output buffer 22 at the ground level and the negative power supply voltage -VER. Similarly, in FIG. 6, the level converters 201, 202...2 of the input buffer 20
0n executes L-CMOS level conversion, and level converters 221 and 222-'' of the output buffer 22 = 2
It is also possible to configure it to perform 2mViCMOS-i''L level conversion.

Furthermore, in the embodiments shown in FIGS. 14 to 21, 23 to 26, and 29 to 30, the PNP emitter 7 lower transistor Q4 of FIG. P.N.
A junction diode Dzf may be added.

The reason why the ratio W/L of the MOSFET is set to 3 is because the channel length of the MOSFET is 3 μm, and currently, due to improvements in photolithography, this channel length LFi is 2 μm.

As miniaturization progresses from 1.5 μm to 1 μm or less, the ratio W/L will correspondingly become smaller.

Further, along with this miniaturization, the element dimensions of bipolar transistors will continue to be reduced, and the resistance values of resistors in the circuit will also change.

A large number of leads L,...L from the sealing resin 301
The method for taking out 64 is also limited to the embodiment shown in FIG. The outer shape of the sealing resin 301 is not rectangular but almost square, and there are many leads L from all four sides.

... Taking out L64 is more appropriate for downsizing the lead frame LT and circuit device IC, and improves the mounting density on the printed circuit board.

[Field of Application] The above description mainly describes the case where the invention made by the present inventor is applied to a logic semiconductor integrated circuit device, but the present invention is not limited thereto.

For example, on a semiconductor chip there may be an input buffer 20° internal logic block 21 . Not only the output buffer 22 but also bipolar analog circuitry as required.

MOS/analog circuit, P channel MO8/logic, N channel MO8/logic izL circuit, ECL
It goes without saying that it is also possible for any of the circuits to be placed on a semiconductor chip.

[Brief explanation of the drawing]

FIG. 1 shows a block diagram of a logic semiconductor integrated circuit device IC that was studied by the inventor of the present invention prior to the present invention, and FIG. 2 is a block diagram of an input buffer that was studied by the inventor of the present invention prior to the present invention. 3 shows the output capacitance dependence of the propagation delay time of the input buffer of FIG. 2, and FIG. 4 is a circuit diagram of the output buffer studied by the inventor prior to the present invention. 5 shows the output load capacitance dependence of the propagation delay time of the output buffer 7 in FIG. 4, and FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device according to an embodiment of the present invention. Figures 7 and 8 are 0MO8-NA of the circuit device in Figure 6.
, FIG. 9 and FIG. 10 show a circuit example of the circuit device CMOS-NOR gate 211 of FIG. 6, and FIGS. 11 and 12 show a circuit example of the circuit device CMOS-NOR gate 211 of FIG. FIG. 13 shows an example of the circuit of the 0MO8-R-87 lip 70 in the internal logic block 21 of the device, and FIG. 14 to 31 show various circuit diagrams of the level converter 201 of the input hacker 20 according to embodiments of the present invention, and FIGS. 32 to 34 and 36 The figures show various circuit diagrams of the level converter 221 of the output buffer 21 according to embodiments of the invention, and FIG. 35 shows the first and second propagation delay times 1PHL. Figure 37 shows the input/output waveform diagram for defining 1PLIH, Figure 37 shows the layout of each circuit block on the semiconductor chip surface of the semiconductor integrated circuit device for MIf#L according to the embodiment of the present invention, and Figure 38 shows the layout of each circuit block on the semiconductor chip surface of the semiconductor integrated circuit device for MIf#L according to the embodiment of the present invention. A lead frame L of a semiconductor chip of a logic semiconductor integrated circuit device according to an embodiment of the invention. 39 shows a completed diagram of the circuit device according to the embodiment of the present invention after resin sealing, and FIG. 40 shows the state of connection of the circuit device to the tab lead LT and the bonding wire. 1 shows a block diagram of an electronic system configured by mounting the circuit device according to the embodiment and other circuit devices on a printed circuit board. Figure Figure Figure Figure D- Figure Figure Figure Figure 16 Figure Figure ■ Figure Figure Figure Figure ■ Figure Figure 20 Figure 22 Figure 23 Figure 24 Figure 25 Figure 32 Figure 34 Figure 37 Figure 39 Figure 40

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising an internal logic block including a CMOS circuit and an input circuit including a bipolar transistor for driving an input of the internal logic block, wherein the internal logic block includes a storage means. A semiconductor integrated circuit device characterized by the presence of.