JPH02223219A - Electronic system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when used in semiconductor integrated circuit devices, for example, logic semiconductor integrated circuit devices whose input/output levels are TTL level, SMM level, and CMOS level. be.

[Background technology]

In FIG. 1, the input/output level studied by the inventor of the present invention prior to the present invention is the TTL level.

1 shows a block diagram of a logic semiconductor integrated circuit device IC whose internal logic level is CMOS level.

Such a circuit device IC receives TTL level input signals IN, .
Input buffer 7710 for converting the level of INK "4Nn to CMOSv Verno signal. Internal logic block 11 for executing logic operation at CMOS level. 0MO8 level output signal of this internal logic block 11. TT
Each circuit 10, 11, and 12 includes an output buffer 12 for level conversion to an L level output signal, and each circuit 10, 11, and 12 is supplied with a 5 volt power supply voltage Vcc and is properly grounded.
There is.

Input terminals IN, INt...IN of the input buffer 10
The high level input voltage Vi old ○ supplied to n is 2.0 volts or more, and this low level input voltage Vit1o is 0.
Set to 3 volts or less. Therefore, the input buffer lO
Input threshold voltage V for the input terminals IN, , IN, . . . INn! th1o is 0.8 volts and 2
．． It is set at 1.3 to 1.5 volts between 0 volts.

On the other hand, the high level output voltage VOHIO obtained from the output of the input buffer 10 is set equal to the high level input voltage Vinxt of the internal logic block 11, and the low level input voltage VOLIG obtained from the output of the input buffer 10 is set equal to the high level input voltage Vinxt of the internal logic block 11.
is the low level input voltage ViL of the internal Mll block 1
Set equal to tt. Therefore, internal logical block 1
P-channel MO constituting the CMOS inverter in 1
8PET threshold voltage VTPtN channel M08 FET threshold 1 hold voltage VTN
+If the power supply voltage is Vcc, the above voltage VOHIO*
V1) it l *VOLIO* ViLll are each set as follows.

Vouto=Vintt>VCC-IVTPI” (
1) VOLIO=ViLtx<VTN
”(2) Set Vcc to 5 to IVTP I to 0
．． 6H #), if V7H is set to 0.6 volts, V
OHIO and V int l are below 4.4 volts, v
ot, to and Vitxt are set to 0.6 volts or more.

Therefore, the input logic threshold voltage vtth of the CMOS inverter within internal logic block 11 is set to approximately 2.5 volts between 0.6 volts and 4.4 volts.

Similarly, the high level output voltage V of the internal logic block 11
High level input voltage vl of OHII and output buffer 12
H12 is set to 4.4 volts or more, the low level output voltage VOL11 of the internal logic block 11 and the low level input voltage ViL1g of the output buffer 12 are set to 0.6 volts or less, and the output buffer 120 input logic
Threshold Vith* is 0.6 volts and 4.
It is set at about 2.5 volts between 4 volts and 4 volts.

5. The high level output voltage VOH of the output buffer 12 is set so that the output buffer 7 12 generates a TTL level output signal.
II is 2.7 volts or more, its low level output voltage V
OLI! is set to 0.5 volt or less.

FIG. 2 is a circuit diagram showing one of the input buffers 10 studied by the inventor of the present invention prior to the present invention.
.

N-channel MO8FETMn, TMn* + Mns+
It is composed of a resistor RpK. The gate, source, and drain of each MO8FET are designated by symbols g, s, and d, respectively.

First stage CMOS consisting of MP I and Mn, especially
The inverter and the second stage CMOS inverter constituted by M pt and Mn are connected in cascade, and R
p and Mn1 constitute a gate protection circuit for protecting the gate insulating film of M pt and Mn. 2nd row C
The output capacitance C3 connected to the drains of Mp and Mn of the MOS inverter is actually the drain capacitance of Mp and Mn, the output of the input buffer 10, and the internal logic block 1.
10 Wiring stray capacitance between input and internal logic block 11
Its value is determined by the input capacitance of .

Each MO8F ETMpt l Mpm I Mll
The ratio W/L of channel @W and channel length of t r Mnt −Mn is 27/3.5 and 4, respectively.
2/3, 126/3.5, 42/3, and 15/3, and the resistance Rp is set to 2 kilohms.

Figure 3 shows the propagation delay time of the input buffer 7 in Figure 2!
The dependence of the output capacitance C3 of PHL e j PLH is shown, the vertical axis shows the propagation delay time, and the horizontal axis shows the output capacitance Cs.

As shown in FIG. 35, the first propagation delay time t PH
L is defined as the time from when the input INPUT changes with the 50% value as the border until the output 0UTPUT changes from the high level to the low level with the 50% value as the border, and is the second propagation delay time t. PLH is input I
Output 0UT after NPUT changes 50% value as a block
Part 5 when PUT changes from low level to high level
It is defined as the time until it changes from the 0% value.

Note that in FIG. 35, tf is defined as falling time, and tr is defined as rising time.

In this way, as can be understood from Diagram 3, the output capacitance dependence KHL (=tpHh/ΔCs) of the first propagation delay time tPHL of the input rose 7710 in FIG. 2 is approximately 0.8n.
aec/pF, second propagation delay time t PLH output capacitance dependence K LH (=xΔt PLH/ΔOs) is approximately 1.
4nsec/pF, both of which are large.

In the input buffer 10 of FIG. 2, in order to set the manual threshold voltage Vith1o to approximately 1.3 to 1.5 volts, the first stage CMOS inverter M p
Ratio W of channel width and channel length of r and Mn
/L is made large^^, and the propagation delay time t PHL
・In order to reduce the output capacitance dependence of tPLH, KkiL*KLH, Mp and Mn of the second stage CMOS inverter are
Assuming that the ratio W/L of l is both a large value of 42/3, Mpl
The channel conductance of and Mrl is increased.

In order to reduce the double output capacitance dependence KHL input bug 7a 10
This results in a significant increase in the area occupied by the device, which hinders the improvement of integration density.

In other words, although miniaturization is currently being actively promoted in the manufacturing technology of integrated circuits, the lower limit of the channel length of MOS FET is 3 μm in the current photolithography using ultraviolet light exposure, and the ratio W of MOS FET is /L
In order to make the channel width W a very large value, the channel width W must be made a very large value, and ultimately the M
This is because the area of the element region of the OS FET is significantly increased.

On the other hand, FIG. 4 is a circuit diagram showing one of the output buffers 12 studied by the inventor of the present invention prior to the present invention, and is a P-channel MO8FETM P 41 N + +
7 Nell M 08 F B 'l' M 114
It is composed of K. Gate of each MO8FET,
The source and drain are each symbol gr' * dK
Therefore, it is shown.

0MO8 of internal logic block 11 in integrated circuit device IC
The level output signals are Mp4 and Mn of the output buffer 12.
A power supply voltage Vcc of 5 volts is supplied to the terminal No. 30, which is applied to the gate of . Therefore, the input logic threshold voltage Vl of the output buffer 12
To set th12 to about 2.5 volts, use Mp4
The ratio W/L of and M n 4 is set to be equal to each other.

Similarly, a TTLN path 14 is shown in FIG. 4, and this circuit 14 is supplied with a power supply voltage Vcc of 5 volts through terminal No. 35. The output signal of the output buffer 12 at the TTL level is obtained from the terminal No. 20, and is supplied to the multi-emitter transistor Q of the TTL circuit 14 and the wide emitters through the terminal 32.

On the other hand, as a TTL circuit, it is a standard type TTL circuit.

Switch TTL circuit, low power switch TTL circuit
'r L circuit, advanced low power switch 11,
Toki TTL circuits have been announced, and their characteristics are naturally somewhat different from each other.

Further, the output of the output buffer 12 is transmitted to a large number of TTL circuits 14.
It is necessary to drive the 0 inputs simultaneously and in parallel. One measure of this driving capability is that it is possible to drive 20 inputs of the low power Shigeru TTL circuit in parallel.

When the output of the output buffer 12 is low level, the low level
0.0 from one input of the power switch TTL circuit.
The low level input current IIL of 4mA is output from the output buffer 7.
It flows into the drain-source path of ON channel MO8FETMn4. Therefore, since the output buffer 12 drives the 20 inputs to low level as described above, K is Mn
4 requires a total of 8 mA to flow.

On the other hand, the low level output voltage VOL1 of the output buffer 12
As already explained, m must be less than 0.5 volts, so N channel of output buffer at 2 # M 0
8 F E T M n 4 on-resistance ROM is 0
．． It must be set to a small value of 5 volts/8 milliamps and 2.5 ohm seismic intensity.

In this way, in order to make the on-resistance RON of Mn a small value, the ratio W/L of Mfl is set to 700/3 to 100.
We have to make it extremely large, 0/3. On the other hand, in order to set the output buffer 120 input logic threshold 1 hold voltage Vithx to approximately 2.5 volts as described above, the ratio W/L of Ml)4 and Mfl must both be equal values. Therefore, the ratio W/L of O8PET Mp+ between P channels and channels of the output buffer 12 is also 70.
It must be made extremely large, from 0/3 to 1000/3.

This also results in a significant increase in the area occupied by the output buffer 12 on the surface of the integrated circuit chip, which not only hinders improvements in integration density, but also reduces the switching speed of the internal logic block 11 for the following reasons. cause a new decline.

That is, both MO3FETM pa of the output buffer 12
#If the ratio W/L of Mn4 is both set to a large value, the gate capacitance of both MO8FETs Mp4 and Mn4f) also becomes a proportionally large value. These gate capacitances Mp4°Mn, become the output load capacitance of the internal logic block 11, so the output resistance of the internal logic block 11 and these gate capacitances cause a reduction in the switching speed of the internal logic block 11.

On the other hand, the output of the output buffer 12 is not only led out as an external output terminal (terminal 20) of the integrated circuit device IC, but also connected to the input terminals of a large number of TTL circuits 14 via external wiring. A12 output load capacity Cx
is often an extremely large value.

Figure tg5 shows the output load capacitance C of the output buffer 12 in Figure 4.
Propagation delay time jPHL + for x! PLH dependence is shown, the vertical axis shows propagation delay time, and the horizontal axis shows output load capacity.

Thus, as can be understood from FIG. 5, the capacitance dependence KHL (=ΔtpuL/ΔOx) of the first propagation delay time t FIL of the output buffer 12 in FIG. 4 is approximately 0.3 ns.
e c / p F * M 2 propagation delay time tPLH
Capacity dependence K 1,1 ((x=Δtpta/ΔCx)
Both are large, approximately 0.17 n5ec/pF.

Therefore, the problems of the input buffer 100 shown in FIG. 2, which are the background art of the present invention, can be summarized as follows.

(1) In order to reduce the dependence of the propagation delay time of the input buffer 10 on the output capacitance, K is set to
Both MO8PETMP* l Mn of MOS inverter,
The ratio W/L must be increased, which hinders the improvement of the integration density. Especially when the integrated circuit device IC is a master slice type or a semi-custom gate array type.

There is a possibility that a very large number of gate input terminals in the internal logic block 11 are connected to the output of the input buffer 10,
If the output capacitance C8 of the input buffer 10 becomes extremely large, the above-mentioned intermediate point becomes extremely important.

(2) Furthermore, since the first stage of the input buffer 100 is composed of CMOS inverters Mp, , Mfl, even if a gate protection circuit formed by Rp and Mn is connected, no voltage is applied to the input terminal IN. The breakdown strength of the gate insulating films of both MO8FETs against the applied surge voltage is not sufficient.

Further, the problems of the output buffer 12 shown in FIG. 4, which are the background art of the present invention, can be summarized as follows.

(3) In order to set the hold voltage Vithxs for the input logic threshold of the output buffer 120 to approximately 2.5 volts and to increase the current sinking ability of the output buffer 12 at the time of q-level output, both MO8FE T M p4
*The ratio W/L of Mna must be both equal and large, which hinders the improvement of the integration density.

(4) Both MO8FETs Mpa- of output buffer 12
When the ratio W/L of Mn4 is increased, both Mp4゜Mn,
The gate capacitance of is also increased. Therefore, the output resistance of the internal logic block and the gate capacitance of the internal logic block 1
This results in a reduction in switching speed of 1. In particular, the output stage of the internal logic block 11 is a MOS with a large output resistance.
When constructed from PET, this reduction in switching speed becomes a significant problem.

(5) Output buffer 12 is M O8F E T M
Since it is composed of P4-Mn4K, the dependence of the propagation delay time on the output load capacitance Cx is large. This problem becomes particularly important when the output of the output buffer 12 is connected to the input terminals of a large number of TTL circuits 14.

[Purpose of the invention]

The object of the present invention is to provide an internal logic block that generates an output signal of 0M08 level when an input signal of 0MO8 level is applied, and a level converter such as TTL-0M08 level conversion for this internal logic block. In a semiconductor integrated circuit device having a capacitor 7a and/or an output buffer 7a for level conversion such as 0MO8-TTL level conversion, the integration density can be improved, and the input buffer and/or the output buffer 7a can be improved.
The object of the present invention is to reduce the dependence of the operating speed of the motor on the output capacitance and to improve the operating speed.

The above and other objects and novel features of the present invention include:
It will become clear from the description of the invention and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a converting buffer converter for TTL-CMOT level conversion for an internal logic block that operates at the 0M08 level, the output transistor that charges or discharges the output capacitance of the level converter is configured with a bipolar transistor. By this, M
Compared to an OS FET, a bipolar transistor has a small output resistance and a large current amplification factor even with a small element size, and a large charging or discharging current can be obtained, which reduces the propagation delay time of the input buffer and its capacitance dependence It is possible to achieve the purpose of reducing the

In addition, in the level converter of the output buffer for converting the 0MO8-'I'TL level for the internal logic block that operates at the 0M08 level, an output 2 transistor is used to charge or discharge the output load capacitance of the level converter. By configuring the transistor with a bipolar transistor, the bipolar transistor has a small output resistance and a large current amplification factor even though the element size is small compared to a MOS FET, and a generous charging current or discharging current can be obtained. Accordingly, the purpose of reducing the propagation delay time of the input buffer and its capacity dependence can be achieved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

6IiA shows a block diagram of a logic semiconductor integrated circuit device IC according to an embodiment of the present invention, in which a TTL-CM08 level converter buffer 20° that performs the same operation as the input buffer IO of FIG. 1 is shown. Internal logic block 21. which operates at the 0M08 level similarly to internal logic block 11 of . The circuits 20, 21, and 22 are connected to the output terminal 7A 22 for output conversion for the MO8-T'I'L level, which performs the same operation as the output buffer shown in FIG. It is supplied with a power supply voltage Vcc of volts and is properly grounded via terminal No. 31.

The input capazza 20 has a plurality of TTL-0MO8 level converters 201, 202...20n, each input is connected to the 1st terminal, 2nd terminal...19th terminal, and each output is connected to an internal logic block. 21 and is connected by an aluminum + cum wiring layer inside the circuit device IC.

Internal logic block 21 is 0MO8/NAND game) 21
1,212,213,214 further 0M08- No. gate 21('-1), 211 further 0M as necessary
O8 exclusive tin OR gate, 0MO8 transmission gate.

Includes 0MO8 inverter, etc.

The 0MO8-NAND gate 211 is, for example, as shown in FIG.
Channel M08 PET M,.

It is composed of a pure CM08 circuit including M4. Further, as another example of the 0MO8-NAND gate 211, as shown in FIG. 8, an NPN transistor Q4. Q! ,
It can also be constructed by a quasi-CM08 circuit that further includes resistor holes, ,R, and the output stage of such a quasi-CMOS circuit is composed of bipolar transistors Q, ,Q, so that the output drive capability is improved. , the dependence of the propagation delay time on the output load capacitance can be reduced.

Further, the 0MO8-NOR gate 211 includes, for example, a P-channel MO8FETM, ,M, and an N-channel MO8FETM, as shown in FIG.

It is composed of a pure CMOS circuit including M. Also, as another example of the 0MO8-NOR gate 21, the first
As shown in figure 0, NPN) transistor Q+ + Qh
It can also be configured by a quasi-CM08 circuit that further includes resistors R, , R, and the output stage of such a quasi-CMOS circuit is composed of bipolar transistors Q+ and QtK, so that the output driving capability is improved. propagation i4
The dependence of the elapsed time on the output load capacity can be reduced.

In the internal logic block 21, these 0M08, N
AND gates, 0MO8-NOR gates are connected in various forms aK according to the master slice method or semi-custom gate array method.

For example, as shown in Figure 11, two 0MO8 NAN
By combining D gates or by combining two 0MO8-NOR gates as shown in FIG. - Combining NOR gates
Gated R-8 controlled by clock signal C
It consists of 7 lips and 70 tubes.

In this way, in the master slice type or gate array type logic semiconductor integrated circuit device IC that meets customer needs, the level converter 201.2 of the input buffer 70 can be changed by changing only the wiring pattern.
02...20n and the inputs of various gates or inverters of the internal logic block 21 are connected in various ways, and similarly, the outputs of the type A gates or inverters of the internal logic block 21 and the output buffer 7 are connected in various ways. The inputs of the level converters 221, 222, . . . , 22m are connected in various ways.

The output buffer 22 has a plurality of 0MO8-TTI level converters 221, 222, .

Input buffer 200 level converter 201, 202...
The essential features of 20n are as follows.

(1) Input voltage hold voltage V1th of each level converter 201.202"10n)t'r 'I'
L Low vbell input voltage 0.8 volts and TTL,・
The level input voltage is set between 2.0 volts and 2.0 volts.

(2) The output capacitance C of each level converter 201, 202...20n in response to the input signal supplied to its input terminal
The output transistor that performs charging or discharging of s is constituted by a bipolar transistor.

Furthermore, an input buffer 200 and a level converter 201゜20
Preferred features of the preferred embodiment of 2...20fl are as follows.

(3) A Schottky barrier diode is connected between the base and collector of the bipolar output transistor Q, which discharges the output capacitance Cs in (2) above.

(4) Each level converter 201, 202, 201m
a second shutter-key barrier diode between the pace and the collector of the drive transistor Q, for driving the pace of the bipolar output transistor Q, with its output in response to an input signal applied to the input terminal of the drive transistor Q; is connected.

(5) The output transistor that performs charging of the output capacitance Cs of each level converter 201.202''lOn is also constituted by a bipolar transistor Q island.

(6) Drive transistor Q via a MOS with high input impedance and amplification effect.

The pace signal or collector signal of is transmitted to the pace of the charging bipolar output transistor Qs.

(7) A Schottky barrier diode DI for level shifting is connected between the input terminal of each level converter 201, 202, . . . 20n and the gate of the drive transistor Q.

(8) Each level converter 201.202...20. There is a distance P between the input terminal of n and the pace of the drive transistor Q.
NP emitter 7-lower transistor Q.

and PN junction diode D for level shift! are connected.

4 to 31 show various circuit diagrams of the input buffer 200 and the level converter 2010 according to embodiments of the present invention, all of which are implemented in accordance with (1) and (2) above.
It has the essential characteristics of Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

In the level converter 201 of FIG. 14, the input terminal I
N is connected to the cand of a level-shifting barrier diode D, whose 7th node is connected to the pace of the drive transistor Q. The head voltage Vr of this diode D is 0.35 volts to 0.4 volts.
The type of barrier metal and barrier area are determined so that the voltage is set to 1 volt. The forward voltage V of the switch barrier diode D of the level converter shown in FIGS. 15 to 31 is similarly set to 0.35 volt to 0.41 volt.

Furthermore, in the m14 diagram, the drive transistor Q and the discharge output transistor Q are connected to their key-shaped base #L.
As shown in the polar signal, a Schittke barrier diode D is connected between the pace and the collector. Clamped transistors with barrier diodes 117 thus have a very small storage time, as is well known. In the following example, a transistor with a key-shaped base electric signal is
This shows that it is such a clamped transistor. Note that the pace of the output transistor Q for discharging is connected to the ground potential point via a 5 kilohm resistor 0 for discharging the pace charge.

Further, in FIG. 14, a resistor R21 of 18 kilohms and a resistor R11 of 2 kilohms are connected in series between the power supply voltage Vcc and the anode of the Schottky barrier diode D. The common connection point of both resistors, , , R, is a P-channel MO8FET as a phase inverter.
Mp+. Its drain is connected to the pace of charging output transistor Q3.

Further, a diode D is connected to ensure that the transistor Q is turned off when the level converter 201 generates a low level output.

The output of the level converter 201 at the emitter of the charging output transistor Q is connected to the output capacitor Cs and the CMOS NAND gate 2 of the internal logic block 21.
11 inputs.

Also, bipolar transistors Q,,Q.

The area of each emitter Q is set to 100 μM to 144 μM, and it is also possible to set the area smaller than this. Furthermore, the ratio W/L of 8408 PET is 32/
The value is 3 to 64/3.

The inventor has confirmed that the embodiment shown in FIG. 914 having the above configuration has the following propagation delay time and its output capacitance dependence.

t tH also (when C5=QpF) -・1.6 n
@ect IILH (when C5=OpF)...
5.7nsecKHL II
IIjO,4n5ec/pFKLH=0.4 n5e
c/pF It can be seen that the propagation delay time 1 FIL r j PLH and the output capacitance dependence KHL * KLM described above are excellent compared with the characteristics of the input terminal 7a 10 in FIG.

Furthermore, the level converter 201 in FIG. 14 can obtain desired characteristics for the following reasons.

(1) The head voltage VF of the shield barrier diode D is set to 0.35 to 0.41 volts, and the base-emitter voltage vB of the transistor Q+ -Q-
lllVBl! is about 0.75 volts, so the voltage filter input to the level converter 2010, Vith, is set to 5 as shown below.

Vlth z−V y + VIIll +Vast
=1.09 to 1.15 volts (2) Output transistors Q, , Q for discharging or charging the output capacitance Cm of the level converter 201.

Since it is constituted by a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) Transistors Q, ,Q driven into the saturation region.

Since a switch barrier diode is connected between each base and each collector of the transistors, the accumulation time is reduced when both transistors Q, Q, switch from on to off. can do.

(4) When the potential at the common connection point of resistor 11 + '11 rises and the phase inversion MO8FET Mpto and the charging output transistor Q1 turn off, the MOSF
Since the input impedance of the gate of ET Mp, , is very high, the current flowing into the gate of Mpto from the common connection point is very small. Therefore, MO8FET
Compared to the case where the phase inverter is configured with a bipolar transistor instead of Mpto, the operating speed for switching the charging output transistor Qa from off to on is improved.

The level converter 201 in FIG. 15 differs from the one in FIG. 14 only in that another PN junction diode D is added, and the addition of this D4 further reduces the low level output voltage of the level converter. be able to.

Regarding the level converter 201 shown in FIG. 15, its propagation delay time and its output capacitance dependence were introduced by the inventor as follows.

t P)IL (However, when C5=OpF)"1.89
nsectset, u (when Cs-0pF)”6
．． 37nsecKHL…0
．． 4 n5ac/pFKLH...0.4 n5ec/
pF Further, the level converter 201 in FIG. 15 can also obtain desired characteristics for the same reason as in the case of FIG. 14.

The level converter 201 in FIG. 16 includes a drive transistor Q,
Only the collector connection method in FIG. 14 is different from that in FIG. 14, and the propagation delay time and output capacitance dependence of the level converter in FIG. 16 were confirmed as follows.

tpiu (however, when using C3 OpP')...1.8
1nsectpLn (However, when C5=OpF...5
．． 08naecKHL 1j
I0.4 n5ec/pFKLH low 0.4 n5ec
/pF Also, in the level converter 201 of FIG.
Desired characteristics can be obtained for the same reason as in the case of Figure 4.

Each level converter 201 in FIG. 17 is a MO8F for phase inversion.
ET Mp,. The only difference from the one in Fig. 815 is that another NPN transistor Q is connected between the drain of the charging output transistor Q and the base of the charging output transistor Q, and the propagation delay of the level converter shown in Fig. 17 is Time and its output capacity dependence were confirmed as follows.

t PHL (However, when C5==Qpp)...2.
01nsecLpLH (when C5w0pF) ・
・4.30 naec, 1Lo1o, 4nsec/p
F KLI (.=0.4 nsec/pF In the level converter 201 in FIG. The transistor Q is connected to the ground potential point via a 5 kilohm resistor RI0 for discharging the electric charge.

A 20 kilohm resistor R11 for collector current limitation is connected to the collector.

Power supply voltage Vcc and shuttling barrier diode D,
18 kilohm resistors R1 and 2 are connected between the anode and the anode.
A kilo-ohm resistor, t, is connected in series. Both resistances, 1.几9. The common connection point of is connected to the gate of a P-channel O8FET MP++ as a charging output transistor.

Further, the ratio W/L of this MP++ is 64/3.

The propagation delay time of the level converter 201 shown in FIG. 18 and its output capacitance dependence were clearly confirmed.

tpuL (when C5=OpFO)...1.9
n5ectpLH (when C5=OpF) -...
2,9 n5ecKILL
j-0,4n5ec/pFKLH...1.3nsec
/pF Furthermore, the level converter 201 in FIG. 18 can obtain desired characteristics for the following reasons.

(1) As in the case of FIG. 14, the level converter 2010
The input voltage 1 hold voltage v+th can be set between 1.09 and 1.15 volts.

(2) Since the output transistor Q that discharges the output capacitance CS of the level converter 201 is composed of a bipolar transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacitance dependence can be reduced8 (3) As in the case of Fig. 14, the transistor Q+
+Q1. The accumulation time can be reduced.

In the level converter 201 of FIG. 19, transistors QI, Q! is a club/button transistor with a barrier diode, and the base of the discharge output transistor Q is a 5 kilohm resistor for discharging the base charge. is connected to the ground potential point via. A load resistance R of 8 kilohms is placed on the collector of the transistor Q.
7, is connected, and a 20 kilohm resistor 4 is connected between the power supply voltage Vcc and the anode of the Schittke barrier diode D. drive transistor Q,
The collector signal of 1 is connected to the gate of an N-channel MO8FET Mnu as a charging output transistor, and the ratio W/L of this MnH is set to 64/3.

The propagation delay time of the level converter 201 shown in FIG. 19 and its output capacitance dependence were confirmed as follows.

tpsu, (when C5=QpF)...1.1 n
aectpLH (when C5=OpF") "4.
8nsecKHL...0.3
nsec/pFKt, +i
1 fight #2.0nsec/p? Furthermore, the level converter 201 in FIG. 19 can obtain desired characteristics for the same reason as in the case of FIG. 18.

In the level converter 201 of FIG. 20, the transistors Q, , Q, are likewise club/button transistors, and the base of the discharging output transistor Q1 has a 5 kilohm resistor for discharging the base charge. is connected to the ground potential point via. 1 at the collector of transistor Q.
A load resistance R0° of 0 kilohm is connected, and the power supply voltage V
A 20 kilohm resistor 4 is connected between cc and the anode of the Schottky barrier diode D. The collector signal of the drive transistor Q is an N-channel MOI FE jr as an amplification transistor.
It is applied to the gate of MnIs, the Mn+s(') ratio W/L is set to 32/3, and a 20 kilohm load resistor R8 is connected to the drain of Mn+s. M
The drain signal of n+s is connected to the amplification transistor and 1. O8k”ET between all P channels is applied to the gate of Mp+s, the ratio W/L of Mp, , is set to 64/3, and M
3. A load resistor of 10 kilohms is installed at the drain of p, , and a resistor for discharging the base charge of the bipolar output transistor Q for charging. is connected.

The propagation delay time of the level converter 201 shown in FIG. 20 and its output capacitance dependence were confirmed as follows.

t PHL (However, when C5=OpF
ectpLn (However, when C5=OpF, 7.5 n
aecKl(L = 0.4
naec/pFKL)I ・
...0.4 naec/pF Furthermore, the level converter 201 in FIG. 20 can obtain desired characteristics for the following reason.

(1) As in the case of FIG. 14, the level converter 2010
Input voltage and hold voltage Vith from 1.09 to 1
．． It can be set to 15 volts.

(2) As in the case of FIG. 14, the switching operation speed or propagation delay time during charging and discharging of the output capacitor jlCm and its dependence on the output capacitance can be reduced.

(3) As in the case of Fig. 14, transistor Qt+Q
, the accumulation time can be reduced.

(4) When the collector potential of the drive transistor Q rises and the charging output transistor Q switches from off to on, the amplifying MO8FETs Mnts and Mp amplify the change in the collector potential of Q. Just transmit it to the base of Q, Hanak, M2S FET
Due to the extremely large human power impedance of Mnts, Q! output transistor Q, to prohibit direct inflow of large base current from the collector of Q to the base of Q.

switching speed can be improved.

In the level converter 201 of FIG. 21, Q.

Q, is a clamped transistor, D, is a barrier diode for level shifting, and the resistors are set to 5 kOhm, 20 kohm, and 8 kohm, respectively. It's been done. The collector signal of the drive transistor Q is 0MO as a voltage multiplier.
P-channel M08 FETs forming 8 inverters
Mp+a and N channel MOB FET Mn
+4 is applied to both gates, pfjMo 8 F E
The drain signal of T M p141 M nu is a P channel M08 F as a charging output transistor.
Applied to the gate of ET Mp++. Mp, 4. M
The local W/L for n+4+M p+t is 24/3.
It is set to 22/3.64/3.

The propagation delay time of the level converter 201 shown in FIG. 21 and its output capacitance dependence were confirmed as follows.

tpuL (when C5=OpF)...2.02n
sectphu (when Cs = Op F")"
4.27naecKHL --
・0.42nsec/pFKLH...1.32nsec
c/pF Furthermore, each level converter 201 in FIG. 21 can obtain desired characteristics for the following reasons.

(1) As in the case of FIG. 14, the input threshold and hold voltage Vith of the level converter 201 can be set to 1.09 to 1.15 volts Ic.

(2) Since the output transistor Q1 that discharges the output capacitance C3 of the level converter 201 is composed of a bipolar 2 transistor with small output resistance, the switching operation speed or propagation delay time when discharging the output capacitance and its output Capacity dependence can be reduced.

(3) As in the case of Fig. 14, transistor Q++Q
, the accumulation time can be reduced.

In the level converter 201 of FIG. 22):,Q.

is a clamped transistor as an output transistor for discharging, and the input terminal IN is connected to a barrier diode D for level shifting.

The cathode of is connected. Anode of D and Q.

A PN junction diode D for level shifting is connected between the base of the power supply voltage Vcc and DI.

A resistor 1 (+16, R'to) with a resistance value equal to 10 kilohms is connected in series between both anodes of D, and a base charge is connected between the input terminal IN and the base of Q. Discharge barrier diode D,
is connected.

Resistance 几, , R,. The common connection point is a P-channel MO8FETM p, , as a charging output transistor.
The ratio W/L of M p, , is 64/3.
is set to .

The propagation delay time of the level converter shown in FIG. 22 and its output capacitance dependence were confirmed as follows.

t PHL (when C5=QpFO) -2,44n
sectpt, u (when Ca=OpF) −・−
5,41n5ecKHL...
1.0 nsec/pFKLH-5,3 nsec/pF Furthermore, the level converter 201 in FIG. 22 can obtain desired characteristics for the following reason.

(1) The forward voltage VF of the barrier diode D1 is set to 0.35 to 0741 volts, and PN
The forward voltage V, of the junction diode D, is 0.75 volts, and the base-emitter voltage VBg of the transistor Q,
Since l is 0.75 volts, the threshold voltage input to the level converter 2010 for turning on the transistor Q is set as follows.

Vith=-Vpl+Lrs+Vaax=1.09 to 1.15 volts (2) Since the output transistor Q, which discharges the output capacitance C3, is composed of a bipolar transistor with small output resistance, the switching time or propagation delay time and Its dependence on output capacitance can be reduced.

(3) Since the transistor Q1 is a double-amplified transistor, its storage time can be reduced.

In the level converter 201 of FIG. 23, Q++Q,
is a clamped transistor, D is a shuttling barrier diode for level shifting, and is a resistor. ,
R14, R, are set to 5 kilohms, 20 kilohms, and 8 kilohms, respectively. The collector signal of the drive transistor Q is a P-channel MO8FET Mp that constitutes a CMOS inverter as a voltage amplifier.
r4 and N-channel, xl (applied to both gates of C8FET Mnti, and the drain outputs of both MO8FETs are applied to the gate of P-channel MO8FET Mp, for switching. M R14t M n+4# M
pII+ local W/L is 24/3.32/3.
It is set to 64/3.

The drain output of MOSFETMp+s is applied to the base of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter shown in FIG. 23 and its output capacitance dependence were examined as follows.

t PHL (when C5=QpFO) -5,07n
5ectpL) + (when C5=OpFO) -5,Q
9 n5ecKHL =0
．． 4 n5ec/pFKLHl-0, 4n5ec/pF Furthermore, the level converter 201 in FIG. 23 can obtain desired characteristics for the following reason.

(]) As in the case of Fig. 14, the level converter 2010
Set the input threshold voltage between 1.09 and 1.
．． It can be set to 15 volts.

(2) As in the case of Fig. 14, the switching operation speed or propagation during charging and discharging with an output capacity of 1 kCs)! ! The elongated time and its dependence on output capacity can be reduced.

(3) As in the case of Fig. 14, transistor Q++Q
, the accumulation time can be reduced.

(When the collector potential of the 41 drive transistor Q rises and the charging output 2/transistor Q3 switches from off to on, the CMOS inverter Mp, ,
M n+4 not only amplifies the collector potential change of Q and transmits it to the base of Q, but also MOS F' E
To improve the switching speed of the output transistor Q, since the gate input impedance of T M l)+4 and M n+4 is extremely large, which prohibits a large base current from flowing directly from the collector of Q to the base of Q. Can be done.

The level converter 201 of the 24th factor is a 10 kilohm resistor R1 for discharging the base charge of the charging output transistor Q.
The only difference from the level converter 201 in FIG. 23 is that 6 is connected between the base and emitter of Q, and the propagation delay time and output capacitance dependence of the level converter 201 in FIG. 24 are as follows. It was confirmed as follows.

tpHh (when C5=QpF)...-6,2ns
ectpLn (when C5=QpFO) -4,9n
aecKHL Ijj
o, 4nsec/pFKLH...0.4nsec/p
F Furthermore, the level converter 201 in FIG. 24 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 shown in Figure 8g25, the resistance R3 of the base charge discharging circuit of the discharging output transistor Q is 1.5.
kohm resistor R11+, 3 kohm resistor R1
, , is switched by an active pull-down circuit constituted by a clamped transistor Q6, and a shut-off barrier diode for discharging the pace charge of the charging transistor Q is connected to the base of Q and Q, The only difference from the one shown in FIG. 24 is that it is connected to the collector of FIG.

tPHL (Cs=OpF f)R)...6.
6 n5ectpLu (when C5=OpF) ・
・・5.3 n5ecKHL
…0.4 n5ac/pFKLH…0.4 n5e
c/pF Furthermore, the level converter 201 in FIG. 25 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter 201 in FIG. 26 is the active pull-down circuit R, , , , in FIG. 25. The only difference from the one in Fig. 24 is that the discharge resistor R1° is replaced by the same active pull-down circuit as +Qa, and the propagation delay time and its output capacitance dependence in Fig. 26 are as follows. confirmed.

t FIL (when C5=OpF) -8,62n
sectPLH (when C5=OpF) ---4,
7nsecKHL…0.4
n5ec/pFKLH...0.4 n5ec/pF Furthermore, the level converter 201 in FIG. 26 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 of FIG.
2.Transistor Q1. Q! , Q are a discharge output transistor and a drive transistor, respectively.

The charging capacity is Cado 2/Dista, and D, D, and D are the barrier diodes and barrier diodes for level shifting, respectively.
It is an N-junction diode, “14 +”16 *R□
, R□ are 20 kilohms, 8 kilohms, and 10 kilohms, respectively.
kilo ohm, 10 kilo ohm resistance, M pis
, M n+6 are each P channel M08 F
ET, N channel MO8FE'r, both "pi"
The ratio W/L of s + M n 16 is both set to a value equal to 32/3.

In particular, M pH@ , M n,11 , Q, ,
The QB is characterized in that it is a quasi-CMOS inverter type amplifier with low output resistance.

The propagation delay time of the level converter 201 shown in FIG. 27 and its output capacitance dependence were confirmed as follows.

tp+u, (when C5=OpF)"5.48ns
ectpx, n (when C5=OpF) --- 5.
23nsecKHL...
・0.37nsec/pFKLH...0.38nsec
c/pF Furthermore, the level converter 201 in FIG. 27 can obtain desired characteristics for the following reason.

(1) The forward voltage vF of the barrier diode D is 0.35 to 0.41 volts, and the transistor pQ
The pace-emitter voltage Vagz of t is 0.75 volts, and the forward voltage VF8 of the PN junction diode D is 0.75 volts.
Since it is set to 75 volts, the threshold voltage Vlth input to the level converter 2010 regarding the on/off operation of the transistor Qt is set as follows.

Vith = Vrt + Vazz + Vra = 1.09 to 1.15 volts (2) The output transistors Q, Q, which discharge or charge the output capacitance Cs, are composed of bipolar transistors with small output resistance, so the switching operation speed is low. Alternatively, the propagation delay time and its output capacitance dependence can be reduced.

(3) Since Q+lQt is a clamped transistor, its accumulation time can be reduced.

(4) The collector potential change of the ffi dynamic transistor Qt' is the quasi-CMOS inverter MP+s + Mn+e p
Since it is amplified by Qm*Q+ and transmitted to the output, the output waveform change speed can be improved.

In the level converter 201 of FIG. 28, the collector load of the transistor Qt is a resistance. rather than PN junction diodes D, , D,. It differs from the one shown in FIG. 27 only in that it is constituted by a resistor R2 of 5 kilohms, and the propagation delay time of the level converter shown in FIG.

tpnL (when C5=OpF) --- 6.66n
sectpt, n (when C5==opF')...
4.16nsecKHL=
0.42nsec/pF'KLH...0.37nsec/
pF Furthermore, the level converter 201 in FIG. 28 can obtain desired characteristics for the same reason as in the case of FIG. 27.

The level converter 201 in FIG. 29 is connected with a PN junction diode D for reliably turning off the transistor Qs, and a switch barrier diode D? for discharging the base charge of the transistor Q. The only difference from the level converter 201 shown in FIG. 23 is that the level converter 201 shown in FIG.

t PHL (However, when C5=OpF)...-1,7
21 sec pbu (when C5=OpF)"5.
44nsecKHL...0
．． 32nsec/pFKLH=-0,29nsec/
pF Furthermore, the level converter 201 in FIG. 29 can obtain desired characteristics for the same reason as in the case of FIG. 23.

The level converter of FIG. 30 has a resistor RI in FIG.
4 is replaced by a resistor R1 of 25 kilohms, and a resistor R1 of 5 kilohms, and a resistor R+s7! l' ratio W
P channel M08 F with /L set to 24/3
ET Mpl? Only the points replaced by
This is different from the one in Figure 9. Since Mp+t acts as an active load element of Q, the amplifier Q* + M pI?
The voltage gain of is extremely large.

Regarding FIG. 30 as well, the propagation delay time and its dependence on output capacitance were confirmed as follows.

t PHL (However, when C5=OpFO)...2.2
nsectpLu (however, when C5=OpF...5.
2 n5ecKHL...0
．． 4 n5ec/pFKLH, -=0.3 n5ec/
pF Furthermore, the level converter 201 in FIG. 30 can obtain desired characteristics for the same reason as in the case of FIG. 23.

In the level converter 201 shown in FIG. 31, transistors Q, , Q, are clamped transistors, Qs is a charging output transistor, Q4 is a PNP emitter/7-hole transistor, and D is a switch kit for level shifting.・
barrier diode.

D is a PN junction diode for level shifting.

is a PN junction diode to ensure that the transistor Q is turned off, and Da is a Shitakki barrier diode to dampen negative noise at the input terminal. Resistors R8゜, R, , R, are 5 kilohms and 8, respectively.
-+Rohm, set to 20KOhm. The collector signal of the drive transistor Q is a P-channel MO8FE that constitutes a CMOS inverter as a voltage amplifier.
T Mp+4 and Nf Yanel M 08 F E '
rM n l applied to both gates of 4, both MO8FE
The drain output of T is P channel MOS for switch.
The gate voltage of FET Mp+s is applied. The local W/Ls of M pI4 and M nu + M pus were set at 24/3.32/3.64/3, respectively. The drain output of the rvios FET Mp+s is applied to the pace of a bipolar transistor Q, which serves as a charging output transistor.

The propagation delay time of the level converter 201 in FIG. 31 and its output capacitance dependence are as follows: 6111F#M
It was done.

tpoL (when C5=OpF)...1.94
~3.84 n5ectpLo (when C5=OpF)...4.64~5.44 n5ecKHL...
・0.38 n5ec/pFKLH-0,30nsec
/pF Furthermore, the level converter 201 shown in FIG. 31 can obtain desired characteristics for the following reasons.

(1) The forward voltage VFI of the blind barrier diode D is 0.35 to 0.41 volts, the forward voltage vrz of the PN junction diode D is about 0.75 volts, and the transistors QI, Qt, Q40 base Between emitters 1
1E pressure V BEI I VBE2 * Vag4ha approx. 0
．． Since the voltage is 75 volts, the input threshold voltage Vith at which transistors Q, , Q, turn on is as follows.

V ith =-VBxa + Vpz + VBE2
+ VBEI = 1.5 volts (2) The output transistors Q, , Q, which discharge or charge the output capacitance Cs, are composed of bipolar transistors with small output resistance, so the switching operation speed or propagation delay time and Its dependence on output capacitance can be reduced.

(3) Since 'J+ and Qt are 2/but transistors, their storage time can be reduced.

(4) Drive transistor Q! When the collector potential of the CMOS inverter M rises and the charging bipolar output transistor Qa switches from off to on, the CMOS inverter M
p! 4 + Mrt14 not only amplifies the collector potential change of Q and transmits it to the pace of Q, but also MO8
F E T M p149M The extremely large gate input impedance of n+i prohibits a large kina pace current from flowing directly from the collector of Q to the pace of Q, and also increases the
Since the base current is supplied at the pace of , the switching speed of the output transistor Q can be improved. Figure 3 includes Figures 14, 19, 22, and 33.
The output capacitance dependence of the propagation delay time of the level converter in the figure is shown by the dashed line, and it can be seen that the output capacitance dependence of either the propagation delay time in Figs. 1 or 2 has been improved. It can be understood.

Next, a plurality of 0MO8-T of the output buffer 22 in FIG.
The TL level converters 221, 222" and 22m will be explained. These level converters 221, 222...2
The essential percentage characteristics of 2m are as follows.

Margin below (1) Each level converter 221.222...
22m input threshold voltage VitbitCM
It is established between U8°-level output voltage 0.6 volts and high level output voltage 4.4 volts.

(2) In response to the input signal supplied to its input terminal (7) each level converter 221. has been done.

Additionally, the output buffer 220 level conversion 0221.22
The preferred features of the preferred embodiment of 2...22m are as follows.

(3) Discharge output transistor Q. Drive the pace of. A high input impedance circuit is connected between the pace of drive transistor QII and the output of internal bm block 21.

(4) The high-input signal bias circuit M in (3) above has a function of logically processing a plurality of output signals of the internal logic block 21. (5) The discharge output transistor Q+o and the drive transistor Q+t are It consists of a clamped transistor with a transparent barrier diode.

(6) The output transistor Q11 that charges the output load capacitor 1icx is composed of a bipolar transistor.

(7) It has a function of controlling the output terminal (JLIT) in a floating manner by simultaneously turning off the discharging output transistor Q+O and the charging output transistor Q'H in response to the 1i41 times signal.

(8) The level converters 5221 and 222-"22m have an open collector output format.

32 to 34 and 36 show various circuit examples of the level converter 221 of the output buffer 20 according to embodiments of the present invention, and all of these level converters are shown in (1) above.
) and (2). Furthermore, these level converters have at least one of the preferred features (3) to (8) above.

%QI in level converter 221 of FIG.

is a refined output transistor, QutiQ+, which discharges to an output load capacity of 11 Cx'. Qll is the output transistor for charging the output load capacitance iCx, and Q□ is the collector signal change of QCs.
+ Current amplification transistor for transmitting to the base of t, approximately so e Rais Q10 is the total of Qio, -
Active pull-down circuit for discharging SMI charges.

Q4 is a multi-emitter transistor, R and t are Q
1. The collector resistor R83 is a resistor D for discharging the base charge of QCs. is a Schottky barrier diode for discharging the base charge of Qll, a resistor for limiting the collector current of IriQ+t*Qts, and a base resistor of R□ViQ + a.

Furthermore, P channel MO8F of internal logic block 21
ET M,,M, and N-channel MUSFE'l'M,
, M4 and the output of the 0MO8 NAND gate 211 is the multi-emitter transistor Q r
the output of the 0MO8-NAND gate 212 is applied to the second emitter of QCs;
The output of the 0MO8-NAND gate 213 is applied to the third emitter of Qsa. Therefore, the level converter 221 not only has a level conversion function, but also has a three-manpower N
It has a logic processing function as an AND gate.

Furthermore, the level converter 221 in FIG. 32 can have desired characteristics for the following reasons.

(1) Transistor Q1. The base of Emi, the pressure V
Bg15 is about 0.75 volts, the voltage V8C between the base and collector of Q4 is about 0.55 volts, transistor Q,
. , Qll base-emitter voltage VBglOVBE
II is approximately 0.75 volts, respectively, and the input threshold and hold voltage of the level converter 221 are set as follows.

Vi th=-Vagts +Vncls +V8E1
1 +VBIC10=-0,75+0.55+0.75
+0.75=1.3 volts (2) Output transistor Q, which discharges or charges the output load capacitance aX of the level converter 221. .

QCs can reduce the switching operation speed or propagation delay time and their dependence on output capacitance compared to the QCs which are composed of bipolar transistors with small output resistance.

(3) Transistor Q+o * Qu + Qtm +
Since Q10e QCs is a clamped transistor, its storage time can be reduced.

(4) Multi-emitter transistor Q1. Since it has a logic processing function, the degree of freedom in designing the master slice type or gate array type logic semiconductor integrated circuit device 1c is improved.

However, it takes! In the level converter 221 shown in Fig. 32, when the output of the CMUS-NAND gate 211 is at a low level, the base of the resistance
0MO8-N from power supply voltage Vcc via emitter junction
Since a large current of 0.4 milliampere always flows into the output of the AND gate 211, the N-channel MO8FBTM, , M, (D
The on-resistance RO is as large as the ratio W/Ll 100/3.
M must be a small value. This is not only to prevent a decrease in the integration density of integrated circuit devices IC, but also to
The inventor's studies have revealed that the switching speed of the 0MO8 NAND gate 211 decreases because the gate capacitance of CJ8FE'l['M,,M, also increases.

Figure Ng33 shows a circuit diagram of a level converter 221 that has been implemented to solve the above-mentioned problem, and the multi-emitter transistor Q4 of Figure 32 is connected by a high input impedance path as described below. has been replaced.

That is, in FIG. 33, such a crystal input impedance circuit has PNP input input transistors 3Q, .
N emitter follower transistor Q16*shi, barrier diode L),,,L),! .

Resistance hole. , Ro, 几, and s'lc.

Further, the level converter 221 includes a PNP) transistor Q,
. , NPN transistor Q16. PN junction diode D, 4. It includes a ninth control circuit constituted by a resistor R1VC and controlling the output terminal OU 'l' to a floating state.

PNP transistor Q of this control circuit. The base of
Internal 'fm buried block 21 channel M (JSl
i”ETM, and N-channel MO8FE'l'M.

CM (J8-NANI) gate 2 configured by and K
It is driven by the No. 11 enable signal ENVc.

An inverted enable signal EN is applied to the input of the gate 211 (0MO8-NANI).

Furthermore, this control circuit has changed its level! 2! 221, the input transistor Q1. and a Schottky barrier diode DI3 are added.

Therefore, when the enable signal EN goes low level, the transistor Q+o*Q,+t of the level converter 221
.

Q+! +QCs are turned off at the same time, so their output terminals OUT and i are in a floating state.

On the other hand, when the enable signal EN becomes high level, the level converter 221 has a two-manual NAND gate and a logic processing function as well, so that the degree of freedom in designing the integrated circuit device IC is increased.

In addition, one block barrier diode DIl #D
I! +Forward same voltage of DI3 vFil + ■FIZ *
v713 is 0.35 to 0.41 volts, PNP
Input transistor Ql? + QCs + Base-emitter voltage of QCs Vszlr r VIIIgxs
+ VBEIII tri approx. 0.75
N PN transistor Q+o * Q++ r QCs
Base-emitter voltage Vagxo * V@go
p Vsgtat'! Since it is approximately 0.75 M rut,
For example, PNP transistor Ql? 0MO8-NANI) applied to the base of the transistor Q, with respect to the output voltage of the gate 211. ,Q.

The input threshold voltage at which V is turned on is as follows.

Vith=-VBEI? +Vagta +VBE1
1 +Vagl.

= 1.5 volts and an output transistor Q, which performs discharging or charging of the output load ""8 amount Cx. , Q, and t are constructed of bipolar transistors with small output resistance, the switching speed can be reduced, and the propagation delay time and its dependence on output capacitance can be reduced. Next, transistor Q. +'Qo*Qss + Q10 +
Since it is a Q+ati clamped transistor, its delay time can be reduced.

However, in the level converter 221 of FIG. 33 as well, when the output of the %CMOS NAND gate 211 is at a low level, the PNP input transistor Ql? The inventor's studies have revealed that the above-mentioned problem cannot be completely solved because a non-negligible current flows from the base of the gate 211 into the output of the gate 211.

FIG. 34 shows the level converter 211 finally solved to almost completely solve such problems, and is constructed by the multi-emitter transistor Q + s Fi of FIG. The second one is replaced by a high input impedance circuit.

In the m34 diagram, such a high input impedance circuit is an N-channel MO8FETM.

M,,,M,,,PN junction diode D1. It is composed of Nyoto. M, 1. MB, M, 3's drain
The source paths are connected in parallel, and each gate is a CMOS-NAND gate 211, 212°2 of the internal logic block 21.
A PN junction diode DI4 is connected in series to these drain-source paths.

1 bill resistance R36, R11e 几1! +RII+'
LH*Rrms are set to 2 kilo ohms, 4 kilo ohms, 10 kilo ohms, 4 kilo ohms, 50 to 75 ohms, and 16 kilo ohms, respectively. transistor Q
,. .

The emitter areas of Qu + Qts + Q10 are 672 μrrf, 132 μrrf, and 3, respectively.
63 μm', 187. urn”.

242　μrn”lc role addition tail.

Furthermore, in order to further improve the logic processing function of the level converter 221, the drive transistor Ql
A second drive transistor Q having the same emitter performance as l
, o are connected in parallel with Qll, and KN channel MO8FETM, , M
, ,M, ,PN junction diode Ll, ,resistance R1
, constitutes a second high input impedance circuit, and this level converter 221 has a logic processing function as a six-person complex gate circuit.

Further, this level converter 221 is supplied with a low level enable signal EN from the internal logic block 21. :, a ninth control circuit for controlling the output terminal 0υTl to the 70-ting state is similarly added. This control circuit consists of an N-channel M08FET Mlte,
Transistor Q□.

Qts + Qts *Resistance R, o, R4,, 几41
* R41e Shirotki barrier diode D,・
e DI? It is composed of e D18 *D,, Ic.

Furthermore, in the level converter 221 in diagram R34, 6
Set the input threshold 1 hold voltage at each gate of the MO8FETM, . The ninth setting on the bolt, Mo...M,. The ratio W/L is set as follows. Furthermore, at this time, Mlm...M3
．． The threshold voltage VTH of the PN junction DA and the diode DI4 is set to 0.75 volts, and the forward voltage VF14 of the PN junction diode DI4 is set to 0.75 volts.
The channel conductance β of I. Hsoxlo-
'It is set to [1/ohm].

When only MO8FIETM11 is on, its gate voltage VX, gate-source voltage ■G8#
Drain current IDe, drain voltage Vy, etc. are calculated. It is assumed that M is biased in the saturated region at this time.

Vx=Vos+VF14
...(1) vy"'vcc-as'I From equations (1) and (2), ...(3) Vy=Vagll+Vagt.

From equations (3) and (5), ...(5) From equations (4) and (6), L Rss In (VX-V
F14-VTH)”...(7) Vcc is 5 volts + vflE11 and Vl)EIO are 0
．． 75 volts, R8, 16 kohm, β0 60
X 10-” [1/Ohmco, VX is 2.5 volts*
By the way, if we put the condition that VF14 is 0.75 volts)' + VTR is 0.75 volts into the above (7) 2, then as Vx increases, Vy decreases, and transistor Q+o*Qll turns off. VX can be considered as the input voltage.

Drain voltage V at which transistor Q1゜, Q, turns off
Y is determined as follows.

L 16X10" 60 (25-
0,75-0,75)"1 fold=-XIO"=7.29-- Thus, Ml,...M2. The ratio W/L is 22
/3, the input threshold voltage of level converter 221 can be set to 2.5 volts.

In the embodiment of FIG. 34 having the above configuration, the following propagation, ! The present inventor has confirmed that there is a dependence on time and its output.

trHb (when C5==OpF) = 8.8
nsec@pxu (when p and C5==pFO) =-
...7.8 n5ecKHL =
0; 11 n5ee/pFK LH-=・0;
01 n5ec/p F In FIG. 5, the output load capacitance dependence of the propagation delay time of the level converter of the embodiment shown in FIG. It can be seen that the output capacitance dependence KHLKLH of each of , 1PLH has been improved.

With the neck hole, the level converter 221Fi shown in FIG. 34 can obtain the desired characteristics for the following reasons.

(1) As mentioned above, the transistor Q. +(J+
+ pace emitter voltage vaglokei VBIIIK
Regarding 1 power supply voltage Vcc + resistance it, MLJ8FE'
Channel conductance β of lゝM, 1−·MB.

and threshold voltage ■ Corresponding to forward voltage VF14 of THe diode D14, Te, Mo 8 F E 'I'
By setting M,, ・M,, O ratio, and W/L,
Input threshold and hold voltage of level converter 221 to 0
．． 2.5 pol) K can be set between 6 volts and 4.4 volts.

(2) Discharging and charging the output load capacitance Cx 1! Since the output transistor Q+otQ++ that performs this is formed of a bipolar transistor with a small output resistance, the switching operation speed or propagation delay time and its dependence on output capacitance can be reduced.

(3) [The distance between the base of the dynamic transistor QIl and the output of the internal logic block 21 is M (J8FETM, 1
Since a high input impedance circuit with a , 0MO8-NANIJ gate 211's N-channel M08FET ratio W/L can be prevented from increasing significantly.

(4) MOSFE'rM of high input impedance circuit,
,.

Since M, .

(5) Two drive transistors Q11 + Q*. Also A
In order to execute the ND logic, the M processing function of the level converter 221 is also included.

(6) Transistor Q+o + (J+s + Qu
+ Q10 * Q*.

Since it is a clamped transistor, its storage time can be reduced.

(7) By setting the enable signal EN to low level, the output transistor Q+oeQ of the p-level converter 221
s and t are turned off at the same time, and the output terminal OUT becomes 70-
This output terminal OLl'lr enters the take state.

When running in parallel with the output terminal of another logic circuit that does not cause fire or water, the signal level of this output terminal OUT should be set to 4.
It can be made unrelated to the output of mm's block 1.

FIG. 36 shows a level converter 22 according to another embodiment of the invention.
1 is shown, and its output terminal au'r.

is commonly connected to the output terminal of another TTL level logic semiconductor integrated circuit device Ie/ of open collector output type,
This common connection point is connected to the 5 volt supply voltage Vcc through a 2 kilohm load resistor R1.0.

The open collector output type T '1' L level circuit device IC' is not particularly driven, but it is equipped with a switching barrier diode DI + Dt * ps, a multi-channel
Emitter transistor Q401 Clamped transistor Q4s to Q44. Resistance R4゜～㇠, 4. The pI is formed by the PN junction diode D4. Shi, rudder,
The collector of the output transistor Q4m is connected as an open collector output to the output terminal No. 43, while inside the circuit device IC/ there is no connection between the voltage Vcc and the collector of the output transistor Q4m. Not connected to.

In the level converter 221 of FIG. 36, one circuit device I is also used.
Any circuit element inside the voltage Vcc
The level converter 221 is formed exactly the same as the level converter 221 shown in FIG. 34, except that it is not connected between the collector and the collector of the output transistor Q1.

Thus, (b) the output terminal of the device 11C and the circuit device I
The output terminal of C' is connected in the form of a so-called wired OB circuit. Furthermore, by setting the enable signal EN to a low level, the output transistor Q+o of the level switching device 221 is forcibly turned off, and the output terminal OU
The level of T can be made independent of the output of internal logic block 21.

FIG. 37 shows a logical half-four rest collection M (
b) The layout of each circuit block on the surface of the semiconductor chip of the device IC is shown.

Central portion Cf1L of semiconductor chip 300? fllll. An internal logic block 21 composed of a 0M08 circuit (pure CMOS circuit or quasi-CM08 circuit) K is wired in the area surrounded by
ilts (t area surrounded by )K includes multiple input level converters (indicated by triangles with fR?s inside) shown in figure $31 and #! A plurality of output level converters (indicated by triangles with white interior) in FIG. The left side of the next area K (the area surrounded by the broken line !4) has a plurality of input level converters shown in FIG. There is.

Upper part! Above 1 are the number of input bonding pads (indicated by thick solid rectangles) corresponding to the number of input level converters, and the number of output bonding pads (indicated by thin solid lines) corresponding to the number of output level converters. ) are arranged, the input section of each input level converter faces each input bonding pad, and the output section of each input level converter is located inside the terminal. The input section of each output level converter faces the internal logic block 21, and the output section of the output level converter faces each output bonding butt.

On the right side [, multiple manual bonding pads and multiple output bonding pads on the right, bottom side! , multiple input pads and multiple output pads under the left side! , the plurality of manual bonding pads and the plurality of output bonding pads on the left side are the upper side sl,
are arranged in the same way as in .

Right side, bottom side 1sp The direction of the input/output part of the input level converter and the direction of the input/output part of the output level converter on the left side s14 are the top side sl, respectively.

The same is true for .

[The tth power supply bonding pad 31j that supplies the source voltage Vcc is placed on at least one of the four etched portions of the semiconductor chip 300, and the grounding bonding pad 31t for connecting to the ground potential point: l The above At least one of the four erotic parts/! c! It is placed.

The semiconductor chip 30 having the layout shown in FIG.
The back surface of 0 is physically and electrically closely connected to the surface of the tab lead LT of the metal lead frame L shown in FIG. 38.

In the lead frame LF shown in FIG. 38, this lead frame L has lead portions LI-7-L16. Waku part Lo.

A hatched portion LD is provided. However, in reality, the same applies to the parts corresponding to the lower right, lower left, and upper left of the semiconductor chip, so the lead frame L
F is the part LOI defined by the dam part with diagonal lfM
Lead part, ~L64. This is a thin metal plate having a structure in which tab leads LT are connected to each other.

After the back surface of the semiconductor chip 300 is connected to the front surface of the tab lead LT, wiring of bonding wires (for example, gold wire or aluminum wire) as described below is performed.

Commercially available wire bonding device el? The power supply bonding pad 30 and the lead portion L14 are electrically connected by the wires 1 and 14 to be used, and then the wires 1. The input pad and lead part are connected by the input pad, and the wire is connected by the output bar.

The wire Ia connects the input pad to the lead portion, and the wire J* connects the output pad to the lead portion 16.

The p input pad and lead part are connected to wire 1.
t electrically connects the grounding pad and tab lead LT.

The lead frame L after the above-mentioned wire arrangement is completed,
The semiconductor chip 300 and the semiconductor chip 300 are delivered to a mold for resin sealing, and liquid resin is injected into the inside of the tom portion LD of the lead frame L. Dam section.

prevents resin from flowing out.

After the resin has solidified, the lead frame L, the semiconductor chip 300, and the resin, which have an integrated structure, are taken out of the mold, and each lead is removed by removing the dam part LD using a 7less machine. The leads L and L114 can be electrically isolated from each other. Each lead L and L64 protruding to the outside of the anabolic resin can be cut downward as necessary, as shown in the completed diagram in Figure 39. As shown, a logic semiconductor integrated circuit device IC sealed with resin 301 is completed. As shown in the same example, no special radiation fins are provided for actively dissipating the heat generated by the three semiconductor chips of the circuit device IC#'i to the outside of the sealing structure.

If such a radiation fin is installed, the circuit device 1c
costs increase undesirably.

In addition to the above-mentioned resin encapsulation method, there are also ceramic encapsulation methods and methods using a metal case as a method for encapsulating a semiconductor chip, but from the viewpoint of the cost of the circuit FITIC, The sealing method is the most advantageous.

In the logic semiconductor iA product circuit device IC according to the embodiment using the drawings of FIGS. 37 to 39, input level converters 201, 202, . . .
...The total number of 20n is 18 to 50. Internal logic block 21
CMOS gate 211゜212...2
11! The total number of is 200-1530. Output level converter 221゜222...2 as output buffer 30
Despite the fact that the number of 2 m is 18 to 50 and the semiconductor chip 300 is a large-scale semiconductor integrated circuit device, the V-time MI device Ic was able to have a structure without heat dissipation fins for the following reason. .

In other words, the power consumption per gate of each 0M08 gate 211, 212, . The total power consumption is extremely low at 7.8 to 59.67 milliwatts. Input level converters 201, 202, . . . 2 also as input buffers 20 according to the embodiment of FIG.
Since On contains many bipolar transistors, the power consumption per each conversion is as large as 2.6ξW, and the total power consumption #Pi of the input buffer 20 with 18 to 50 converters is 46.8 to 130 milliwatts. It's big.

Since each output level converter 221, 222, . . . 22m as output buffer 20 according to the embodiment of FIG. As large as .8 milliwatts,
The total power consumption of the output buffer 22 with 18 to 50 converters is as large as 68.4 to 190 milliJ watts.

From the above data, the number of converters is 18 and the manual buffer is 20.
21° internal logic block with 200 gates and 18 converters
In the output buffer 220 circuit device IC, the 37th
In the central part 1o of the semiconductor chip surface in the figure, 6.4% of the heat is generated, while in the comparative parts 1r, l*
-/s, A! 4 A total of 93.6 percent of the heat is generated.

Also, the input buffer 20 . of the converter 50 . Number of gates: 153
0 internal logic block 21. In a circuit device IC with an output buffer 22 having 50 converters, 15.8% of the total heat is generated at the central portion 1o of the semiconductor chip surface in Fig. MB2, and each side portion It -A't -1m-14 A total of 84.2 percent heat is generated.

By the way, as shown in FIG. 37, the internal logic block 21, which generates a small amount of heat, is placed in the center of the Tera 1, and the input buffer 20 and output buffer 22, which generate a large amount of heat, are located at each side of the chip. .

1*elsm Compared to the case where it is placed in No. 4, as shown in Fig. 38, a large amount of heat on each side Hrlte 1 mm 14 is generated by the tab lead L.
Not only is it taken out to the outside of the circuit device #, , IC (in the case where one lint board KIC is mounted on 11!, then the ground line of the printed circuit board) via the T and the lead part Li as a grounding lead, but also a large number of The outside of the circuit device IC (particularly when the printed circuit board KIC is mounted, the signal line and tOIA line of the printed circuit board) is exposed through the bond wire and each lead part...L64. be able to.

In contrast to the above embodiment, the input buffer 20 and output buffer 22, which generate the heat of the TIC, are arranged in the central part of the chip lf, and the central part! . It has been confirmed through calculations by the inventor that if the internal logic block 21 is arranged around the circuit device IC, a large amount of heat in the central portion 10 will not be easily extracted to the outside of the circuit device IC.

For the above reasons, the circuit device IC of the above embodiment can have a structure without heat dissipation fins. In addition, the circuit device 10 has a resin-sealed structure with holes, IC cost) Th
It has become possible to significantly reduce the amount.

FIG. 40 shows a logic semiconductor integrated circuit device IC and another TTL level cooking semiconductor integrated circuit device 401 t 402 according to the embodiment using the drawings of FIGS. 37N to 39.
. . 40 n , 501 to 505° 600 are mounted on a printed circuit board.

In the figure, a device [4] that outputs the '1' TL level is shown.
Each output of 01, 402...40n is connected to circuit device I.
The outputs of the circuit device 11e are supplied to the inputs of TTL input level devices 501...505.

Furthermore, by commonly connecting the output OUT of the circuit device IC and the output of the device 600,
executes parallel operation.

Circuit device IflcO input buffer power buffer 2
The heat generated by 2 and the large fiK is the ground line of the printed circuit board, try? It can be dissipated to the input signal line, input signal line, and output signal line.

Also, an enable signal E supplied to the output buffer 22
When N is set to low level, its output OUT, 0[J
'l'□...0[JTmtlTm-ting state is reached, and the input levels of devices t501, 502, and 503 are set to the output level of device 600.

In addition, the input buffer 20 and the device 40], 402...
Rumor: High speed can be obtained with the interface between the 4On and the internal Al1fi block 21 and input buffer 20.
A high speed is obtained at the interface between the internal blotter blocks of the output buffer 22, and a high speed is obtained at the interface between the internal blotter blocks of the output buffer 22.
... 505 and the output buffer 20 also provides high speed.

[Effects] According to the above embodiments, favorable effects can be obtained for the following reasons.

(1) MOS
Compared to a FET, a bipolar transistor has a small device size, a small output resistance, a large current amplification factor, and a large charging current or discharging current. ! Due to the effect that current is available, the propagation delay of the input level converter 114
1 and its output capacitance dependence can be reduced.

(2) In the input level converter 201, a transistor that performs majority carrier operation is connected between the base and collector of the bipolar transistor that is driven into the harmonic region.
Since the barrier diode is connected, the injection of minority carriers from the collector layer into the base layer can be reduced, so that the accumulation time can be reduced.

(3) Input level converter 20 according to a preferred embodiment
1, the drive transistor Q is connected via an MO8 buffer with high input impedance and voltage amplification function.
By transmitting the pace signal or collector coefficient of , to the pace of the charging phase bipolar output transistor Q, the operation speed of the output transistor Q, is increased due to the high input impedance and voltage layer @A function of this MOB buffer. be done.

(4) In the input level converter 201 according to the preferred embodiment, VC between the input terminal IN and the drive transistor Q is a PNP emitter follower transistor Q.
By connecting , and the PN junction diode D4, not only can the input voltage and hold voltage of the input level converter 2010 be set appropriately, but also the input impedance at that pace is improved due to the optical amplification effect of the transistor Q. Therefore, the influence of the output impedance of the TTL level signal source connected to the input terminal IN can be reduced.

(5) For charging or discharging the output load valve cover Cx of the output level converter 221 1: By configuring the output transistor to be executed by a bipolar transistor, the bipolar 2 transistor can be used even if the element size is small compared to the 18408FET. The output resistance is small, the current amplification factor is large, and a large charging current or discharge current can be obtained, so that the propagation delay time of the output level converter and its output capacitance dependence can be reduced.

(6) Output 7) In the level converter 221, 1. A Schittke barrier diode is connected between the base and the collector of the bipolar transistor driven into the saturation region, which performs majority carrier operation, so that the minority carriers are injected from the collector layer into the base layer. Since the storage time can be reduced, the storage time can be shortened.

In the output level converter 221 according to the preferred embodiment, a high input chi/beadance MO8 circuit is connected between the output of the internal logic block 21 and the drive transistor (+Lt). M
081i' E The current flowing from the gate of 'I' to the output of the internal logic block 21 can be reduced to a negligible level. It is possible to prevent a decrease in

(8) In the output level converter 221 according to the preferred example of included angles, the internal sum of the high input impedance MO8 circuit is
By providing the function of logically processing multiple output signals of the robot block, it is a master slice type or gate array type l11il physical conductor integrated circuit! ! Place I
Freedom of design of C t1i1. ditto can be done.

(9) Output level converter 2 according to preferred embodiment
21, a t-th control circuit is arranged to control the output terminals (JUT,
When the output terminal of the logic circuit and the output terminal of another logic circuit are not commonly connected, the level of this common output terminal can be set by the output of the other logic circuit.

(1) According to a preferred embodiment, an internal logic block 21 whose power consumption is reduced by being composed of a pure CM08 circuit or a 40M08 circuit is arranged in the center of the surface of the #-conductor chip, and a plurality of bipolar・Input level converter 2 that includes transistors and consumes a large amount of power
By arranging the output level converter 221 and the output level converter 221 at the periphery of the semiconductor chip surface, heat dissipation becomes easy. We were able to reduce costs.

aυ According to a preferred embodiment, since the logic semiconductor integrated circuit device IC has a resin-sealed structure, its cost can be reduced.

On the other hand, input terminal I of input level conversion ¥5201
Since N is not applied to the gate of the MOSFET but to the gate of the switch barrier diode D10 or the pace of the PNP transistor Q4, the breakdown strength against the surge voltage applied to the input terminal IN is Just in case you can improve.

The invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist of the invention. It goes without saying that there is.

For example, in the sixth cause, the human cover, 7720OL/Bell converter 201.202""20n, CL-CM
Executes OS level conversion and converts the level of output buffer 22 Wip221, 222-...22m is 0MO
It is also possible to use concentrated acids to perform 8-ECL level conversion. For this purpose, an input buffer 20. Internal logic block 21. Needless to say, it is sufficient to operate the output buffer 22 at the ground level and the negative itt source pressure -VIE. Furthermore, in the same way, in the sixth stage, the level converters 201 and 202 of the input buffer 2o=20
n#'iI''L-c Pvt o s level conversion is executed, and the level converters 221 and 2 of the output buffer 22
22=22mViCMOS-i''L level conversion can also be configured.

Furthermore, in the embodiments of FIGS. 14 to 21, FIGS. 23 to 26, and FIGS. 29 to 30, the PNP emitter follower transistor Q4 of FIG. P.N.
A junction diode D may also be added.

'! ft, M (JSPET (D ratio W/l, (7) per minute L
The reason for setting t3 is to make sure that the MOSFET channel length is 3 μm, and with improvements in photolithography, this channel length is now 2 μm.

The miniaturization is progressing from 1.5 μm to 1 μm or less.

Correspondingly, the ratio W/L will be smaller per minute.

However, as this miniaturization continues to drive down the dimensions of bipolar transistors, the epicenter of resistance within the circuit will also occur.

In addition, a large number of leads L, . . . Le from the anti-soil resin 301
The method of taking out No. 4 is also not limited to the embodiment shown in FIG. 39.

The outer shape of the restraining resin 301 is not rectangular but almost square, and there are many leads L from all four sides.

... Taking out L64 is more appropriate for downsizing the lead frame LT and circuit device IC, and improves the mounting density on the printed circuit board.

[Field of Application] The above description mainly describes the case where the invention made by the present inventor is applied to a logic semiconductor integrated circuit device, but is not limited thereto.

For example, on a semiconductor chip there is an input buffer 20° and an internal logic block 21. Not only the output buffer 22, but also the necessary *
Depending on the bipolar analog circuit.

MUS/Analog circuit, P channel length + OS/
Logic, N channel 8108 Logic, i”L
Needless to say, either the circuit or the ECL circuit can be placed on a semiconductor chip.

[Brief explanation of the drawing]

! Figure 1 shows a block diagram of a logic semiconductor integrated circuit device IC that was studied by the inventor of the present invention prior to the present invention, and Figure 2 shows an input buffer that was studied by the inventor of the present invention prior to the present invention. FIG. 3 shows the output capacitance dependence of the propagation delay time of the input buffer in FIG. 2, and FIG. 5 shows the output load capacitance dependence of the propagation delay time of the output buffer in FIG. 4, and FIG. 6 shows a block diagram of a logic semiconductor integrated circuit device according to an embodiment of the present invention. , Figures 7 and 8 are 0MO8, NA of the circuit device in Figure 6.
A circuit example of the ND gate 211 is shown, and the circuit device CMOS-No. in FIG. 9, FIG. 1O, and FIG.
11 and 12 show a circuit example of an S-8 flip-flop in the internal wIII logic block 21 of the circuit device shown in FIG. 6, and FIG. A circuit example of an 0MO8 gated S flip-flop in the logic block 21 of the circuit device shown in FIG. 2 shows the complete circuitry of the device 201. 32 to 34 and 36 show circuit diagrams of the level converter 221 of the output buffer 21 according to an embodiment of the present invention, and FIG. 35 shows the first and second propagation delay times 1PHL. FIG. 37 shows the layout of each circuit block on the surface of the semiconductor chip 1 of the logic semiconductor integrated circuit device according to the embodiment of the present invention; The figure is uninvented 81! A lead frame L of a semiconductor chip of a logic semiconductor integrated circuit device by application. FIG. 39 shows a completed diagram of the circuit device c in the embodiment of the present invention after being sealed with resin, and FIG. 1 shows a block diagram of an electronic system configured by mounting a circuit device according to an embodiment of the present invention and other circuit devices on a printed circuit board. Fig. Fig. Fig. ■ Fig. 14 Fig. 16 Fig. U Fig. Fig. Fig. 20/ Fig. 20 Fig. 22 Fig. 23 Fig. Fig. 25 Fig. 32 Fig. Z/2 Figure 26 Figure 27 Figure 30 Figure 34 Figure 39 Figure 40

Claims (1)

[Claims] 1. An electronic device comprising a driving semiconductor integrated circuit device and at least one driven electronic circuit device whose input is connected to an external output lead of the driving semiconductor integrated circuit device. In the system, the driving semiconductor integrated circuit device includes an internal logic block including at least a CMOS circuit;
an output circuit including a bipolar transistor that leads an output of the internal logic block to the external output lead. 2. In an electronic system comprising a driving electronic circuit device and a driven semiconductor integrated circuit device whose external input lead is connected to the output of the driving electronic circuit device, the driving electronic circuit device comprises: , at least a first bipolar transistor for deriving an output signal of a predetermined output logic level to its output, and the driven semiconductor integrated circuit device has an input section connected to the external input lead, and an output section connected to the first bipolar transistor. an input level conversion circuit including at least a second bipolar transistor outputting a logic level different from a predetermined output logic level; and at least a CMOS circuit;
An electronic system comprising: an internal logic block that receives the output of the input level conversion circuit at its input.