JPH02224369A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To realize a circuit which can operate as designed and be manufacture high in yield by a method wherein the active layers of two types of FETs, E-FET and D-FET, are formed through the same process. CONSTITUTION:In a semiconductor device provided with two types of FETs with different threshold voltages, an enhancement FET(E-FET) and a depression FET(D-FET), in the same chip, both the FETs have a first conductivity type active layer respectively formed in the same ion implantation process executed only once. The E-FET whose threshold voltage is lower than that of the other has a second conductivity type injection layer under the active layer, and the gate length of the E-FET is shorter than that of the D-FET. That is, the active layers of both the E-FET and the D-FET are formed in the same process. By this setup, as the process variation of two types of FETs in threshold voltage occurs in the same direction, the variation of the threshold voltage hardly impedes a circuit operation, and processes can be reduced in number.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and is particularly used for semiconductor logic circuits using Schottky gate field effect transistors (MESFETs).

[Conventional technology]

In recent years, integrated circuits using compound semiconductors such as gallium arsenide (GaAs) have attracted attention due to their high-speed, high-frequency operation and low power consumption, and their application to digital circuits is being actively promoted. In compound semiconductor circuits such as GaAs, the transistors are often composed of MESFETs, unlike in the case of silicon (St). Regarding logic gates, which are extremely important circuit elements of digital integrated circuits, various circuits using MESFETs are known.

Figure 2 shows one of the conventional typical circuits using MESFET.
FIG. 2 is a circuit diagram of an inverter circuit using an edPET Logic circuit. As shown in the figure, a depletion type FET (D-FET) for a load is connected to an enhancement type FET (E-FET) for driving, and an input signal IN is applied to the gate of the E-FET.

Then, an output signal OUT is taken out from the connection point between the D-FET and the E-FET. Since this circuit has a simple configuration, it is widely used in large-scale integrated circuits.

Such a circuit uses two types of F with different threshold voltages.
ET (E-FET, D-FET) is required, and this difference in threshold voltage is realized by changing the active layer of the FET. The first method is to adjust the dose and acceleration energy of implanted ions for forming the active layer, and the second method is to adjust the dose and acceleration energy of implanted ions to form the active layer. This forms an injection layer of opposite conductivity type. Second
According to this method, leakage current to the substrate side is prevented when the gate length is shortened, and therefore the performance of the FET with the short gate can be improved. This is BP (buriedP−
This is called the 1ayer) technology and is particularly effective when increasing the driving capability of large-scale integrated circuits.

[Problem to be solved by the invention]

However, since the active layers of the two types of FETs manufactured by the first and second methods are formed by different ion implantation processes, there is a drawback that their threshold voltages vary. Therefore, there was a problem to be solved in that it became difficult to operate the logic circuit according to the designed value. Furthermore, the ion implantation process for forming the active layer is required for each FET and must be performed twice, which is one of the reasons for the increase in the number of steps. Furthermore, in the FET according to the second method, B
FET with no injection layer formed using P technology (D-F
ET), when the gate length is shortened, a short channel effect as shown in FIG. 3(A) tends to occur, and due to an increase in drain conductance, it may no longer function as an active load.

[Means to solve the problem]

The present invention provides a semiconductor device having two types of FETs (E-FET and D-FET) with different threshold voltages in the same chip, in which both FETs are formed by the same single ion implantation process. These FETs include an active layer of a first conductivity type and have a shallower threshold voltage (E-FET), which further includes an injection layer of a second conductivity type below the active layer, and has a gate length is something else (D
-FET).

[Effect]

According to the present invention, there are two types of FETs (E-FETs).

Since the active layers of each of the D-FETs are formed through the same process, process fluctuations in the threshold voltages of the two types of FETs will appear in the same direction, so they will not significantly impede the operation of the circuit. The number of steps can also be reduced. In addition, FET with deep threshold voltage (D-FET
) also suppresses the short channel effect.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention in which a DCFL circuit is constructed, according to manufacturing steps.

In an example of the semiconductor device of the present invention, as shown in FIG.
-FET and a driving E-FET. These FETs have an n-type active layer 11 and an n+-type contact region 12 in a substrate 1, and further have a gate electrode 3G in Schottky contact on the n-type active layer 11, and a source in ohmic contact on the n-type contact region 12. It is configured with an electrode 3S and a drain electrode 3D. And E-FE
Only for T, there is a p-type injection layer 1 under the n-type active layer 11.
3 is formed.

The first characteristic of the present invention is that the n-type active layers 11 of the E-FET and D-FET are both formed through the same process.

Therefore, the number of injection steps can be reduced from two to one. Further, even if the threshold voltage of the FET deviates due to various conditions in the ion implantation process when forming the n-type active layer 11, this deviation similarly occurs in the same direction for the E-FET and the D-FET. Therefore, these FE
The operation of a DCFL circuit or the like made of a combination of T is not significantly hindered. The second characteristic is that the gate length of the E-FET having the p-type injection layer 13 is shorter than that of the D-FET. As a result, while the gate length of the E-FET, which is not likely to cause a short channel effect due to BP technology, can be sufficiently shortened, the gate length of the other D-FET can be sufficiently shortened to the extent that the short channel effect does not occur. I have it.

The semiconductor device of the present invention is manufactured, for example, through the steps shown in FIGS. 1(a) to 1(f).

First, a substrate 1 made of, for example, semi-insulating GaAs is prepared, and a photoresist film is applied thereto by a spin coating method or the like. Then, patterning is performed using a photolithography technique to form a first mask 21 having openings in the E-FET and D-FET formation regions. Here, the opening of the D-FET for active load is changed to the E-FET for drive switching.
Make it larger than the FET aperture. Then, an n-type impurity is ion-implanted through this first mask 21 to form an n-type active layer 11 (as shown in FIG. 1(a)). Next, the first mask 21 is removed by dipping in acetone or ashing,
Apply a photoresist film again and buttering each F.
The second mask 22 has an opening in the area where the ET contact region is to be formed.

Then, n-type impurities are ion-implanted at a high concentration through this second mask 22 to form each F-contact region 12.
ET (as shown in FIG. 1(b)).

Next, the second mask 22 is removed, and a photoresist film is applied again and patterned to form a third mask 23 having an opening only in the E-FET formation region. Then, an n-type impurity is ion-implanted through the third mask 23, and a p-type impurity is ion-implanted.
A mold injection layer 13 is formed (as shown in FIG. 1(C)). In this way, while forming the n-type active layer 11 in the same process for both E-FET and D-FET,
A p-type injection layer 13 is formed only for the E-FET.

Next, the third mask 23 is removed and annealing is performed,
Activate the ion implantation layers 11, 12, and 13 (see Figure 1 (
d) As shown). Thereafter, a source electrode 3S and a drain electrode 3D made of ohmic metal are formed by a lift-off method (as shown in FIG. 1(e)), and then gate electrodes 3GE and 3GD made of Schottky metal are formed. Here, the gate length of the gate electrode 3GE of the E-FET is made shorter than that of the gate electrode 3GD of the D-FET. Specifically, the gate electrode 30E has a gate length of 1 μm or less, and the gate electrode 3GD has a gate length of 1 μm or more (see FIG.
f) As shown). This completes the basic structure of the present invention.

According to the above-mentioned manufacturing process, not only can semiconductor devices be manufactured with high yield against fluctuations in FET threshold voltage due to process fluctuations, but also cost reduction can be achieved by reducing the number of steps. Further, the characteristics of the D-FET for active load, which is likely to cause short channel effects, can be improved. For example, E.
'When the gate length of both D-FETs is 0.5 μm,
The IV characteristic of the D-FET has a short channel effect as shown in Figure 3 (A), but the E-FET has a gate length of 0.5.
If the gate length of μm5D-FET is 1.5 μm, D-
The FET (7) IV characteristics are as shown in Figure 3 (B),
Short channel effect can be suppressed.

〔Effect of the invention〕

As explained above in detail, the present invention uses two types of FETs.
Since the active layers of each (E-FET, D-FET) are formed through the same process, it is possible to make the process fluctuations of the threshold voltages of the two types of FETs in the same direction, and therefore the logic operation is It won't have a big impact. Further, it is possible to prevent the drain conductance from increasing due to short channel effect occurring in the FET serving as an active load.

Therefore, it is possible to operate according to the design value, and CF
L circuits etc. can be realized with high yield.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a DCFL circuit, and FIG. 3 is a diagram showing a short channel effect. 1...Substrate, 3S...Source electrode, 3D...Drain electrode, 3GE, 3GD...Gate electrode, 11...
・N-type active layer, 12...n-type contact region, 13
...p-type injection layer, 21-23...mask. Patent Applicant Sumitomo Electric Industries Co., Ltd. Representative Patent Attorney Yoshiki Hase Yoshiki Buying G11 Niga (Compensation Rod Sho Diagram <2) School 1 Furnace S Me = Yogi! (Maehira) (InD(, 7'L supination 2nd figure FETa lobe method 3rd figure

Claims (1)

[Claims] 1. In a semiconductor device having two types of FETs having mutually different threshold voltages in the same chip, the two types of FETs have different threshold voltages.
The ET includes an active layer of a first conductivity type formed by the same ion implantation process, and the type with a shallower threshold voltage of the two types of FETs has a second conductivity type active layer below the active layer. A semiconductor device further comprising a conductive type injection layer and having a gate length shorter than that of other types of FETs. 2. The FET that includes the injection layer is an enhancement type with a gate length of 1 μm or less, and the FET that does not include the injection layer
2. The semiconductor device according to claim 1, wherein is a depression type semiconductor device having a gate length of 1 μm or more.