JPH043922A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH043922A
JPH043922A JP10594890A JP10594890A JPH043922A JP H043922 A JPH043922 A JP H043922A JP 10594890 A JP10594890 A JP 10594890A JP 10594890 A JP10594890 A JP 10594890A JP H043922 A JPH043922 A JP H043922A
Authority
JP
Japan
Prior art keywords
layer
drain electrode
source electrode
ohmic
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10594890A
Other languages
Japanese (ja)
Inventor
Takahiro Kawabata
川端 隆弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP10594890A priority Critical patent/JPH043922A/en
Publication of JPH043922A publication Critical patent/JPH043922A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain a semiconductor device, in which the resistance of an ohmic junction is lowered, by ohmic-joining a source electrode and a drain electrode on a Ge implantion layer formed in an active layer in an ohmic-joined position. CONSTITUTION:In a MES FET, Ge implantion layers 9 are formed on an active layer 2 in positions, where a source electrode 3 and a drain electrode 4 are ohmic-joined, and the source electrode 3 and the drain electrode 4 composed of the two layers of an AuGe layer 6 and an Ni layer 7 are formed on the Ge implanted layers 9, but trivalent Ga and pentavalent As bond in a latticed manner in the active layer 2. Since crystallizability is damaged when Ge ions are implanted but recrystallization can be accomplished by executing heat treatment and the positions of Ga are replaced with partial Ge ions and N-type impurities are formed, AuGe and Ni constituting the source electrode 3 and the drain electrode 4 are evaporated onto the Ge implanting layers 9, to which N-type impurities are formed. Ge in AuGe is diffused easily into the Ge implanted layer 9 and alloyed through heat treatment, and an ohmic junction having low resistance is shaped. Accordingly, a semiconductor device in which the resistance value of a junction section is lowered is acquired.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置、特にMES (■etalse
miconductor ) F E Tの製造方法に
関し・詳しくは、ソース電極及びドレイン電極のオーミ
ック特性を向上させたMES  FETの製造方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, particularly MES (■etalse
The present invention relates to a method for manufacturing a MES FET with improved ohmic characteristics of a source electrode and a drain electrode.

〔従来の技術〕[Conventional technology]

例えば、高周波でハイパワーが要求される衛星通信には
、優れた高周波特性をもつMES  F−ETが使用さ
れる。MES  FETは、金属と半導体とのショット
キー接合により形成されるF−ETで、その構造を第4
図に示す、MES  F−ETは、半絶縁性GaAsの
基板(1)上に、n型不純物イオンを導入して電流が流
れる活性層(2)を形成し、その活性層(2)上に、ソ
ース電極(3)とドレイン電極(4)とをオーミック接
合し、また前記ソース電極(3)とドレイン電極(4)
との間にゲート電極(5)をショア)キー接合したもの
である。ソース電極(3)とドレイン電極(4)は、活
性層(2)とオーミック接合するAuGe層(6)と、
Ni層(7)との二層で構成される。オーミンク接合は
、AuGe−Niを活性層(2)に蒸着した後、熱処理
をすることにより、AuGe−Niと活性層(2)とが
合金化したものである。他方、ショットキー接合される
ゲート電極(5)は、金属を活性層(2)に接合しただ
けのものであり、ゲート電極(5)直下の活性層(2)
には、空乏層(8)が形成される。空乏層(8)は、キ
ャリアの存在しない領域で、ゲートルソース間に逆バイ
アス電圧を加えることにより空乏層(8)の領域が拡大
する。
For example, MES F-ET, which has excellent high frequency characteristics, is used in satellite communications that require high frequency and high power. MES FET is an F-ET formed by a Schottky junction between a metal and a semiconductor, and its structure is
In the MES F-ET shown in the figure, n-type impurity ions are introduced into a semi-insulating GaAs substrate (1) to form an active layer (2) through which current flows. , the source electrode (3) and the drain electrode (4) are ohmically connected, and the source electrode (3) and the drain electrode (4)
A gate electrode (5) is connected by a Shore key. The source electrode (3) and the drain electrode (4) have an AuGe layer (6) in ohmic contact with the active layer (2),
It is composed of two layers: Ni layer (7). In the ohmink junction, AuGe-Ni and the active layer (2) are alloyed by heat treatment after depositing AuGe-Ni on the active layer (2). On the other hand, the gate electrode (5) to be Schottky bonded is simply a metal bonded to the active layer (2), and the active layer (2) directly below the gate electrode (5)
A depletion layer (8) is formed therein. The depletion layer (8) is a region where carriers do not exist, and the region of the depletion layer (8) is expanded by applying a reverse bias voltage between the gate and the source.

いま、ドレイン−ソース電圧を印加すると、活性層(2
)内のキャリアによって、ドレイン−ソース電流が流れ
る。このドレイン−ソース電流は、空乏層(8)の厚さ
を変化することによって、増減することができる。空乏
層(8)の厚さは、ゲートルソース間の逆バイアス電圧
を増減させることによって変化する。従って、ドレイン
−ソース電流は、逆バイアス電圧を変化することによっ
て制御することができる。
Now, when a drain-source voltage is applied, the active layer (2
) causes a drain-source current to flow. This drain-source current can be increased or decreased by changing the thickness of the depletion layer (8). The thickness of the depletion layer (8) is varied by increasing or decreasing the reverse bias voltage between the gate and source. Therefore, the drain-source current can be controlled by changing the reverse bias voltage.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ソース電極(3)及びドレイン電極(4)は、n型不純
物を導入した活性層(2)にオーミック接合することに
より、ドレイン−ソース電流が流れるようにしている。
The source electrode (3) and the drain electrode (4) are ohmically connected to the active layer (2) into which n-type impurities are introduced, so that a drain-source current flows.

従って、オーミック接合における抵抗値が小さい程、ド
レイン−ソー入電流を効率よく流すことができる。特に
、高周波でハイパワーが要求される衛里通信用のMES
F−ETにあっては、大電流のドレイン−ソース電流が
流れることから、オーミック接合における抵抗値が大き
いと、発熱等のロスが生ずる。
Therefore, the smaller the resistance value in the ohmic junction, the more efficiently the drain-saw input current can flow. In particular, MES for satellite communication, which requires high frequency and high power.
In the F-ET, a large drain-source current flows, so if the resistance value in the ohmic junction is large, losses such as heat generation will occur.

そこで、本発明はソース電極及びドレイン電極のオーミ
ック接合を低抵抗化した半導体装置の製造方法を提供す
ることを目的とする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the resistance of the ohmic junction between a source electrode and a drain electrode is reduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は上記目的を達成するため、半絶縁性の基板(1
)上にn型不純物を導入した活性層(2)に、AuGe
−Niのソース電極(3)及びドレイン電極(4)をオ
ーミック接合し、前記画電極(3)(4)間にゲート電
極(5)をシツートキー接合した半導体装置の製造方法
において、ソース電極(3)及びドレイン電極(4)を
オーミック接合する位置の活性層(2)に、Ge注入層
(9)を形成し、前記Ge注入層(9)上に、ソース電
極(3)及びドレイン電極(4)をオーミック接合する
ことを特徴とするものである。
In order to achieve the above object, the present invention has a semi-insulating substrate (1
) with n-type impurities introduced into the active layer (2), AuGe
-Ni source electrode (3) and drain electrode (4) are ohmically bonded, and a gate electrode (5) is seat-key bonded between the picture electrodes (3) and (4). ) and the drain electrode (4), a Ge injection layer (9) is formed in the active layer (2) at a position where ohmic contact is made between the source electrode (3) and the drain electrode (4). ) is characterized by ohmic connection.

〔作用〕[Effect]

Ge注入層上に、ソース電極及びドレイン電極を構成す
るAuGeを蒸着すると、AuGeのGeが容易にGe
注入層に拡散されて合金化する。従って、ソース電極及
びドレイン電極がGe注入層にオーミック接合される抵
抗値は小さくなる。
When AuGe constituting the source and drain electrodes is deposited on the Ge injection layer, the Ge in the AuGe easily becomes Ge.
It is diffused into the injection layer and alloyed. Therefore, the resistance value of the ohmic contact between the source electrode and the drain electrode and the Ge injection layer becomes small.

〔実施例〕〔Example〕

本発明に係る一実施例を第1図乃至第3図を参照して説
明する。但し、従来と同一部分は同一符号を附して、説
明を省略する。
One embodiment of the present invention will be described with reference to FIGS. 1 to 3. However, the same parts as the conventional ones are given the same reference numerals, and the explanation is omitted.

本考案に係るMES  FETは、ソース電極(3)及
びドレイン電極(4)をオーミンク接合する位置の活性
層(2)上にGe注入層(9)を形成することを特徴と
する。即ち、このGe注入層(9)上に、AuGe層(
6)とNi層(7)の二層からなるソース電極(3)及
びドレイン電極(4)を積層する。
The MES FET according to the present invention is characterized in that a Ge injection layer (9) is formed on the active layer (2) at a position where the source electrode (3) and the drain electrode (4) are connected to each other through ohmink contact. That is, on this Ge injection layer (9), an AuGe layer (
A source electrode (3) and a drain electrode (4) consisting of two layers, 6) and a Ni layer (7), are laminated.

ところで、活性層(2)は、平面的に表わすと、第2図
に示すように、3価のGaと5価のA3とが格子状に結
合したものである。このような活性層(2)に、Geイ
オンを注入すると、結晶性が損なわれるが、熱処理を施
こすことにより再結晶化され、第3図に示すように、一
部のGeイオンがGaの位置に置換される。Geは4価
の原子であり、Gaは3価の原子であるから、Geイオ
ンがGaの位置に置換されると、電子が余り、n型不純
物が生成される。このように、Geイオンの注入により
、活性層(2)のAuGe中にn型不純物が生成された
Ge注入層(9)上に、ソース電極(3)及びドレイン
電極(4)を構成するAuGeとNiを蒸着する。熱処
理することによりAuGeのGeは、Ge注入層(9)
中のGeにより、容易にGe注入層(9)中に拡散され
て合金化し、低抵抗なオーミック接合が形成され、ソー
ス電極(3)及びドレイン電極(4)が完成する。
By the way, the active layer (2), when expressed in plan, is a combination of trivalent Ga and pentavalent A3 in a lattice shape, as shown in FIG. When Ge ions are implanted into such an active layer (2), the crystallinity is impaired, but they are recrystallized by heat treatment, and as shown in Figure 3, some Ge ions become Ga ions. replaced in position. Since Ge is a tetravalent atom and Ga is a trivalent atom, when a Ge ion is substituted at the position of Ga, electrons are left over and an n-type impurity is generated. In this way, the AuGe that forms the source electrode (3) and the drain electrode (4) is placed on the Ge implanted layer (9) in which n-type impurities are generated in the AuG of the active layer (2) by implantation of Ge ions. and evaporate Ni. By heat treatment, the Ge of AuGe becomes a Ge injection layer (9)
Due to the Ge contained therein, it is easily diffused into the Ge injection layer (9) and alloyed to form a low resistance ohmic junction, thereby completing the source electrode (3) and drain electrode (4).

〔発明の効果〕〔Effect of the invention〕

本発明によれば、Ge注入層上にソース電極及びドレイ
ン電極をオーミック接合するため、接合部の抵抗値が減
少し、発熱等のロスが発生せず、大電流のドレイン−ソ
ース電流を効率よ(流すことができる。
According to the present invention, since the source electrode and the drain electrode are ohmically bonded on the Ge injection layer, the resistance value of the junction is reduced, no loss such as heat generation occurs, and a large drain-source current can be efficiently handled. (It can flow.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係るMES  FETの断面図、第2
図は、活性層の分子構造図、第3図はGe注入層の分子
構造図である。 第4図は従来のMES  FETの断面図である。 (1) 一基板、      (2) −活性層、(3
)・−ソース電極、   (4) −ドレイン電極、(
5) −ゲート電極、   (9) −Ge注入層。 a  As AS 基板1 2:f)−+牙暫
FIG. 1 is a cross-sectional view of the MES FET according to the present invention, and FIG.
The figure shows the molecular structure of the active layer, and FIG. 3 shows the molecular structure of the Ge injection layer. FIG. 4 is a cross-sectional view of a conventional MES FET. (1) one substrate, (2) -active layer, (3
)・-source electrode, (4) -drain electrode, (
5) -Gate electrode, (9) -Ge injection layer. a As AS Substrate 1 2:f)-+Fang

Claims (1)

【特許請求の範囲】[Claims] (1)半絶縁性の基板上にn型不純物を導入した活性層
に、AuGe・Niのソース電極及びドレイン電極をオ
ーミック接合し、前記両電極間にゲート電極をショット
キー接合した半導体装置の製造方法において、 ソース電極及びドレイン電極をオーミック接合する位置
の活性層に、Ge注入層を形成し、前記Ge注入層上に
、ソース電極及びドレイン電極をオーミック接合するこ
とを特徴とする半導体装置の製造方法。
(1) Manufacturing a semiconductor device in which a source electrode and a drain electrode of AuGe/Ni are ohmically bonded to an active layer doped with n-type impurities on a semi-insulating substrate, and a gate electrode is Schottky bonded between the two electrodes. In the method, a Ge injection layer is formed in the active layer at a position where the source electrode and the drain electrode are ohmically connected, and the source electrode and the drain electrode are ohmically connected on the Ge injection layer. Method.
JP10594890A 1990-04-20 1990-04-20 Manufacture of semiconductor device Pending JPH043922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10594890A JPH043922A (en) 1990-04-20 1990-04-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10594890A JPH043922A (en) 1990-04-20 1990-04-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH043922A true JPH043922A (en) 1992-01-08

Family

ID=14421068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10594890A Pending JPH043922A (en) 1990-04-20 1990-04-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH043922A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011136743A (en) * 2009-12-28 2011-07-14 Mieko Shishido Storage box

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011136743A (en) * 2009-12-28 2011-07-14 Mieko Shishido Storage box

Similar Documents

Publication Publication Date Title
JPH0371776B2 (en)
JPS5963767A (en) Semiconductor device
JPH0444328A (en) Semiconductor device and manufacture thereof
JPS5860574A (en) Manufacture of field-effect transistor
JPS6359272B2 (en)
JPS61208268A (en) Conductance modulation type semiconductor device
JP2688678B2 (en) Field effect transistor and method of manufacturing the same
JPH04225533A (en) Field-effect transistor
JPS59222966A (en) Semiconductor device
JPH04291966A (en) Schottky barrier semiconductor device
JPH03240243A (en) Manufacture of field effect type transistor
JPH0493038A (en) Field-effect transistor
JP3201447B2 (en) Semiconductor circuit device and method of manufacturing the same
JPS6332273B2 (en)
JPS61163666A (en) Manufacture of field-effect transistor
JPH01243591A (en) Semiconductor device
JPS62202561A (en) Field effect transistor and its manufacture
JPH04218969A (en) Schottky barrier semiconductor device
JPS61144880A (en) Production of field effect transistor
JPH03231424A (en) Manufacture of compound semiconductor device
JPH0332062A (en) Electrode structure and semiconductor element using the electrode structure
JPH03136251A (en) Pn junction type field effect transistor and manufacture thereof
JPH03159178A (en) Manufacture of capacitive schottky diode
JPS61100973A (en) Manufacturing method of field effect transistor
JPS61222271A (en) Field effect transistor and manufacture thereof