JPH0222929A - Serial-parallel a/d converter - Google Patents

Abstract

PURPOSE:To obtain a serial-parallel A/D converter possible to perform a fast operation by performing A/D conversion in a period of one clock. CONSTITUTION:A reference voltage Vrc is compared with an input voltage Ws in a comparator Ai for high-order conversion, and the input voltage Vs is supplied to a comparator Bi for low-order conversion in the same period as that when a comparison operation is performed. A reference voltage Vrf for low-order conversion is formed corresponding to the result of comparison of the comparator Ai, and next, the reference voltage Vrf is compared with the input voltage Vs, then, an output code can be obtained from the output of those comparators Ai and Bi. The input voltage of the next sample is supplied to the comparator Ai while the comparison operation is performed in the comparator Bi, then, the same operation is repeated. Therefore, the operation of the A/D conversion can be performed in the period of one clock essentially. In such a way, the fast operation can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a series/parallel type A/D converter in which upper A/D conversion and lower A/D conversion are performed separately.

[Summary of the invention]

In this invention, a first reference resistor string that generates a plurality of first reference voltages for upper-level A/D conversion, and a plurality of first reference resistors that compare levels of the first reference voltages and an input signal are provided. a comparator, a second reference resistor string that selectively generates a plurality of second reference voltages for lower-order A/D conversion by the output of the first comparator, and a second reference voltage and an input signal. It includes a plurality of second comparators that compare levels, and a circuit that forms a digital output from the output signals of the first comparator and the second comparator. By configuring the second reference voltage and the input signal to be compared at the same time, both upper conversion and lower conversion can be performed in one clock period, and high-speed conversion operation is possible.

[Conventional technology]

As a conventional A/D converter, a fully parallel A/D converter with a high conversion speed is known. However, the fully parallel A/D converter requires 2 bits to perform n-bit A/D conversion.
``One comparator is required, resulting in problems of increased chip area and increased power consumption.

A series-parallel type A/D converter is known as an A/D converter capable of high-speed conversion next to a fully parallel type.

For example, when obtaining an 8-bit digital output, a series-parallel type A/D converter performs A/D conversion of the upper 4 bits, converts the output to D/A, and converts the input signal and D/A conversion output. This difference is converted into a 4-bit digital output by a lower A/D converter. Therefore, there is a problem in that a D/A converter and a differential amplifier circuit are required.

In order to solve such problems,
As described in Japanese Patent No. 426, a system has been proposed in which a reference voltage for upper-level conversion and a reference voltage for lower-level conversion are formed using a resistor circuit and a switching element. In this method, the D/A conversion circuit and the differential amplifier circuit can be omitted.

[Problem to be solved by the invention]

In the series/parallel A/D converter described in the above literature, a control signal is generated for the switching element after the upper A/D conversion output is obtained, and this control signal causes the resistance string for lower conversion to be changed. Due to the chosen configuration, a period of two clocks is required for the conversion operation, the conversion speed is inferior to the fully parallel type, and there is also the problem of requiring one sample hole circuit on the input side. was there.

Therefore, it is an object of this invention to
An object of the present invention is to provide a series-parallel type A/D converter that can perform D conversion and can operate at high speed.

[Means to solve the problem]

In this invention, a first reference resistor array 11 that generates a plurality of first reference voltages for upper-level A/D conversion, and a plurality of first reference resistors that compare levels of the first reference voltage and an input signal are provided. comparator Al, and a plurality of second reference voltages for lower A/D conversion.
The second signal selectively generated by the output of the comparator At of
A plurality of second comparators Bi compare the levels of the second reference voltage and the input signal, and form a digital output from the output signals of the first comparator At and the second comparator Bi. The second comparator Bl receives the input signal first, and
Next, the second reference voltage and the input signal are compared.

[Effect]

The comparator At for upper conversion first receives the first reference voltage Vrc, then receives the input voltage VS, and compares the reference voltage Vrc and the input voltage Vs. The input voltage Vs is supplied to the comparator B1 for lower conversion in the same period as the period in which this comparison operation is performed. A reference voltage Vrf for lower conversion is formed according to the comparison result of the comparator Ai, and this reference voltage Vrf and the input voltage Vs are then compared. An output code is obtained from the outputs of these comparators Al and Bi. When comparator B1 is performing comparison operation, comparator At
The input voltage of the next sample is supplied to , and the same operation as described above is repeated.

Therefore, the A/D conversion operation is performed substantially in one clock period, and high-speed operation is possible.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of this embodiment.
is an upper conversion circuit, and 2 is a lower conversion circuit. An input signal (voltage Vs) is supplied to the upper conversion circuit 1 and the lower conversion circuit 2 from an input terminal 3. 4 and 5 are power supply terminals to which reference DC voltages vh and Vf (Vh>Vj) are supplied, respectively.These DC voltages vh and v2 are supplied to the upper conversion circuit 1 and the lower conversion circuit 2, respectively. A reference voltage is formed by the provided resistor string.

For example, a 4-bit output signal from the upper conversion circuit 1 and a 4-bit output signal from the lower conversion circuit 2 are supplied to an encoder 6. The encoder 6 is provided to convert an 8-bit code consisting of 4-bit codes into a specific code (for example, a Gray code), and to perform error correction code encoding processing on the 8-bit code. . An output signal of the A/D conversion is obtained at the output terminal 7 of the encoder 6. The encoder 6 may be a circuit that simply outputs the output from the upper conversion circuit 1 and the output from the lower conversion circuit 2 as an 8-bit code.

Further, a resistor matrix 8 is provided, and a control signal corresponding to the output code of the upper conversion circuit 1 is supplied to the resistor matrix 8 . Resistance matrix 8 selectively generates a reference voltage for lower-order conversion according to the control signal, and this reference voltage is supplied to lower-order conversion circuit 2 .

Further, the upper conversion circuit 1 is supplied with a clock signal from a terminal 9, and the lower conversion circuit 2 is supplied with a clock signal from a terminal 10. These clock signals are used to operate chipper type comparators provided in each of the upper conversion circuit 1 and the lower conversion circuit 2.

FIG. 2 shows a specific configuration for performing 8-bit A/D conversion. The upper conversion circuit 1 compares a reference voltage formed by a resistor string 11 consisting of 16 resistors inserted in series between power supply terminals 4 and 5 and a signal voltage Vs from an input terminal 3. Comparators A1 to A1
5, and an upper encoder 12 to which the output signals of the comparators A1 to A15 are supplied. (17/2 R) or (17R) added to each resistor in resistor string 11
means relative resistance value. Comparators A1-A
15 generates an output of "1" when the input voltage Vs is higher than the respective reference voltage, for example.

A 4-bit output signal from the upper encoder 12 is supplied to the encoder 6. In addition, the line LO
A control signal for controlling the switching elements of the resistance matrix 8 is sent to L15. - For example, when the outputs of comparators A1 to A6 become "1" and the outputs of comparators A7 to A15 become "O", a 4-bit output code (0101) is generated from the upper encoder 11, and the line L6 A control signal of "1" is generated.The control signals sent to other lines other than L6 become "0".

The resistance matrix 8 is basically 16 series resistors further connected in series, and one of the 16 resistors is selected by a control signal from the upper encoder 12. For this purpose, each set of resistors is provided with comparators BO to B15 for lower-level conversion of the reference voltage generated at the connection point between the resistors.
A MOS-FET is provided for supplying the power. The gates of the FETs of each set of resistor matrix 8 are commonly connected and connected to line LO-L15. The control signal is “
The FETs connected to the 1'' line are simultaneously turned on, and the reference voltage is supplied to the comparators BO to B15 via the turned-on FETs.

(1) and R assigned to the resistance of the resistance matrix 8 are:
means relative resistance value.

The signal voltage Vs is supplied from the input terminal 3 to the comparator BO-815, and the output signals of the comparators BO to B15 are supplied to the lower encoder E3. The 4-bit output code generated from the lower encoder 13 is sent to the encoder 6.
supplied to

In this embodiment, the upward and downward transformations are substantially 1
Executes in clock time. If the comparator representing the above-mentioned upper conversion comparators A1 to A15 is A1, and the comparator 81 is representative of the lower conversion comparators BO to B15, then these comparators A
! and Bi have the configuration shown in FIG.

Comparator At consists of switches 21, 22 and 25, capacitor 23 and MOS inverter 24, and capacitor Bi similarly consists of switches 31, 32 and 35, capacitor 33 and MOS inverter . These comparators Al and Bi have a square-shaped configuration.

Switches 21, 22, 25, 31, 32.35 are MO
It is composed of S-FET. These switches are connected to clock signals φrc, φSC, φbc, φrf,
0N10FF control is performed by φsf and φbf. FIG. 4 shows the timing of these clock signals, and shows that the switch is ON during the period when the clock signal is “1”.
The switch is turned off during the period when the clock signal is "0".

Regarding the phases of clock signals φrc, φbc, and φrf,
The phases of clock signals φ3c, φ3f, and φbf are opposite to each other.

As will be described later, the comparator Ai for upper level conversion compares the reference voltage taken in at the timing R i-1 in FIG. 4 with the input voltage taken in at the timing Sl. In addition, in the comparator Bi for lower conversion, S
The input voltage taken in at timing i and the reference voltage taken in at timing R1' are compared. By repeating this operation, both upper and lower conversions are executed substantially in one clock cycle.

Since the input voltage Vs is taken into the upper conversion comparator Ai and the lower conversion comparator Bi at the same timing, there is no need for a sample and hold circuit to hold the input voltage Vs.

Furthermore, since the reference voltage is taken into the comparator Ai at the same timing as the comparison operation performed by the comparator Bi, the resistance circuit 11 that generates the reference voltage for upper conversion and the resistance matrix 8 that generates the reference voltage for lower conversion are provided separately.

Regarding the operation of the comparators Ai and Bi described above, the fifth
This will be explained in more detail with reference to the drawings. In Figure 5, T
s represents one period (sampling period) of the clock signal.

In the comparator At, the clock signal φ shown in FIG.
At re, the switch 21 is set to OIL, and the reference voltage Vrc for upper conversion from the terminal 41 is supplied to the capacitor 23. At the same time, the switch 25 is turned on by the clock signal φbe shown in FIG. 5A, the input and output of the MOS inverter 24 are short-circuited, and the MOS inverter 24 enters a high gain state in the period T1.

At the next timing, switches 21 and 25 are turned off.
L, the switch 22 is activated by the clock signal φsc shown in FIG. 5B.
turns on. Therefore, via the switch 22, the input terminal 3
, the input voltage Vs is supplied to the capacitor 23, and the period T
2, the reference voltage Vr is set by the MOS inverter 24.
A comparison operation is performed between c and the input voltage Vs.

Further, as shown in FIG. 5C, the clock signal φ3c is “
In the period T3 immediately after the period T2 within the period of 1 m, the upper encoder 12 outputs a control signal for setting the lower reference voltage. This control signal is supplied to the resistance matrix 8,
A reference voltage Vrf for lower conversion is generated.

In a period T4 having the same timing as this period T2, as shown in the fifth diagram, the clock signals φ3f and φbf are “1”.
”, therefore, switches 32 and 35 are ONL, .
The input voltage Vs is supplied to the capacitor 33 via the switch 32, and the input and output of the MOS inverter 34 are short-circuited by the switch 35, so that the MOS inverter 34 enters a high gain state. That is, the comparators At and Bi sample the input voltage Vs at the same timing.

During the next period T5 when the clock signal φrf becomes 11'' shown in FIG. , the input voltage Vs and the reference voltage rf are compared within this period Ts.

During this period T5, the clock signals φre and φbc (FIG. 5A) become "1", and the same operation as described above is repeated. Therefore, both upper conversion and lower conversion can be substantially performed in one clock cycle.

The comparator Bi for lower conversion described above first receives the input voltage Vs and then inputs the reference voltage Vrf for lower conversion to perform a comparison operation, so it has a function of holding the input voltage Vs during the period T5. It is necessary to have it. In other words, the comparator B1 has a chipper type configuration. on the other hand,
In the comparator At for upper conversion, the reference voltage Vr is first
Since the comparison operation is performed at the same time as c is input and the input voltage VS is manually applied, it is not limited to chipper type configurations.
Comparator A for upper conversion is a differential type comparator, etc.
It can be applied as t.

〔Effect of the invention〕

Since this invention has a series-parallel type configuration, it does not require a large number of comparators unlike the parallel type, and also does not require a differential amplifier circuit or a D/A converter, resulting in a small circuit scale and consumption. It has the advantage of using less power. In particular, the present invention can perform an A/D conversion operation in a period of substantially one clock, thus enabling a high-speed conversion operation.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the overall configuration of this invention;
The figure is a connection diagram showing the configuration of an example in which this invention is applied to 8-bit A/D conversion, FIG. 3 is a connection diagram used to explain an embodiment of this invention, and FIGS. 3 is a timing chart used to explain the operation of one embodiment. Explanation of main symbols in the drawings 1: Upper conversion circuit, 2: Lower conversion circuit, 3: Input terminal,
8: Resistance matrix, 11: Resistor string, Comparator for Al2 upper conversion, Bi: Comparator for lower conversion. Agent Patent Attorney Tadashi Sugiura 1st contribution / 7 books / 8-ta I) To main distribution Figure 3 Figure 5 ,, 78. ,-t,,i. Concert one evening, 9 pieces, Figure 4

Claims (1)

[Claims] A first reference resistor array that generates a plurality of first reference voltages for upper-level A/D conversion, and a plurality of resistor arrays that compare levels of the first reference voltages and input signals. a first comparator; and a second comparator that selectively generates a plurality of second reference voltages for lower A/D conversion based on the output of the first comparator.
a plurality of second comparators that compare the levels of the second reference voltage and the input signal; and a digital output from the output signals of the first comparator and the second comparator. A series-parallel type A circuit, wherein the second comparator is configured to receive the input signal first, and then compare the second reference voltage and the input signal. /D converter.