JPH022295B2 - - Google Patents
Info
- Publication number
- JPH022295B2 JPH022295B2 JP57050404A JP5040482A JPH022295B2 JP H022295 B2 JPH022295 B2 JP H022295B2 JP 57050404 A JP57050404 A JP 57050404A JP 5040482 A JP5040482 A JP 5040482A JP H022295 B2 JPH022295 B2 JP H022295B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- pattern
- resistance
- elements
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
本発明は互いに整合を必要とする抵抗体パター
ンを有する半導体装置、特に同一の周辺パターン
分布を要する抵抗体を複数個有する装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having resistor patterns that require matching with each other, and particularly to a method for manufacturing a device having a plurality of resistors that require the same peripheral pattern distribution.
例えば、半導体装置における抵抗体はフオトレ
ジスト等を用いた抵抗パターンを写真蝕刻法等に
より形成される。抵抗体の形成は熱拡散法、イオ
ン注入法またドープドオキサイド法等により選択
的に行なわれる。とくに抵抗パターンはマスクパ
ターンを用いてエツチングにより作られる。ボロ
ン、リン、アンチモンおよびヒ素等の不純物を導
入して抵抗領域を形成する方法も取られる。 For example, a resistor in a semiconductor device is formed by a resistive pattern using photoresist or the like by photolithography or the like. The resistor is selectively formed by a thermal diffusion method, an ion implantation method, a doped oxide method, or the like. In particular, the resistor pattern is created by etching using a mask pattern. A method of forming a resistance region by introducing impurities such as boron, phosphorus, antimony, and arsenic is also used.
電子回路上、特に特性が一致した、即ち整合を
必要とする半導体素子を形成する場合は、従来に
おいては不純物拡散時の層抵抗のばらつきおよび
拡散マスク製作時の素子寸法のばらつきの影響を
考慮して2つ以上の整合素子の配置をできるだけ
隣接させ、かつパターンの形状および方向性を同
一にするように配慮してパターン設計が行なわれ
ていた。 In electronic circuits, especially when forming semiconductor elements that require matching characteristics, conventional methods take into account the effects of variations in layer resistance during impurity diffusion and variations in element dimensions during diffusion mask fabrication. Pattern design has been carried out with consideration given to arranging two or more matching elements as close as possible and making the shapes and directions of the patterns the same.
しかしこの配慮だけでは十分な整合が得られな
かつた。これは写真蝕刻の際のパターン相互の干
渉による素子寸法の設計値に対するずれを補正す
ることが出来ないためと考えられる。すなわち写
真蝕刻技術においてマスクに描かれたパターンは
密着露光法あるいは投影露光法等によつてシリコ
ン基板上に塗布されたフオトレジスト(感光性樹
脂)に焼き付けられるが、この時素子パターン間
の間隔の広さが異なると、光が照射された部分が
光重合反応を起して硬化し、光が照射されない部
分が現像により除去されるネガタイプのフオトレ
ジストを使用した場合、マスクの暗部が素子パタ
ーンと一致する。従つて並列に並ぶ3個の抵抗体
を形成する際、抵抗パターン以外の部分に光が照
射される。このため平面的にみて左右両端に位置
する抵抗パターンより外側にある露光領域は抵抗
パターンによつてはさまれた部分(中央の抵抗パ
ターンの両側)の露光領域よりも広い。この結果
光の照射量が領域によつて異なつてしまい、外側
の領域には多くの光があたり重合度は密となる
が、パターン間の領域は照射量が少なく重合度が
粗になる。しかも微細化に伴つてパターン間隔が
狭くなる程その重合度は更に小さくなる。従つて
現像時の定着(リンス)処理において十分に重合
されなかつた部分(抵抗パターンによつてはさま
れた部分)が溶解されせまくなつてしまう。一
方、両端に位置する抵抗パターンの外側は十分に
重合されているため、上記の溶解は少ない。従つ
てどうしても中央の抵抗パターンの巾が両端のそ
れよりも広くなつて抵抗値にバラツキが生じてし
まう。 However, this consideration alone did not result in sufficient consistency. This is thought to be due to the inability to correct deviations in element dimensions from design values due to interference between patterns during photoetching. In other words, in photo-etching technology, a pattern drawn on a mask is printed onto a photoresist (photosensitive resin) coated on a silicon substrate by a contact exposure method or a projection exposure method, but at this time, the spacing between element patterns is If the areas are different, the areas irradiated with light will cause a photopolymerization reaction and harden, and the areas not irradiated with light will be removed by development.If you use a negative type photoresist, the dark areas of the mask will be different from the element pattern. Match. Therefore, when forming three resistors arranged in parallel, light is irradiated onto parts other than the resistor pattern. Therefore, when viewed in plan, the exposure area outside the resistor patterns located at both left and right ends is wider than the exposure area in the portion sandwiched by the resistor patterns (both sides of the central resistor pattern). As a result, the amount of light irradiation differs depending on the region, and the outer regions receive a lot of light and the degree of polymerization becomes dense, but the region between the patterns receives less irradiation and the degree of polymerization becomes rough. Moreover, as the pattern interval becomes narrower with miniaturization, the degree of polymerization becomes smaller. Therefore, in the fixing (rinsing) process during development, the portions that are not sufficiently polymerized (the portions sandwiched between the resistor patterns) are not dissolved. On the other hand, since the outside of the resistance pattern located at both ends is sufficiently polymerized, the above-mentioned dissolution is small. Therefore, the width of the resistance pattern at the center inevitably becomes wider than that at both ends, resulting in variations in resistance values.
一方、ポジ型レジストを使う場合、これは感光
された部分が除去されるので、マスクの明部が抵
抗パターンと一致する。従つてこの場合は露光さ
れるレジスト領域の面積は等しい。しかし抵抗パ
ターンによつて両側がはさまれた闇部に相当する
部分(中央の抵抗パターンの両側)へは隣接する
抵抗パターン(明部)からの光の回り込み、およ
び屈折した光の反射によつてパターン間がせまい
ために相互干渉をうけて不要に露光されてしま
う。一方、両端の抵抗パターンはその外側からの
光の影響を受けないため、不要露光は約半にな
る。その結果やはり中央の抵抗パターンの巾がそ
の両端の抵抗パターンの巾よりも広くなつてしま
い、抵抗値のバラツキが大きくなつてしまう。 On the other hand, when using a positive resist, the exposed areas are removed so that the bright areas of the mask match the resistor pattern. Therefore, in this case, the areas of the exposed resist regions are equal. However, the part corresponding to the dark part sandwiched on both sides by the resistor pattern (both sides of the central resistor pattern) is affected by the wraparound of light from the adjacent resistor pattern (bright part) and the reflection of refracted light. Since the distance between the patterns is narrow, mutual interference occurs, resulting in unnecessary exposure. On the other hand, since the resistor patterns at both ends are not affected by light from outside, unnecessary exposure is reduced to about half. As a result, the width of the resistor pattern at the center becomes wider than the widths of the resistor patterns at both ends, resulting in large variations in resistance values.
従つて従来の写真食刻法により例えば同一巾を
持つ3本のスリツトを平行に等間隔で並べた場
合、焼き付けられたレジストパターンでは中央の
スリツトの巾はその両側のスリツトの巾より広く
なる。このように従来整合を必要とする半導体素
子を形成する際考慮したパターンの配置だけでは
希望の整合が取れなくなる。さらにマスク製作時
におけるパターンの転写においても上記現像が起
こりマスクパターン自身も設計通りの寸法が得ら
れなくなり、パターン寸法の設計値からのずれを
増大させることになる。 Therefore, if, for example, three slits of the same width are arranged in parallel at equal intervals using conventional photolithography, the width of the central slit will be wider than the width of the slits on either side of it in the printed resist pattern. As described above, it is not possible to achieve the desired alignment by simply arranging patterns that have been considered when forming semiconductor elements that require alignment. Furthermore, the above-mentioned development occurs during pattern transfer during mask production, and the mask pattern itself cannot have the designed dimensions, increasing the deviation of the pattern dimensions from the designed values.
この発明の目的は著しく整合がとれた抵抗が得
られる構造の半導体装置の製造方法を提供するに
ある。 An object of the present invention is to provide a method for manufacturing a semiconductor device having a structure that provides extremely well-matched resistance.
本発明によれば互に整合されるべき抵抗体の周
辺パターン分布の条件が同一になるように本来の
抵抗パターンの外側に他に回路上何ら関係のない
非抵抗パターンが付加される。 According to the present invention, a non-resistance pattern which has no relation to the circuit is added outside the original resistance pattern so that the peripheral pattern distribution conditions of the resistors to be matched with each other are the same.
次に図面を参図してこの発明による半導体集積
回路装置の例を説明しよう。 Next, an example of a semiconductor integrated circuit device according to the present invention will be explained with reference to the drawings.
第1図は抵抗値が1:2の比であることが要求
される抵抗素子を形成する場合、同形、同寸法を
持つ3つの拡散抵抗素子A,B,Cが同一間隔で
平行に並べられて半導体基板に形成される。抵抗
素子A,Bの各一端部はアルミニウム配線1にコ
ンタクト部2,3をそれぞれ通じて接続され、他
端部は配線4にコンタクト部5,6をそれぞれ通
じて接続される。抵抗素子Cの両端部はそれぞれ
コンタクト部6,7を通じて配線8,9に接続さ
れる。抵抗素子A,B,Cは同形、同寸法であ
り、同一不純物濃度であるから、その各抵抗値を
Rとすれば配線1,4間の抵抗値はR/2、配線
8,9間の抵抗値はRとなる。しかしながら従来
においては抵抗素子A,B,Cを厳密に同形、同
寸法とすることができなかつた。 Figure 1 shows that when forming a resistance element that requires a resistance value ratio of 1:2, three diffused resistance elements A, B, and C having the same shape and dimensions are arranged in parallel with the same spacing. formed on a semiconductor substrate. One end of each of the resistive elements A and B is connected to an aluminum wiring 1 through contact parts 2 and 3, respectively, and the other end is connected to a wiring 4 through contact parts 5 and 6, respectively. Both ends of the resistance element C are connected to wirings 8 and 9 through contact portions 6 and 7, respectively. Resistance elements A, B, and C have the same shape, the same size, and the same impurity concentration, so if their respective resistance values are R, the resistance value between wires 1 and 4 is R/2, and the resistance value between wires 8 and 9 is R/2. The resistance value is R. However, in the past, it has not been possible to make the resistive elements A, B, and C exactly the same shape and size.
この発明においては抵抗素子A,B,Cの周辺
パターン分布が同一になるようにこれ等抵抗素子
A,B,Cと回路的に無関係の浮遊拡散領域D1,
D2が設けられる。拡散領域D1は抵抗素子Aの素
子Bと反対側において素子A,B間の間隔d1と同
一の間隔d1をもつて互に平行に対向して配され、
かつその長さl1は素子A,B,Cのそれと同一と
される。同様に抵抗素子Cの素子Bと反対側にお
いて間隔d1を保ち互に平行対向し、長さl1の浮遊
拡散領域D2が設けられる。領域D1,D2の巾は抵
抗素子A,B,Cの巾と同一にする必要はない。 In this invention, floating diffusion regions D 1 , which are unrelated to the resistive elements A, B, and C in terms of circuit so that the peripheral pattern distributions of the resistive elements A, B, and C are the same, are
D 2 is provided. The diffusion regions D 1 are arranged parallel to each other and facing each other with the same distance d 1 as the distance d 1 between the elements A and B on the opposite side of the resistance element A from the element B,
And its length l 1 is the same as that of elements A, B, and C. Similarly, floating diffusion regions D 2 having a length l 1 are provided on the opposite side of the resistance element C from the element B, parallel to each other and facing each other with a distance d 1 between them. The widths of regions D 1 and D 2 do not need to be the same as the widths of resistive elements A, B, and C.
上述の構成によれば抵抗素子A,BおよびCの
各パターンの周辺パターン分布の条件は全く同じ
となり、抵抗素子A,B,Cを形成するためのレ
ジストパターンと同時に浮遊領域D1,D2に対す
るレジストパターンも同時に形成され、このため
露光−現像時に受ける各素子A,B,Cに対する
影響は全く同一となり、同一寸法の抵抗素子A,
B,Cが得られ、素子A,Cの各巾より素子Bの
巾が大となるようなことはない。 According to the above configuration, the peripheral pattern distribution conditions of the respective patterns of resistive elements A, B, and C are completely the same, and the floating regions D 1 , D 2 are formed at the same time as the resist patterns for forming resistive elements A, B, and C. The resist pattern for each element is also formed at the same time, so that the effects on each element A, B, and C during exposure and development are exactly the same, and the resistive elements A, B, and C of the same size are
B and C are obtained, and the width of element B is never larger than each width of elements A and C.
第2図においては互に平行配列された抵抗素子
A,Bの外側に浮遊拡散領域D1,D2を形成し、
この抵抗素子A,Bの両端をそれぞれ配線1,4
に接続して並列抵抗とされる。これ等抵抗素子
A,Bと離してこれと整合されるべき抵抗素子C
が形成され、その際、抵抗素子Cの両側に浮遊拡
散領域D3,D4が同時に形成される。領域D1素子
A間、素子A,B間、素子B領域D2間、素子C
と領域D3及びD4との各間はすべて同一とされる。
この場合も抵抗素子A,B,Cの寸法を厳密に一
致させることができる。第3図は第1図において
浮遊領域D2の代りに他の素子Eが形成された場
合である。素子E及びC間の間隔はd1とされる。 In FIG. 2, floating diffusion regions D 1 and D 2 are formed outside of resistance elements A and B arranged in parallel to each other,
Wires 1 and 4 are connected to both ends of these resistance elements A and B, respectively.
It is used as a parallel resistor by connecting it to . A resistive element C that should be separated from and matched with these resistive elements A and B.
is formed, and at this time, floating diffusion regions D 3 and D 4 are simultaneously formed on both sides of the resistance element C. Area D 1 between elements A, between elements A and B, between element B area D 2 , element C
and areas D3 and D4 are all the same.
In this case as well, the dimensions of the resistive elements A, B, and C can be precisely matched. FIG. 3 shows a case where another element E is formed in place of the floating region D 2 in FIG. 1. The spacing between elements E and C is d 1 .
一例として抵抗パターン巾が10μパターン間隔
が10μの場合、東京応化工業(株)のネガレジスト
(OMR−83)を用い、シリコン酸化膜の厚さが
0.7μエツチング液としてフツ酸:フツ化アンモニ
ウムが1:6のバツフアードHFで形成した従来
の抵抗体では整合のバラツキが両端と中央とで2
〜5%あつたが、本実施例では1%以内だつた。
又、上述ではネガタイプのフオトレジストを用い
た場合の例であり、即ち例えば第1図においてパ
ターン形成工程の露光−現像後は、パターンA,
B,C,D1及びD2の部分にはレジストはなく、
その他の部分に露光されて重合したレジストが残
つているが、これと逆にパターンA,B,C,
D1,D2の部分に光照射され、その部分が除去さ
れるポジタイプフオトレジストを用いる場合にも
本発明は適用される。 As an example, if the resistor pattern width is 10μ and the pattern spacing is 10μ, use a negative resist (OMR-83) from Tokyo Ohka Kogyo Co., Ltd., and the thickness of the silicon oxide film is
In a conventional resistor formed using buffered HF with a ratio of fluoric acid and ammonium fluoride of 1:6 as a 0.7μ etching solution, the variation in matching between both ends and the center is 2.
5%, but in this example it was within 1%.
Moreover, the above is an example in which a negative type photoresist is used, that is, for example, in FIG. 1, after exposure and development in the pattern forming step, patterns A,
There is no resist in parts B, C, D 1 and D 2 ,
Resist that has been exposed and polymerized remains in other areas, but on the other hand, patterns A, B, C,
The present invention is also applicable to the case of using a positive type photoresist in which portions D 1 and D 2 are irradiated with light and those portions are removed.
第1図は本発明装置の一例である整合を必要と
する2つの抵抗素子を並べて配置した平面図、第
2図は整合を必要とする抵抗素子を単独に配置し
た場合の平面図、第3図は本発明装置の更に他の
例を示す平面図である。
A,B,C:素導体素子としての抵抗素子、
D1,D2,D3,D4:浮遊拡散領域。
Fig. 1 is a plan view of an example of the device of the present invention in which two resistance elements requiring matching are arranged side by side, Fig. 2 is a plan view of a case in which a resistance element requiring matching is arranged singly, and Fig. 3 The figure is a plan view showing still another example of the device of the present invention. A, B, C: resistance element as an elementary conductor element,
D 1 , D 2 , D 3 , D 4 : floating diffusion regions.
Claims (1)
拡散領域からなる第1の抵抗体を少なくとも2つ
以上同じ間隔で並列に配置した第1の抵抗群と、
前記幅と実質的に等しい幅をもつ帯状拡散領域か
らなる第2の長さを有する第2の抵抗体を少なく
とも1つ含む第2の抵抗群とを有し、前記第1の
抵抗群の両側に前記第1の抵抗体と前記間隔だけ
離れて並行する前記第1の長さ以上の長さをもつ
た第1の拡散領域を備え、前記第2の抵抗群の両
側に前記第2の抵抗体と前記間隔だけ離れて並行
する前記第2の長さ以上の長さをもつた第2の拡
散領域を備え、前記第1の抵抗体、前記第2の抵
抗体、前記第1の拡散領域および前記第2の拡散
領域をそれぞれ同じ製造工程で同時に形成するこ
とを特徴とする半導体装置の製造方法。1. A first resistor group in which at least two first resistors each consisting of a strip-shaped diffusion region having a substantially equal width and a first length are arranged in parallel at the same interval;
a second resistor group including at least one second resistor having a second length, which is made of a band-shaped diffusion region having a width substantially equal to the width, and on both sides of the first resistor group. a first diffusion region having a length equal to or greater than the first length, which is parallel to the first resistor and spaced apart from the first resistor, and the second resistor is provided on both sides of the second resistor group. a second diffusion region having a length equal to or greater than the second length, which is parallel to the body and separated by the distance, the first resistor, the second resistor, and the first diffusion region; and the second diffusion region are formed simultaneously in the same manufacturing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050404A JPS57202774A (en) | 1982-03-29 | 1982-03-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57050404A JPS57202774A (en) | 1982-03-29 | 1982-03-29 | Semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP48097567A Division JPS5947463B2 (en) | 1973-08-29 | 1973-08-29 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57202774A JPS57202774A (en) | 1982-12-11 |
| JPH022295B2 true JPH022295B2 (en) | 1990-01-17 |
Family
ID=12857923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57050404A Granted JPS57202774A (en) | 1982-03-29 | 1982-03-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57202774A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3382726D1 (en) * | 1982-06-30 | 1994-01-27 | Fujitsu Ltd | Integrated semiconductor circuit arrangement. |
| JP3028420B2 (en) * | 1988-09-05 | 2000-04-04 | セイコーエプソン株式会社 | Semiconductor integrated device |
| US6476695B1 (en) | 1999-05-26 | 2002-11-05 | Sharp Kabushiki Kaisha | High frequency module |
| JP4113199B2 (en) | 2005-04-05 | 2008-07-09 | 株式会社東芝 | Semiconductor device |
| WO2020203507A1 (en) * | 2019-04-01 | 2020-10-08 | パナソニックセミコンダクターソリューションズ株式会社 | Monolithic semiconductor device and hybrid semiconductor device |
-
1982
- 1982-03-29 JP JP57050404A patent/JPS57202774A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57202774A (en) | 1982-12-11 |
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