JPH02230362A - Digital arithmetic processing unit - Google Patents

Abstract

PURPOSE:To surely perform data transfer even when contention occurs in addresses by sending a standby signal to a processor having a standby function and making the processor make access to a shared memory preferentially while a fast processor without having the standby function makes access to the shared memory. CONSTITUTION:A digital signal processor(DSP) 1j is provided with a fast processing function compared with a universal processor. A memory(ROM) 1k to store the instruction of the DSP and a memory(dual port RAM) 11 to store data computed by the DSP are connected to a local bus 1q, and the DSP 1j makes access to it arbitrarily. And during that time, a data acknowledge signal is prolonged in point of time so as not to activate the data acknowledge signal for the processor (CPU) which can perform standby for the access to the dual port RAM 11. Thereby, since the standby of the access to the dual port RAM can be performed until the data acknowledge signal is activated, unstable data can be prevented occurring even when the contention occurs in the addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital arithmetic processing device, and in particular to data transfer that completely eliminates data collisions during address conflicts in dual-baud RAM in multiprocessor systems. The present invention relates to a digital arithmetic processing device equipped with means.

[Conventional technology]

Conventionally, in a multiprocessor system, when dual port RAM is accessed by two processors,
When there was an address conflict, the processor that accessed it later was made to wait. In addition, conventionally, general-purpose CPUs (for example, 68,000
．． 8086, etc.) was applied.

[Problem to be solved by the invention]

The above conventional technology is an arithmetic processing system that accesses dual-port RAM asynchronously, and a high-speed processor (DSP, etc.) that cannot wait for processor processing (memory access) is applied to one side, and the dual-port RAM is There was a problem in which data became undefined when the same address was accessed from both directions.

An object of the present invention is to provide a digital arithmetic processing device in which data is reliably transferred even when addresses conflict when a dual port RAM is accessed from both directions in a system having a DSP as described above. It's about doing.

[Means to solve the problem]

In a multiprocessor system, when the same address is accessed from dual-port RAM from both directions (one is a device that does not have the function of waiting for memory access like a DSP), the processor that has the function of waiting for memory access This is achieved by sending a signal from the DSP side to make memory access standby.

[Effect]

While accessing the dual port RAM, the DSP temporally adjusts the data acknowledge signal so as not to activate the data acknowledge signal for a processor (CPU) that can wait for access to the dual port RAM. Try to stretch it out.

Since the CPU waits to access the dual port RAM until the data acknowledge signal becomes active (until the DSP access ends), data will not become undefined even in the event of an address conflict.

〔Example〕

An embodiment of the present invention will be described below.

Figure 1 shows a unit of a digital protection relay device according to an embodiment of the present invention. In FIG. 1, a unit 100a receives an input signal inn (n=1.2,
-N), converts it into digital data, performs filter processing using digital calculations, and outputs the calculation results. The unit 100b is a unit having system control functions such as data transfer of the protection relay device and arbitration of the system bus shown in IW.

Here, the configuration of the unit 100a will be explained. l
a, lb, and 1c are low-pass filters (LPF) that remove harmonics superimposed on the input signal ilIn.
The LPF mainly prevents aliasing component errors due to sampling. ld, la and 1f are each LPF
This is a sample/hold circuit (S/H) that samples and holds the outputs of (la, lb, and lc) at the same time. 1g sequentially switches the data held by the S/H circuit and converts it to the analog/digital conversion circuit shown in 1h (
This is a multiplexer that inputs to the A/D). The A/D shown at 1h converts the analog input signal Inn into a digital signal Xn (n=1.2, . . . N) and stores it in the memory (RAM) shown at 11.

1j is a digital signal processor (DSP: Di
It is a digital signal processor) and has faster processing capabilities than general-purpose processors.

1k is the above DSP instruction (command word)
This is a memory (ROM) that stores. IQ is a memory (dual port RAM) that stores data calculated by DSP.
: bidirectionally accessible memory). RAM mentioned above
1 i , ROM 1 k, and RAMIQ are connected to a local bus indicated by 1 q, and are arbitrarily accessed by the DSP 1 j.

1m is an interface circuit with system bus 1w. in
is a gate circuit, and 1o is a counter circuit. 1p is the above-mentioned S/Hid~1f, MPX1g, A/Dih
, RAMI i and DSP1j.

1x is a data strobe (DS) signal given from the system control unit shown in 100b. 1y
is the serial output signal (So) from DSP1j, IZ
is the data acknowledgment (DT) for confirming data transfer to the system control unit of 100b
ACK) signal.

Next, each block in the system control unit 100b will be explained.

1r is a general-purpose CPU, which has a function of transferring data to each unit of the entire protection relay device (for example, an analog input unit, a relay calculation unit, a setting processing unit, a sequence processing unit, etc.). 1s is an interface circuit with the system bus 1w, 1t is the CPUI
r instruction memory (ROM), 1
u is a RAM, and 1v is a local bus of the system control unit 100b.

FIG. 2 shows a detailed diagram of the DSP 1j. As shown in the figure, an address register 22 for specifying addresses of external memory,
a data register 23 used as a parallel port;
Data RAM 24, m-bit x m-bit high-speed parallel multiplier 25, instruction ROM 26, ALU (Aritha+etic Logic U) that performs addition and subtraction, etc.
nit) 2 7, register 28 for accumulator etc.
, a control circuit 29 that controls interrupts of external control signals (a, b, C, etc.), and an internal bus 30 within the DSP 17.

The multiplier 25 multiplies the contents of the input signals A and B during one instruction cycle, and outputs the result C to the internal bus 30. As is well known, the DSP1j is characterized by being able to perform multiply-accumulate operations within one instruction cycle and by being able to perform pipeline processing, thereby realizing high-speed numerical operations on fixed and floating point data. shall be. This allows input data related to multiple input points to be filtered in real time. In this respect, general-purpose processors cannot be applied because their processing speeds are slow.

In addition, the DSP 1j has a serial register shown in 31, which stores serial input data (SI) and serial output data (
It has the feature of being able to input and output S○).

Further, in order to maximize the high-speed calculation function of a DSP, many DSPs operate so that all instructions are completed in one clock. Therefore, many devices do not have the function of making calculations and input/output operations wait using external information (for example, a Wait signal: a signal that causes calculations and input/output operations to wait).

FIG. 3 shows waveform examples of various parts to explain general problems caused by using the above-mentioned DSP. In FIG. 3, (a) is an address for writing data from the DSP side to the dual port RAM, and (b) is a write signal.

(C) is the address from the master CPU side, (d) is the address strobe signal, (e) is the mask write signal, (
f) is a data strobe signal.

Here, it is assumed that the master CPU reads the data at address A, but since it is selected at the same time as the write address A of the DSP, the data DA taken in by the mask CPU shown in (g)
becomes indeterminate. At this time, the slave (such as an analog input unit) outputs the data acknowledge signal (h) to the mask CPU after a period of time depending on the access time of the memory accessed by the master CPU. Therefore, problems such as malfunctions may occur due to undefined data.

The present invention completely eliminates the above-mentioned problems and prevents system malfunctions.

Below, the operation of the embodiment of the present invention will be explained along the flowchart shown in FIG.

(i) Analog input, A/D conversion LPEs 1a to 1c receive input signals 1n representing state quantities detected by sensors such as power system transformers and current transformers.
Enter 1 to 1 n. The LPEs 1a to 1c act as prefilters that prevent aliasing errors due to sampling. This filter output is S/H circuit 1d~1
The sample is held every period T by f. M.P.
X1g sequentially switches the S/H circuits 1d to 1f every cycle T', and inputs the contents of the S/H circuits 1d to 1f into the A/D conversion circuit 1h. The A/D conversion circuit 1h receives the input signal in1
~inn is converted from an analog quantity to a digital quantity x1~X,1, and these are stored in RAMIQ. These operations are repeated every cycle T. (ii) Initial processing (4a) As the initial processing, the internal memory (RA
M24 and register 28) and RAM li are initialized.

(iii) Data input (4b) The voltage/current signals stored in the RAM shown in FIG. 11 are transferred to the internal memory RAM 24 of the DSP 1j.

(iv) Filter coefficient input (4c) Filter coefficients necessary for digital filter calculation are transferred from other units to the internal memory 24 of the DSP 1j via the external ROM 1k or the system bus 1w.

(V) Digital filter operation (4d) Several methods can be specifically considered for the filter operation, and one example is the processing shown in the following equations (1) and (2).

Wn=KXn+Bt・Wn-t+Bz・Wn-z...
(1) Yn=Wn+Az-Wn-t+Az・Wn-z −(
2) K: Gain coefficient, AI, A2, Bl, B2: Filter coefficient xn: Input data Yn: Output data Wn-z: 1 time delay data of Wn Wn-z: 2 time delay data of Wn Voltage, current data The calculations are performed sequentially using a plurality of pieces of data, and the calculation results are stored in the internal RAM 24 of the DSP 1j. The configuration and characteristics of the digital filter will be explained in detail later.

(vi) Serial data output (1) (48) Before outputting the above digital filter operation result, serial data is output using the serial input/output function of the DSP 1j described above.

FIG. 5 shows a specific circuit example of the gate circuit and counter circuit shown in 1n and 10 of FIG. In Figure 5, SEL is the board (slave) select signal, DS
is the data strobe signal from master CPU1r, S○
is serial data from the DSP 1j, and DTACK is an acknowledge signal to the master CPU 1r.

5a is a NOR gate, 5b is an AND gate, 5c is a counter (shift register), and 5d is an open collector type NAND gate, and each gate circuit is well known.

Serial data ("L11 level") from the DSP 1j in FIG. 1 is applied to the S○ terminal of the AND gate in FIG. 5b.

By doing so, a signal of 11 L u level is applied to the input terminals A, B and CLR of the counter 5c, so the output terminal Q of the counter 5c becomes "L n" and 1o
The DTACK signal becomes “H”. Since this DTACK signal is "H", the master CPU of 1r in FIG.
defers the operation if it is currently reading (or writing). (Actually, wait until DTACK becomes “L”.) Therefore, the serial output from DSP1j is 11L,
By applying it to the SO terminal of the AND gate 5b, the operation of the master CPU 1r can be put into a waiting state. (vii) Data output (4f) DSP1j outputs digital filter calculation data to RAMIQ. (vii) Serial data output (2) (4 g) After completing the transfer of the digital filter calculation data in the 4f block, the serial data (゛'H” ) to (v
i) of the AND gate in FIG.
Apply to the terminal.

By doing so, the counter in FIG. 5c starts counting up, and after a predetermined time has elapsed, the output terminal Q becomes 11 H j#, and the DTACK signal becomes II
Therefore, since the data acknowledge signal is returned, the master CPU 1r performs the following processing.

(If reading is in progress, the operation is restarted.) The above-described operation is repeated every cycle T.

FIG. 6 shows waveforms of various parts showing the operation of the present invention.

The DSP 1j receives the address information shown in FIG. 6(a) and (b)
) outputs the write signal Wp shown in FIG.

Before that, apply serial data (“L”) to the So terminal, and as shown in (Q), set it to “L 71” during data transfer (while accessing RAM1u), and after transfer, II H Make it I+.

On the other hand, the master CPU 1r performs R asynchronously with the DSP 1j.
In order to access AM1Ω, address information is output at the timing shown in (d). Because it is accessed asynchronously, RAMIQ address A is accessed at the same time as DS.
It may be accessed from P1j and master CPU1r. Therefore, the content of the data when viewed from the master CPU 1r is undefined, but due to the So signal in (c),
As shown in (e), since the time for the DTACK signal to become II L I+ is extended, the data is determined after the DSP 1j completes the data transfer. Therefore, it is completely eliminated that the data becomes unstable due to address matching, and a highly reliable protection relay system can be constructed without causing malfunction of the protection relay system.

FIG. 7 shows a modified embodiment of the present invention.

In FIG. 7, only 7a and 7y are different from the block diagram shown in FIG.

7a is a dual port R with an interrupt signal generation function.
AM, and a detailed block is shown in FIG. 8a.

In 8a, Do=Dn is connected to a data path, and Ao-A is connected to an address bus. INT is dual port R
This is an interrupt signal generated from AM.

(Actually, the above INT signal becomes active by accessing a certain fixed address.) CS is a chip select signal, OE is an output enable signal,
WE is a write enable signal.

Next, the operation of the modified example will be explained.

In the embodiment shown in FIG. 1, an example has been described in which serial output data is applied from the DSP 1j to the 1n gate circuit. In the modified example, before outputting the filter operation data, instead of the serial output data, a certain fixed address is accessed so that the INT signal from the dual port RAM 7a becomes active ("L"). By doing so, the signal (I N"r) shown in FIG. 7 7y is output, and 1n
applied to the gate circuit.

In addition, in FIG. 7, the counter 1o receives DTACK from immediately after the gate circuit 1n becomes LtL"' until the DSP 1j accesses the dual port RAM 7a.
Therefore, the same effect as the embodiment shown in FIG. 1 is obtained.

Furthermore, a register circuit is provided, and dual port RAMI
While accessing Q, a signal of 11 L I+ level is applied to the 1n gate circuit by outputting "L" (actually 0) data from the DSP 1j to the register circuit.

Therefore, it is easy to understand that such a method also has the effects shown in FIG. 1 of the present invention.

In the present invention, an example of data transfer between an analog input unit and a system control unit has been described. Needless to say, it can also be applied.

〔Effect of the invention〕

According to the invention, an asynchronous and identical dual port RAM
When accessed by two processors, the data will not become undefined even if an address conflict occurs, so the protection relay system will not malfunction and its reliability can be improved.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment of the present invention, Figure 2 is a DSP
3 is a timing waveform diagram of each part during address conflict in dual port RAM, FIG. 4 is an operation flow diagram of an embodiment of the present invention, and FIG. 5 is an element circuit in an embodiment of the present invention. 6, AO to ATL are timing waveform diagrams of various parts during address conflict in the dual port RAM according to the present invention, FIG. 7 is a block diagram of a modified example of the embodiment of the present invention, and FIG. It is a block diagram. 1a, 1b, 1c - low-pass filter,
ld, le, if...sample hold circuit, 1g.
...Multiplexer, 1h...Analog/digital conversion circuit, 11...Random access memory, 1j...
...Digital signal processor, 1p...timing control circuit. 00~{)TL High 1 drawing rate S section High 6 drawing (1) Edo Shimata L A-N
A-N A (bl mute)
−“１ 『１１１（Cps0 (＋）士゜一タ9＾

Claims (1)

[Claims] 1. A high-speed processor without a standby function, a processor with a standby function, and a shared memory, which takes in data from a certain system and performs arithmetic processing at regular intervals according to a predetermined processing procedure. In the digital arithmetic processing device, while the high-speed processor without the standby function accesses the shared memory, a standby signal is sent to the processor with the standby function so that the processor with the standby function accesses the shared memory preferentially. A digital arithmetic processing device characterized by: 2. A digital arithmetic processing device comprising a high-speed processor without a standby function and a digital signal processor. 3. The digital arithmetic processing device according to item 2, wherein serial data is sent from the digital signal processor as the standby signal. 4. In the above item 1, a dual port RAM with an interrupt signal generation function is installed in the shared memory, and the processor without the standby function issues an interrupt signal to the shared memory, and this signal is used as a standby signal. A digital arithmetic processing device characterized in that it transmits data.